CN104377301A - III-V group compound semiconductor Hall element and manufacturing method thereof - Google Patents
III-V group compound semiconductor Hall element and manufacturing method thereof Download PDFInfo
- Publication number
- CN104377301A CN104377301A CN201410676818.5A CN201410676818A CN104377301A CN 104377301 A CN104377301 A CN 104377301A CN 201410676818 A CN201410676818 A CN 201410676818A CN 104377301 A CN104377301 A CN 104377301A
- Authority
- CN
- China
- Prior art keywords
- hall element
- substrate
- iii
- compound semiconductor
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention discloses a III-V group compound semiconductor Hall element and a manufacturing method of the III-V group compound semiconductor Hall element. According to the Hall element manufactured with the method, a III-V group compound semiconductor single-crystal substrate used for epitaxial growth and a Hall element functional layer are stripped, and the Hall element is assembled on a rigid supporting substrate or an insulating cooling base. Because the Hall element is assembled on the insulating cooling base, the cooling capacity of the insulating cooling base can be greatly improved; meanwhile, because a face-down bonding technology is adopted, the chip area occupied by one single Hall element can be effectively reduced, and cost is reduced. After the single-crystal substrate is simply processed, the single-crystal substrate can be repeatedly used for epitaxial growth, and the number of repetition is larger than twenty. Meanwhile, a doped III-V group compound semiconductor single-crystal substrate which is lower in price can be adopted instead of an expensive semi-insulating single-crystal substrate adopted in a traditional technology, and therefore, the production cost of the Hall element can be greatly reduced.
Description
Technical field
The present invention relates to based on epitaxially grown Ⅲ-Ⅴ compound semiconductor Hall element and preparation method thereof, belong to semiconductor advanced manufacturing technology field.
Background technology
21 century is the information computerization epoch, and sensor technology is the important technical basis of information-intensive society.Hall element is a kind of magneto-dependent sensor based on Hall effect, their sound construction, and volume is little, lightweight, life-span is long, easy for installation, and power consumption is little, and frequency is high, vibration resistance, is not afraid of pollution or the corrosion of dust, greasy dirt, steam and smog etc., therefore applies more and more wider in modern society.Hall element is the Primary Component in DC brushless motor, be widely used in mobile phone, automobile ABS, electronic striking and travel speed to measure, also can be used for Hall ammeter, electronic compass, current/voltage sensor, become the Primary Component that national defence, industry, many branchs of industry such as civilian are indispensable, also be the core technology of Development of Military Equipment simultaneously, in national defense industry construction, there is leading role.
Current Hall element mainly adopts ion implantation and epitaxial growth method two kinds of modes to prepare, two kinds of methods all need a thickness to reach the monocrystalline substrate material of hundreds of micron, the Hall element of preparation comprises the functional layer of several microns and the substrate layer of hundreds of micron, monocrystalline substrate material is expensive, in Hall element, do not bear the effect of functional layer, originally can reuse, in current preparation technology, but can only use once, exist and waste greatly.On the other hand, in traditional handicraft, produce monocrystalline substrate material used as Hall element, be necessary for insulation or semi-insulating single crystal backing material, its price wants expensive a lot of compared to there being the monocrystalline substrate material of certain doping.
Summary of the invention
The present invention aims to provide a kind of novel processing step of Ⅲ-Ⅴ compound semiconductor Hall element, wherein, in the preparation process of Hall element, Hall element functional layer can be realized effectively be separated with monocrystalline substrate material, single crystalline substrate after treatment, can be recycled and reused for epitaxial growth, on the other hand, more cheap doped single crystal backing material can be adopted, thus greatly can reduce production cost.
Technical scheme of the present invention is: a kind of novel processing step of Ⅲ-Ⅴ compound semiconductor Hall element, and the method comprises:
A) provide a kind of Ⅲ-Ⅴ compound semiconductor single crystalline substrate, preferably, select gallium arsenide substrate or InP substrate;
B) in Ⅲ-Ⅴ compound semiconductor single crystalline substrate, one deck sacrifice layer is prepared;
C) on sacrifice layer, grow the functional layer material of Hall element;
D) at the flexible and chemically inert material of extension functional layer surface adhesion one deck, this layer material can additional substrate be peeled off, and raises the efficiency and rate of finished products;
E) select selective corrosion solution corrosion sacrifice layer, realize Hall element extension functional layer and Ⅲ-Ⅴ compound semiconductor single crystalline substrate is peeled off; Ⅲ-Ⅴ compound semiconductor single crystalline substrate after stripping, after simple process, reusable;
F) by the extension functional layer flexible material one side after stripping, stick in another rigid substrate, preferably, select silicon substrate, glass substrate, ceramic substrate or rigidity plastics substrate are as rigid substrate;
G) in Hall element functional layer, the follow-up chip technology needed for final Hall element is prepared;
After completing chip technology, according to product size and radiating requirements, further processing can be selected, carry out step h);
H) Hall element of chip technology will be completed, by technologies such as inverse bondings, be assembled on the insulating radiation substrate of metal patternization in advance, then the solution that selectivity is very high is utilized, dissolve the adhesive used in previous process, Hall element is separated with passive flexible material and rigid substrate, the Hall element that thickness is only several microns can be prepared.Meanwhile, by wire-bonding package on insulating radiation substrate, instead of on Hall element metal electrode direct routing, the chip size (wire-bonding package require metal derby there is larger area) of Hall element can be effectively reduced.
The novel processing step of a kind of Ⅲ-Ⅴ compound semiconductor Hall element according to an embodiment of the invention, wherein, described Ⅲ-Ⅴ compound semiconductor single crystalline substrate is GaAs (GaAs), described sacrifice layer is aluminium arsenide (AlAs), and described selective corrosion solution is hydrofluoric acid (HF) solution.
In sum, the present invention utilizes extension lift-off technology, on amorphous substrate, achieves the preparation of Hall element.Technology provided by the present invention, very has cost advantage.For Ⅲ-Ⅴ compound semiconductor single crystalline substrate, the thickness that each process consumes is no more than 10 microns, the substrate of 500 microns, at least can reuse 20 times.Simultaneously, Hall element prepared by traditional handicraft, require that Ⅲ-Ⅴ compound semiconductor single crystalline substrate is semi-insulated, its price wants expensive many relative to doped single crystal substrate, and adopt our substrate desquamation technology, for the conductivity not requirement of single crystalline substrate, doped single crystal substrate can be adopted, reduce costs further.
Accompanying drawing explanation
Below, embodiment of the present invention are described in detail by reference to the accompanying drawings.In accompanying drawing: 001 is Ⅲ-Ⅴ compound semiconductor single crystalline substrate; 002 is sacrifice layer; 003 is Hall element functional layer; 004 is flexible material; 005 is rigid support substrate; 006 is Ohm contact electrode; 007 is patterned metal; 008 is insulating radiation base.
Fig. 1 Ⅲ-Ⅴ compound semiconductor single crystalline substrate prepares Hall element, comprises Ⅲ-Ⅴ compound semiconductor single crystalline substrate 001, sacrifice layer 002, Hall element functional layer 003;
Fig. 2 adheres to flexible material 004 in extension functional layer 003, comprises Ⅲ-Ⅴ compound semiconductor single crystalline substrate 001, sacrifice layer 002, Hall element functional layer 003, flexible material 004;
After Fig. 3 illustrates that sacrifice layer 002 is corroded, Ⅲ-Ⅴ compound semiconductor single crystalline substrate 001 is separated with Hall element functional layer 003, flexible material 004;
Fig. 4 illustrates that the Hall element functional layer 003 after peeling off, flexible material 004 adhere to each other with rigid support substrate 005;
Fig. 5 adopts semiconductor planar technique, prepares Hall element Ohm contact electrode 006, and mesa etch, the techniques such as passivation;
Fig. 6 adopts inverse bonding technique, and the Ohm contact electrode 006 of Hall element and metallized insulating radiation base 008 are in advance fitted together, the metallization pattern of insulating radiation base is 007;
Flexible material 004, other parts of rigid support substrate 005 and Hall element, on the basis of Fig. 6, are separated by Fig. 7.
Embodiment
embodiment 1:
First an arsenide gallium monocrystal substrate is got, by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), at Grown one deck aluminium arsenide (AlAs) sacrifice layer, and Hall element functional layer.After having grown, get epitaxial wafer, surperficial spin coating layer of adhesive A, this adhesive and Subsequent semiconductor planar technique compatibility, can not change in technical process, then get a flexible material B and adhere on it, this flexible material also with semiconductor planar process compatible, can not change.Epitaxial wafer after process is soaked in the solution containing hydrofluoric acid, hydrofluoric acid to the selecting response ratio of aluminium arsenide (AlAs) and GaAs (GaAs) more than 10000.Utilize hydrofluoric acid to the highly corrosive of sacrifice layer aluminium arsenide (AlAs), sacrifice layer is all eroded, make Hall element functional layer and arsenide gallium monocrystal substrate desquamation.
Get a size and the duplicate silicon chip of arsenide gallium monocrystal substrate in addition again, at silicon chip surface spin coating layer of adhesive A, flexible material B and the Hall element functional layer after peeling off to be adhered to and on silicon chip, flexible material B side and silicon chip bonding.According to the technique of typical Hall element, adopt conventional lithographic methods, spin coating photoresist, exposure, development, obtains Hall element electrode pattern.Then utilize electron beam evaporation (E-beam) gold evaporation-germanium (Au-Ge) alloy, after removing photoresist and dissolving photoresist in liquid, the metal be attached on photoresist comes off, and remaining metal is then the metal ohmic contact of Hall element.Short annealing in nitrogen atmosphere, makes metal and semi-conducting material form good ohmic contact.Then adopt the method for photoetching alignment, continue at epi-layer surface spin coating photoresist, exposure, development, obtains the figure of Hall element mesa etch.Adopt chemical wet etching or dry etching, get rid of the semi-conducting material not having photoresist protection zone, obtain the pattern of Hall element bunge bedstraw herb shape.Remove the photoresist of insulation blocking, then utilize plasma enhanced chemical vapor deposition method (PECVD), in Hall element plated surface last layer silicon nitride (SiNx) passivation material, to protect Hall element.Again adopt the method for photoetching alignment, preparation erodes the figure of the passivation material that Hall element metal ohmic contact covers, and then utilizes dry etching, removes the silicon nitride (SiNx) on metal ohmic contact, finally utilizes the liquid that removes photoresist, and removes photoresist.
embodiment 2:
First an arsenide gallium monocrystal substrate is got, by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), at Grown one deck aluminium arsenide (AlAs) sacrifice layer, and Hall element functional layer.After having grown, get epitaxial wafer, surperficial spin coating layer of adhesive A, this adhesive and Subsequent semiconductor planar technique compatibility, can not change in technical process, then get a flexible material B and adhere on it, this flexible material also with semiconductor planar process compatible, can not change.Epitaxial wafer after process is soaked in the solution containing hydrofluoric acid, hydrofluoric acid to the selecting response ratio of aluminium arsenide (AlAs) and GaAs (GaAs) more than 10000.Utilize hydrofluoric acid to the highly corrosive of sacrifice layer aluminium arsenide (AlAs), sacrifice layer is all eroded, make Hall element functional layer and arsenide gallium monocrystal substrate desquamation.
Get a size and the duplicate silicon chip of arsenide gallium monocrystal substrate in addition again, at silicon chip surface spin coating layer of adhesive A, flexible material B and the Hall element functional layer after peeling off to be adhered to and on silicon chip, flexible material B side and silicon chip bonding.According to the technique of typical Hall element, adopt conventional lithographic methods, spin coating photoresist, exposure, development, obtains Hall element electrode pattern.Then utilize electron beam evaporation (E-beam) gold evaporation-germanium (Au-Ge) alloy, after removing photoresist and dissolving photoresist in liquid, the metal be attached on photoresist comes off, and remaining metal is then the metal ohmic contact of Hall element.Short annealing in nitrogen atmosphere, makes metal and semi-conducting material form good ohmic contact.Then adopt the method for photoetching alignment, continue at epi-layer surface spin coating photoresist, exposure, development, obtains the figure of Hall element mesa etch.Adopt chemical wet etching or dry etching, get rid of the semi-conducting material not having photoresist protection zone, obtain the pattern of Hall element bunge bedstraw herb shape.Remove the photoresist of insulation blocking, then utilize plasma enhanced chemical vapor deposition method (PECVD), in Hall element plated surface last layer silicon nitride (SiNx) passivation material, to protect Hall element.Again adopt the method for photoetching alignment, preparation erodes the figure of the passivation material that Hall element metal ohmic contact covers, and then utilizes dry etching, removes the silicon nitride (SiNx) on metal ohmic contact, finally utilizes the liquid that removes photoresist, and removes photoresist.
Get an insulating radiation substrate, substrate is arranged according to the metallic pattern of Hall element, the metallic pattern that preparation is symmetrical, then adopt inverse bonding technique, by the metal of Hall element together with the metal solder of insulating radiation base.Finally, use the solution can removing adhesive A, adhesive A is dissolved, flexible material B and silicon chip are separated with Hall element.So far, whole technical process all completes.
Claims (8)
1. a Ⅲ-Ⅴ compound semiconductor Hall element, is characterized in that: the Hall element chip not having single crystalline substrate, is assembled on rigid support substrate or insulating radiation substrate.
2. the preparation method of a kind of Ⅲ-Ⅴ compound semiconductor Hall element as claimed in claim 1, the method comprises:
A) a kind of Ⅲ-Ⅴ compound semiconductor single crystalline substrate is selected;
B) in Ⅲ-Ⅴ compound semiconductor single crystalline substrate, one deck sacrifice layer is prepared;
C) functional layer material of continued growth Hall element on sacrifice layer;
D) at the flexible and chemically inert material of extension functional layer surface adhesion one deck;
E) select selective corrosion solution corrosion sacrifice layer, realize Hall element extension functional layer and Ⅲ-Ⅴ compound semiconductor single crystalline substrate is peeled off; Ⅲ-Ⅴ compound semiconductor single crystalline substrate after stripping, after simple process, reusable;
F) by the extension functional layer flexible material one side after stripping, stick on another rigid support substrate;
G), in the Hall element functional layer after stripping, the follow-up chip technology needed for final Hall element is prepared.
3. the novel processing step of a kind of Ⅲ-Ⅴ compound semiconductor Hall element as claimed in claim 2, it is characterized in that: after step g), according to product needed, the Hall element of chip technology will be completed, by technologies such as inverse bondings, be assembled on the insulating radiation substrate of metal patternization in advance, then Hall element be separated with passive flexible material and rigid substrate, complete ultra-thin Hall element and make.
4. the novel processing step of a kind of Ⅲ-Ⅴ compound semiconductor Hall element as claimed in claim 2, is characterized in that: described Ⅲ-Ⅴ compound semiconductor single crystalline substrate is GaAs (GaAs) substrate or indium phosphide (InP) substrate.
5. the novel processing step of a kind of Ⅲ-Ⅴ compound semiconductor Hall element as claimed in claim 2, is characterized in that: based on gallium arsenide substrate, and described sacrifice layer is aluminium arsenide (AlAs) layer or gallium aluminium arsenic (AlGaAs) layer; Based on InP substrate, described sacrifice layer is indium gallium arsenic (InGaAs) layer.
6. the novel processing step of a kind of Ⅲ-Ⅴ compound semiconductor Hall element as claimed in claim 2, is characterized in that: described rigid support substrate is silicon substrate, glass substrate, ceramic substrate or rigidity plastics substrate.
7. the novel processing step of a kind of Ⅲ-Ⅴ compound semiconductor Hall element as claimed in claim 2, is characterized in that: based on gallium arsenide substrate, and described selective corrosion solution is hydrofluoric acid (HF) solution; Based on InP substrate, described selective corrosion solution is citric acid and hydrogen peroxide mixed liquor.
8. the novel processing step of a kind of Ⅲ-Ⅴ compound semiconductor Hall element as claimed in claim 3, is characterized in that: described insulating radiation substrate is heat dissipation ceramic sheet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410676818.5A CN104377301A (en) | 2014-11-24 | 2014-11-24 | III-V group compound semiconductor Hall element and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410676818.5A CN104377301A (en) | 2014-11-24 | 2014-11-24 | III-V group compound semiconductor Hall element and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104377301A true CN104377301A (en) | 2015-02-25 |
Family
ID=52556076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410676818.5A Pending CN104377301A (en) | 2014-11-24 | 2014-11-24 | III-V group compound semiconductor Hall element and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104377301A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105261698A (en) * | 2015-09-30 | 2016-01-20 | 苏州矩阵光电有限公司 | Hall element and manufacturing method |
| CN110676205A (en) * | 2019-09-17 | 2020-01-10 | 中国电子科技集团公司第十一研究所 | Method for multiple use of substrate of chip and infrared detector |
| CN113745268A (en) * | 2021-08-06 | 2021-12-03 | 苏州矩阵光电有限公司 | Monolithic integrated Hall circuit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2081505A (en) * | 1980-08-05 | 1982-02-17 | Itt Ind Ltd | Hall effect device |
| US4883561A (en) * | 1988-03-29 | 1989-11-28 | Bell Communications Research, Inc. | Lift-off and subsequent bonding of epitaxial films |
| US6214733B1 (en) * | 1999-11-17 | 2001-04-10 | Elo Technologies, Inc. | Process for lift off and handling of thin film materials |
| CN1757106A (en) * | 2003-01-07 | 2006-04-05 | S.O.I.Tec绝缘体上硅技术公司 | Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer |
| CN102299210A (en) * | 2011-09-14 | 2011-12-28 | 中国科学院苏州纳米技术与纳米仿生研究所 | Method for manufacturing inverted film solar cell |
| CN102376788A (en) * | 2010-08-11 | 2012-03-14 | 朱忻 | Multilayered film used for solar energy cell, preparation method thereof and purpose thereof |
| CN103797568A (en) * | 2011-09-19 | 2014-05-14 | 国际商业机器公司 | High throughput epitaxial lift off for flexible electronics |
-
2014
- 2014-11-24 CN CN201410676818.5A patent/CN104377301A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2081505A (en) * | 1980-08-05 | 1982-02-17 | Itt Ind Ltd | Hall effect device |
| US4883561A (en) * | 1988-03-29 | 1989-11-28 | Bell Communications Research, Inc. | Lift-off and subsequent bonding of epitaxial films |
| US6214733B1 (en) * | 1999-11-17 | 2001-04-10 | Elo Technologies, Inc. | Process for lift off and handling of thin film materials |
| CN1757106A (en) * | 2003-01-07 | 2006-04-05 | S.O.I.Tec绝缘体上硅技术公司 | Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer |
| CN102376788A (en) * | 2010-08-11 | 2012-03-14 | 朱忻 | Multilayered film used for solar energy cell, preparation method thereof and purpose thereof |
| CN102299210A (en) * | 2011-09-14 | 2011-12-28 | 中国科学院苏州纳米技术与纳米仿生研究所 | Method for manufacturing inverted film solar cell |
| CN103797568A (en) * | 2011-09-19 | 2014-05-14 | 国际商业机器公司 | High throughput epitaxial lift off for flexible electronics |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105261698A (en) * | 2015-09-30 | 2016-01-20 | 苏州矩阵光电有限公司 | Hall element and manufacturing method |
| CN110676205A (en) * | 2019-09-17 | 2020-01-10 | 中国电子科技集团公司第十一研究所 | Method for multiple use of substrate of chip and infrared detector |
| CN110676205B (en) * | 2019-09-17 | 2023-01-06 | 中国电子科技集团公司第十一研究所 | Method for multiple use of substrate of chip and infrared detector |
| CN113745268A (en) * | 2021-08-06 | 2021-12-03 | 苏州矩阵光电有限公司 | Monolithic integrated Hall circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101785115B (en) | Thin film III-V compound solar cell | |
| JP2020107890A (en) | Selective, electrochemical etching of semiconductor | |
| US10014216B2 (en) | Method for manufacturing semiconductor device using high speed epitaxial lift-off and template for III-V direct growth and semiconductor device manufactured using the same | |
| US10340187B2 (en) | Strain relief epitaxial lift-off via pre-patterned mesas | |
| KR20120083307A (en) | Method for producing compound semiconductor crystal, method for manufacturing electronic device, and semiconductor substrate | |
| CN104362196A (en) | InGaAs infrared detector and preparing method thereof | |
| WO2010020066A1 (en) | Method for fabricating semiconductor light-emitting device with double-sided passivation | |
| CN104377301A (en) | III-V group compound semiconductor Hall element and manufacturing method thereof | |
| TWI445189B (en) | Lift-off structur for substrate of a photoelectric device and method thereof | |
| CN102956552A (en) | Preparation method for semiconductor device | |
| CN104409593A (en) | Method of preparing nitride epitaxial layer, substrate and device wafer | |
| US8330036B1 (en) | Method of fabrication and structure for multi-junction solar cell formed upon separable substrate | |
| CN109686837A (en) | A kind of preparation method of high sensitivity Hall element | |
| CN110600990B (en) | GaN-based laser based on flexible substrate and HEMT device transfer preparation method | |
| KR20160047759A (en) | Method of fabrication and structure for multi-junction solar cell formed upon separable substrate | |
| CN105591026A (en) | Method for preparing high-sensitivity Hall element | |
| CN205004354U (en) | III - V compound semiconductor hall element of clan | |
| JP2008258563A (en) | Semiconductor device manufacturing method, semiconductor device, and electronic device | |
| CN105576119A (en) | High-sensitivity Hall element and preparation method thereof | |
| CN105826814A (en) | Method of preparing indium phosphide-based narrow-ridge waveguide semiconductor laser | |
| CN104393168A (en) | Hall element and preparation method thereof | |
| CN108054098A (en) | A kind of manufacture craft of the GaN-HEMT chips with field plate | |
| KR100638351B1 (en) | semiconductor substrate and the manufacturing method of the same | |
| JP2005026242A (en) | Semiconductor element and method of manufacturing the same | |
| TWI585990B (en) | Lift-off structure for substrate of a photoelectric device and method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150225 |
|
| WD01 | Invention patent application deemed withdrawn after publication |