CN104347506A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN104347506A
CN104347506A CN201310312337.1A CN201310312337A CN104347506A CN 104347506 A CN104347506 A CN 104347506A CN 201310312337 A CN201310312337 A CN 201310312337A CN 104347506 A CN104347506 A CN 104347506A
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CN
China
Prior art keywords
grid
semiconductor substrate
semiconductor device
ion implantation
groove
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CN201310312337.1A
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Chinese (zh)
Inventor
谢欣云
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN201310312337.1A priority Critical patent/CN104347506A/en
Publication of CN104347506A publication Critical patent/CN104347506A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The invention discloses a method for manufacturing a semiconductor device. The method comprises the following steps: providing a semiconductor substrate; forming grids on the semiconductor substrate; executing a comprehensive ion implantation process so as to form groove pre-etching regions in the semiconductor substrate at the two sides of each grid; forming offset sidewalls at the two sides of each grid; forming grooves in the groove pre-etching regions; and forming epitaxial layers in the grooves. According to the manufacture technology provided by the invention, the top portions of the SiGe/SiC epitaxial layers formed in the silicon semiconductor substrate at the two sides of each grid structure are closer to the grid structures in a vertical direction and a horizontal direction, such that stress on a semiconductor device channel is enhanced, the parasitic expansion resistance of the semiconductor device is reduced, and finally the performance of a PFET semiconductor device and an NFET semiconductor device is improved.

Description

A kind of method making semiconductor device
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of method making semiconductor device.
Background technology
At present, semi-conductor industry is growth of device in the wafer device of silicon substrate mainly, such as, MOSFET device structure includes source region, source electrode, drain and gate, wherein, described active area is arranged in bulk silicon substrate, and described grid is positioned at active region, the active region of described grid both sides.Ion implantation is carried out to form source electrode and drain electrode to the active area of described grid both sides, below grid, there is conducting channel, between described grid and conducting channel, have gate dielectric layer.Dissimilar according to ion implantation, to form cavity type metal oxide semiconductor transistor and electron type mos field effect transistor.
Recently, strain engineering technology is considered to one and Moore's Law is prolonged one of raw key technology, so-called strain engineering technology, namely by introducing local simple tension or compression stress to the conducting channel of MOSFET, promote the conducting channel carriers mobility of MOSFET, thus at gate-dielectric thinner layer thickness or when remaining unchanged, drive current is significantly increased, the final device performance improving MOSFET.For the conducting channel in silicon substrate, the Available Material that can produce the unidirectional strain in local has SiGe and SiC must distinguish the unidirectional strain structure of layout for PMOS and NMOS.Wherein, mobility PMOS introducing compression stress being increased to hole is called local Uniaxial Compression strain, and is called local simple tension strain to the mobility of NMOS introducing tensile type of stress raising electronics.
The strain engineering technology be applied at present mainly contains: the silicon nitride cover layer of deposition stretching or compressive type of stress; At shallow trench isolation from the oxide skin(coating) with increase stretching or compressive type of stress in metallide dielectric medium structure, and SiGe epitaxial loayer fills source, the drain region of etching or rising.
The source/drain region that SiGe epitaxial loayer fills etching is a kind of strain engineering technology be widely used.At the source/drain region selective epitaxial growth SiGe epitaxial loayer of PMOS, there is following advantage: the lattice constant of SiGe is different from Si thus makes the conducting channel in silicon substrate produce strain, for improving the mobility of holoe carrier, SiGe has less energy gap than Si, and the potential barrier like this between semiconductor and silicide reduces.For more advanced technology node, in the source/drain region of PMOSFET and NMOSFET, form SiGe and SiC epitaxial layer increases the stress of raceway groove and the ectoparasitism resistance reducing device.Along with constantly reducing of polysilicon gate size, decrease the adaptability to changes of SiGe and SiC epitaxial layer generation.In order to strengthen the adaptability to changes that SiGe and SiC epitaxial layer produce, need to reduce the distance of epitaxial loayer top to polysilicon gate, but this will skew sidewall (offset spacer) of being formed in grid both sides of impact.
In the prior art, first etch the source/drain region of the grid both sides in PMOSFET region to form groove, again by growing SiGe epitaxial loayer in the groove in the method for selective epitaxial growth source/drain region after etching, compressive type of stress due to epitaxial loayer importing is conducted to the conducting channel of PMOSFET, finally improves the mobility in the hole in PMOSFET.Then; PMOSFET region forms protective layer; the source/drain region of the grid both sides in etching N MOSFET region is to form groove; again by growing SiC epitaxial layer in the groove in the method for selective epitaxial growth source/drain after etching; tensile type of stress due to epitaxial loayer importing is conducted to the conducting channel of NMOSFET, finally improves the mobility of the electronics in NMOSFET.
Along with constantly reducing of semiconductor dimensions, in order to the stress improved in semiconductor device and the resistance reduced between source-drain electrode, SiGe in PMOSFET and NMOSFET and SiC epitaxial layer need vertical direction and horizontal direction closer to polysilicon gate, but, epitaxial loayer will affect the formation of grid skew sidewall near polysilicon gate, in MOSFET element, embed the technology of epitaxial loayer, use the epitaxial loayer embedded to form source region or drain region by Challenge.
Therefore, propose a kind of manufacture method of semiconductor device, on the impact of grid skew sidewall during to avoid growing epitaxial stressor layers in the source/drain region of MOSFET element, simultaneously, reduce the distance of epitaxial loayer top to grid, to improve the mobility of channel carrier, and then effectively improve the performance of transistor.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of method making semiconductor device, comprising the following steps, Semiconductor substrate is provided; Form grid on the semiconductor substrate; Perform comprehensive ion implantation technology, to form groove pre-etched district in the Semiconductor substrate of described grid both sides; Skew sidewall is formed in the both sides of described grid; Groove is formed in described groove pre-etched district; Epitaxial loayer is formed in described groove.
Preferably, the injection ionic agent of described comprehensive ion implantation technology is the dopant of N-type.
Preferably, the implant angle of described comprehensive ion implantation technology is 0 ° to 10 °.
Preferably, the step of grid described in re-oxidation process process is adopted before being also included in the comprehensive ion implantation technology of execution.
Preferably, the step of LDD ion implantation is performed after being also included in the described skew sidewall of formation.
Preferably, the step of PKT ion implantation is performed after being also included in the described skew sidewall of formation.
Preferably, dry etch process is adopted to form described groove.
Preferably, the step of groove described in wet etching treatment is adopted after being also included in the described groove of formation.
Preferably, the material of described epitaxial loayer is SiGe.
Preferably, epitaxial growth technology is adopted to form described epitaxial loayer.
To sum up, the present invention proposes the manufacturing process that a kind of source/drain region in NFET region and PFET region forms SiGe and SiC, form grid skew sidewall after formation polysilicon gate before, adopt comprehensive ion implantation technology process Semiconductor substrate of N-type dopant, to improve the lateral etch rate of silicon semiconductor substrate below polysilicon gate and grid skew sidewall, thus the stress effect strengthened further in FET semiconductor device and the resistance reduced between source-drain electrode.The top that can make the SiGe/SiC epitaxial loayer formed in the silicon semiconductor substrate of grid structure both sides according to manufacturing process of the present invention in the vertical direction with horizontal direction closer to grid structure, to strengthen the stress to semiconductor device channel and the parasitic spreading resistance of reduction semiconductor device, finally improve the performance of PFET semiconductor device and NFET semiconductor device.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
The cutaway view of the device that Figure 1A-1H obtains for the correlation step making semiconductor device according to one embodiment of the present invention;
Fig. 2 is the process chart making semiconductor device according to another execution mode of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it will be apparent to one skilled in the art that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by in following description, detailed step is proposed, the manufacture method that the present invention proposes a kind of semiconductor device to be described, the impact on grid skew sidewall when forming epitaxial stress layer to avoid the both sides of the grid structure in MOSFET element Semiconductor substrate to grow.Detailed being described below of obvious preferred embodiment of the present invention, but remove outside these detailed descriptions, the present invention can also have other execution modes.
In order to solve the problems of the prior art, the present invention proposes a kind of manufacture method of semiconductor device.With reference to Figure 1A to Fig. 1 H, the cutaway view of the correlation step of the embodiment according to one aspect of the invention is shown.
Below in conjunction with accompanying drawing 1A-1H, the specific embodiment of the present invention is described in detail.With reference to Figure 1A to Fig. 1 H, the cutaway view of the correlation step of the embodiment according to one aspect of the invention is shown.
As shown in Figure 1A, provide Semiconductor substrate 100, in the substrate 100 of described semiconductor, be formed with trap and active area;
Semiconductor substrate 100 can comprise any semi-conducting material, and this semi-conducting material can include but not limited to: Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III-V or group Ⅱ-Ⅵ compound semiconductor.
Semiconductor substrate 100 comprises various isolation structure, such as shallow trench isolation.Semiconductor substrate 100 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.In addition, Semiconductor substrate can be defined active area.
As preferably, described Semiconductor substrate 100 is the thickness of Si material layer is 10-100nm, is preferably 30-50nm.
Trap is formed in described Semiconductor substrate 100, when described substrate selects N-type substrate, particularly, the N-type substrate that those skilled in the art select this area conventional, then in described N-type substrate, form P trap, in an embodiment of the present invention, first in described N-type substrate, form P trap window, in described P trap window, carry out ion implantation, then perform annealing steps and advance to form P trap.When described substrate selects P type substrate, particularly, the P type substrate that those skilled in the art select this area conventional, then in described P type substrate, N trap is formed, in an embodiment of the present invention, first in described P type substrate, form N trap window, in described N trap window, carry out ion implantation, then perform annealing steps and advance to form N trap.
Described Semiconductor substrate 100 is divided into NFET region and PFET region, and this NFET region has the first grid 101N be formed on the channel region of Uniform Doped, and PFET region has the second grid 101P be formed on the channel region of Uniform Doped.First grid 101N comprises gate dielectric and is positioned at the polysilicon gate 102A on gate dielectric.Second grid 101P comprises gate dielectric and is positioned at the polysilicon gate 102B on gate dielectric.
In of the present invention one particularly execution mode, described first grid 101N and second grid 101P is polysilicon gate, the formation method of described polysilicon gate construction is for form gate dielectric first on a semiconductor substrate 100, as preferably, the material of described gate dielectric is silicon dioxide, and the mode of thermal oxidation can be adopted to be formed.
Be preferably formed polysilicon gate in the present invention, the formation method of polysilicon layer can select low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions forming described polysilicon layer comprise: reacting gas is silane (SiH4), and the range of flow of described silane can be 100 ~ 200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700 ~ 750 degrees Celsius; Reaction chamber internal pressure can be 250 ~ 350 millis millimetres of mercury (mTorr), as 300mTorr; Also can comprise buffer gas in described reacting gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen can be 5 ~ 20 liters/min (slm), as 8slm, 10slm or 15slm.
Then patterning is carried out, to form polysilicon gate on a semiconductor substrate, described patterning method is the photoresist layer first forming patterning, with described photoresist layer for polysilicon layer described in mask etch and gate dielectric, described photoresist layer is removed in last ashing, but the patterning method of described polysilicon gate is not limited to above-mentioned example.
In order to repair the damage of polysilicon gate edges, after the gate formation, employing reoxidizes method (re-oxidation) and forms oxide layer 103 in the periphery of Semiconductor substrate 100 and grid 102A, 102B, and the material of described oxide layer is the oxide of silicon.
As shown in Figure 1B, after formation polysilicon gate, carry out the comprehensive ion implantation of N-type dopant (Blank Implant) technique, form groove pre-etched district respectively with the both sides of grid 102A, the 102B in PFET region and NFET region in described Semiconductor substrate.Concrete, with polysilicon gate 102A and polysilicon gate 102B for mask, use the dopant of N-type to carry out comprehensive ion implantation technology (Blank Implant) to Semiconductor substrate, in the Semiconductor substrate of described grid 102A and 102B both sides, form groove pre-etched district 104A, 104B.The groove pre-etched district formed improves the lateral etch rate of silicon semiconductor substrate below polysilicon gate and grid skew sidewall, and then, in silicon semiconductor substrate the top of the SiGe/SiC epitaxial loayer that the both sides of grid structure are formed in the vertical direction with horizontal direction closer to grid structure, to strengthen the stress of semiconductor device channel and the parasitic spreading resistance (parasitic extension Rs) reducing semiconductor device.At a specific embodiment of the present invention, the technique of comprehensive ion implantation is: injection ion beam energy is 10KV ~ 50KV, and ion dose is 1e 14~ 1e 20atom/cm 2, the range of tilt angles of injection is 0 ° ~ 10 °.
As shown in Figure 1 C, in described Semiconductor substrate 100, described polysilicon gate 102A both sides form skew sidewall (offset spacer) 105A, skew sidewall 105B is formed in the both sides of polysilicon gate 102B, the material of skew sidewall is such as silicon nitride, the insulating material such as silica or silicon oxynitride.Along with diminishing further of device size, the channel length of device is more and more less, it is also more and more less that the particle of source-drain electrode injects the degree of depth, and the effect of skew sidewall is the channel length of the transistor improving formation, the hot carrier's effect reducing short-channel effect and cause due to short-channel effect.Form the technique such as chemical vapour deposition (CVD) of skew sidewall in grid 102A, 102B both sides, in the present embodiment, the thickness of described skew sidewall may diminish to 80 dusts, by depositing and etching formation.
Described skew side wall construction can comprise at least one deck oxide skin(coating) and/or at least one deck nitride layer, its for follow-up carry out etching or ion implantation time protection grid 102A, 102B skew sidewall injury-free.
As shown in figure ip, perform LDD ion implantation respectively in the both sides of described grid structure 102A, 102B and skew sidewall 105A, 105B, to form lightly doped region 106A, 106B, the method for described formation LDD can be ion implantation technology or diffusion technology.The ionic type that described LDD injects is according to the electrical decision of the semiconductor device that will be formed, and the device namely formed is NMOSFET device, then the foreign ion mixed in LDD injection technology is one in phosphorus, arsenic, antimony, bismuth or combination; The device formed in an embodiment of the present invention is PMOSFET device, and the foreign ion of injection is boron.According to the concentration of required foreign ion, ion implantation technology can a step or multistep complete.
After completing described ion implantation, can be subjected to displacement with the atomic collision in semiconductor lattice, lattice atoms to eliminate high-octane incident ion, cause a large amount of rooms, described device is annealed at a certain temperature, to recover the structure of crystal and to eliminate defect.The temperature of annealing is 200-800 DEG C.
In a specific embodiment of the present invention, the both sides of described grid 102A, 102B and skew sidewall 105A, 105B perform pocket injection technology (PKT respectively on a semiconductor substrate 100, Pocket implantation), form pocket region 106A, 106B, for preventing short-channel effect.The element type that pocket injects can be, P type element boron fluoride or boron, N-type element phosphor or arsenic.The ionic type that described pocket injects is according to the electrical decision of the semiconductor device that will be formed.
As referring to figure 1e, grid 102A, skew sidewall 105A, groove pre-etched district 104A and lightly doped region 106A(or pocket region 106A in NFET region) upper formation mask layer 107, mask layer 107 covers the part that will form NFET device, and expose the part that will form PFET device, then, the groove pre-etched district of grid 102B both sides in PFET region and light doping section (pocket region) is etched to form sunk structure 108.
Mask layer 107 for the protection of the device architecture in NFET region to avoid the damage to NFET region devices structure in etching process.The material of mask layer can be silicon dioxide or silicon nitride, and described mask layer can pass through the formation such as chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method.As an example, described silicon nitride mask layer can be by ammonia and dichlorosilane at the temperature of about 750 DEG C, adopts low-pressure chemical vapor deposition to be formed.
The groove pre-etched district 104B of grid 102B both sides and light doping section 106B(or pocket region in etching PFET region) to form sunk structure 108, can adopt dry etch process, dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Such as using plasma etching, etching gas can adopt the gas based on oxygen (O2-based).Concrete, adopt lower radio-frequency (RF) energy also can produce low pressure and highdensity plasma gas to realize dry etching.As an example, the range of flow of the etching gas of using plasma etching can be 50 cc/min (sccm) ~ 150 cc/min (sccm), and reative cell internal pressure can be 5 millitorrs (mTorr) ~ 20 millitorr (mTorr).Wherein, the etching gas of dry etching can be bromize hydrogen gas, carbon tetrafluoride gas or gas of nitrogen trifluoride, can also pass into some and add gas, as nitrogen, helium or oxygen etc.Form sunk structure 108 by control etch rate and etch period, described sunk structure becomes " U " connected in star.The degree of depth of " U " connected in star 108 can be determined according to the degree of depth of desired source/drain region.Substrate surface can be arranged essentially parallel to bottom " U " connected in star." U " connected in star sidewall can be substantially perpendicular to substrate surface.
As shown in fig. 1f, from the sidewall of " U " connected in star 108, to Semiconductor substrate, there is crystal orientation optionally wet etching.Have crystal orientation optionally wet etching be well known in the art, such as, etching speed on <111> crystal orientation can be less than the etching speed on other crystal orientation.
In a specific embodiment of the present invention, adopt wet etching " U " connected in star 108, to form " ∑ " connected in star, this wet etching will stop on <111> crystal face and <11-1> crystal face, thus formed " ∑ " connected in star, can adopt Tetramethylammonium hydroxide (TMAH), dilution hydrofluoric acid (DHF) carry out wet etching.
Then in " ∑ " connected in star, SiGe layer 109 is formed, the one in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG) that chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method etc. can be selected to be formed.
The method of selective epitaxial growth is adopted to form described SiGe epitaxial loayer in a groove, in a specific embodiment of the present invention, epitaxial growth equipment is generally reaction chamber, after wafer is put into reaction chamber, in reaction chamber, pass into reacting gas and heat, reacting gas grows required crystal structure in the groove of Semiconductor substrate.Particularly, select silane and germane as reacting gas, and select helium or nitrogen as carrier gas, wherein the flow-rate ratio of reacting gas and carrier gas is 0.01-0.1, and the temperature of deposition is 300-1000 DEG C, is preferably 650-750 DEG C, gas pressure is 1-50torr, is preferably 20-40Torr.Wherein, so-called selective epitaxial growth process refers to that SiGe epitaxial loayer only deposits the surface of exposing Semiconductor substrate in a groove.
Then, as shown in fig. 1h, grid 102B, skew sidewall 105B, groove pre-etched district 104B and lightly doped region 106B(and/or pocket region 106B in PFET region) upper formation mask layer 110, mask layer 110 covers the part that will form PFET device, and expose the part that will form NFET device, then, remove the mask layer 107 in NFET region, then, the groove pre-etched district 104A of grid 102A both sides and 106A(pocket region, light doping section in etching N FET region territory) to form sunk structure 111.
Mask layer 110 for the protection of the device architecture in PFET region to avoid the damage to NFET region devices structure in etching process.The material of mask layer can be silicon dioxide or silicon nitride, and described mask layer can pass through the formation such as chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method.As an example, described silicon nitride mask layer can be by ammonia and dichlorosilane at the temperature of about 750 DEG C, adopts low-pressure chemical vapor deposition to be formed.
The mask layer 107 removed in NFET region can adopt dry ecthing method that wet etch method also can be adopted to remove mask layer.Dry ecthing method can adopt the anisotropic etch process based on carbon fluoride gas.Wet etch method can adopt hydrofluoric acid solution, such as buffer oxide etch agent or hydrofluoric acid cushioning liquid.
The groove pre-etched district 104A of grid 102A both sides and light doping section 106A(and/or pocket region in etching N FET region territory) to form sunk structure 111, can adopt dry etch process, dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Such as using plasma etching, etching gas can adopt the gas based on oxygen (O2-based).Concrete, adopt lower radio-frequency (RF) energy also can produce low pressure and highdensity plasma gas to realize dry etching.As an example, the range of flow of the etching gas of using plasma etching can be 50 cc/min (sccm) ~ 150 cc/min (sccm), and reative cell internal pressure can be 5 millitorrs (mTorr) ~ 20 millitorr (mTorr).Wherein, the etching gas of dry etching can be bromize hydrogen gas, carbon tetrafluoride gas or gas of nitrogen trifluoride, can also pass into some and add gas, as nitrogen, helium or oxygen etc.Form sunk structure 111 by control etch rate and etch period, described sunk structure becomes " U " connected in star.The degree of depth of " U " connected in star 111 can be determined according to the degree of depth of desired source/drain region.Substrate surface can be arranged essentially parallel to bottom " U " connected in star." U " connected in star sidewall can be substantially perpendicular to substrate surface.
Then, adopt the method for selective epitaxial growth in groove 111, form described SiC epitaxial layer 112, in a specific embodiment of the present invention, epitaxial growth equipment is generally reaction chamber, after wafer is put into reaction chamber, in reaction chamber, pass into reacting gas and heat, reacting gas grows required crystal structure in the groove of Semiconductor substrate.Particularly, select silane and methane as reacting gas, and select helium or nitrogen as carrier gas, wherein the flow-rate ratio of reacting gas and carrier gas is 0.01-0.1, and the temperature of deposition is 300-1000 DEG C, is preferably 650-750 DEG C, gas pressure is 1-50torr, is preferably 20-40Torr.Wherein, so-called selective epitaxial growth process refers to that SiC epitaxial layer only deposits the surface of exposing Semiconductor substrate in a groove.
With reference to Fig. 2, show the process chart making semiconductor device according to one embodiment of the present invention, for schematically illustrating the flow process of whole manufacturing process.
In step 201, provide Semiconductor substrate, Semiconductor substrate has the first area separated by shallow trench and second area that are formed thereon.First area is N-shaped field-effect transistor region, second area is p-type field-effect transistor region, be formed with source region and trap in the semiconductor substrate, in NFET region and PFET region, be formed with grid, formed by oxide layer in the periphery of Semiconductor substrate and grid;
In step 202., after formation grid and oxide layer, the comprehensive ion implantation technology of N-type dopant is carried out, to form groove pre-etched district respectively in the described Semiconductor substrate in PFET region and NFET area gate both sides;
In step 203, the both sides of the grid in NFET region and PFET region form skew sidewall on the semiconductor substrate;
In step 204, in NFET region and PFET region, LDD ion implantation or pocket injection technology is performed respectively;
In step 205, the both sides of the grid structure in PFET region form the first groove in the semiconductor substrate;
In step 206, adopt the first groove described in wet etching treatment to form first " ∑ " connected in star, in first " ∑ " connected in star, adopt epitaxial growth technology to form SiGe layer;
In step 207, the both sides of the grid structure in NFET region form the second groove in the semiconductor substrate;
In a step 208, in described second groove, adopt epitaxial growth technology to form SiC layer.
To sum up, the present invention proposes the manufacturing process that a kind of source/drain region in NFET region and PFET region forms SiGe and SiC, form grid skew sidewall after formation polysilicon gate before, adopt N-type doping injection to improve the lateral etch rate of silicon semiconductor substrate below polysilicon gate and grid skew sidewall, thus the stress effect strengthened further in FET semiconductor device and the resistance reduced between source-drain electrode.The top that can make the SiGe/SiC epitaxial loayer formed in the silicon semiconductor substrate of grid structure both sides according to manufacturing process of the present invention in the vertical direction with horizontal direction closer to grid structure, to strengthen the stress to semiconductor device channel and the parasitic spreading resistance of reduction semiconductor device, finally improve the performance of PFET semiconductor device and NFET semiconductor device.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.

Claims (10)

1. make a method for semiconductor device, comprising:
Semiconductor substrate is provided;
Form grid on the semiconductor substrate;
Perform comprehensive ion implantation technology, to form groove pre-etched district in the Semiconductor substrate of described grid both sides;
Skew sidewall is formed in the both sides of described grid;
Groove is formed in described groove pre-etched district;
Epitaxial loayer is formed in described groove.
2. the method for claim 1, is characterized in that, the injection ionic agent of described comprehensive ion implantation technology is the dopant of N-type.
3. the method for claim 1, is characterized in that, the implant angle of described comprehensive ion implantation technology is 0 ° to 10 °.
4. the method for claim 1, is characterized in that, is also included in the step adopting grid described in re-oxidation process process before performing comprehensive ion implantation technology.
5. the method for claim 1, is characterized in that, is also included in the step performing LDD ion implantation after forming described skew sidewall.
6. the method for claim 1, is characterized in that, is also included in the step performing PKT ion implantation after forming described skew sidewall.
7. the method for claim 1, is characterized in that, adopts dry etch process to form described groove.
8. the method for claim 1, is characterized in that, is also included in the step adopting groove described in wet etching treatment after forming described groove.
9. the method for claim 1, is characterized in that, the material of described epitaxial loayer is SiGe.
10. the method for claim 1, is characterized in that, adopts epitaxial growth technology to form described epitaxial loayer.
CN201310312337.1A 2013-07-23 2013-07-23 Method for manufacturing semiconductor device Pending CN104347506A (en)

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Application publication date: 20150211