CN104050104B

CN104050104B - Data alignment method

Info

Publication number: CN104050104B
Application number: CN201410274518.4A
Authority: CN
Inventors: 何旭; 洪浩; 王磊
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2014-06-19
Filing date: 2014-06-19
Publication date: 2017-04-12
Anticipated expiration: 2034-06-19
Also published as: CN104050104A

Abstract

The invention belongs to the field of digital signal processing and particularly relates to a data alignment method which is used for processing multiple paths of parallel signals and has low hardware complexity. The data alignment method includes the following steps of determining the number and type parameters of data selectors, caching input data, extracting data slots for reorganization, determining magnitude of each reorganized data block and carrying out interblock arrangement on the data blocks. By means of the data alignment method, hardware resource consumption for alignment of the multiple paths of parallel data can be effectively reduced, and at the same time, complexity of locating and wiring is lowered.

Description

A kind of data alignment method

Technical field

The invention belongs to digital processing field, more particularly to it is a kind of for multi-path parallel signal process, low hardware The data alignment method of complexity.

Background technology

The situation of data dislocation can be faced in digital signal processing, for example：In the base band line number of high-speed radiocommunication It is in word signal processing, unpredictable due to receiving end data initial time position, cause to receive initial data in multiple and line number Do not know according to the position in passage；As sending and receiving end crystal oscillator frequency is inconsistent, sample-timing error is caused to be accumulated, receiving data Timing position will gradually slide in multidiameter delay data channel.And the signal processing module of rear end, such as channel equalization, decoding Need to obtain the multidiameter delay data of timing position fixation etc. module, so needing to carry out at alignment of data multidiameter delay data Reason.

In the process of m roads parallel digital signal, serial data consists of one group with continuous m symbol, continuous in time Data set constitutes m channel parallel data streams, as shown in figure 1, Fig. 1 (a) is two adjacent groups m channel parallel data under normal circumstances；Fig. 1 B there is misalignment for data in (), compare normal condition, and data have been misplaced x character position successively, now need to carry out data Alignment, specific to for T2 groups be exactly according to data misplace number x, by alignment of data operation so that data are normal again The D [m+1] of situation, D [m+2] ..., D [2m].

Existing alignment of data scheme is, according to different dislocation values, to select 1 data selector directly from adjacent using m roads 2m The output of m circuit-switched datas is selected in two groups of m channel parallel datas.Obviously, when m values are larger, m roads 2m selects the realization of 1 selector consume Substantial amounts of hardware resource and cause placement-and-routing to complicate, or even be difficult to, have a strong impact on systematic function.

The content of the invention

It is an object of the invention to provide a kind of for multi-path parallel signal process, low hardware complexity alignment of data Method.

The purpose of the present invention is achieved by the steps of：

S1, number n and the n that according to m channel parallel datas and actual hardware platform situation, determine data selector The type parameter n1 of data selector, n2, n3 ..., nn, wherein, n >=2, m=2a, the natural number that a is not zero；

S2, according to S1 the type parameter n1 of n data selector, n2, n3 ..., nn constitutes n DBMSs and selects The data selector of device, i.e., first selects 1 for n1, and second data selector selects 1 for n2, and the 3rd data selector is selected for n3 1 ... ..., nth data selector selects 1 for nn, wherein, n1 × n2 × n3 × ... × nn=m；

S3, the m channel parallel datas to being input into carry out two-level cache；

S4, according to data dislocation value, choose 1 data slot respectively from per grade of caching in two-level cache described in S3, totally 2 Data slot, 2 data fragment assemblies restructuring obtain recombination data block, wherein, data dislocation value is obtained according to actual measurement；

S5, according to the value of m and n1 determines S4 recombination data block piecemeal size；

S6, data dislocation value and piecemeal size described in S5 according to S4 carry out piecemeal and block to recombination data block described in S4 Interior alignment, obtains block data；

S7, according to S4 data dislocation value and n size, by block data described in S6 carry out between block sort, export number According to.

Further, the type parameter of data selector described in S2 is selected according to actual hardware condition, is empirical value.

The invention has the beneficial effects as follows：

The present invention provides a kind of for multi-path parallel signal process, low hardware complexity data alignment method, can have Effect reduces the hardware resource consumption of multidiameter delay alignment of data, while reducing the complexity of placement-and-routing.

Description of the drawings

Fig. 1 is the m channel parallel data schematic diagrams of normal condition and misalignment.

Fig. 2 is alignment of data scenario-frame block diagram of the present invention.

Fig. 3 is (2nd) step operation chart of example in specific embodiment.

Fig. 4 is (3rd) step operation chart of example in specific embodiment.

Fig. 5 is (4th) step operation chart of example in specific embodiment.

Specific embodiment

Below in conjunction with the accompanying drawings and specific embodiment is further detailed to the present invention.

This example assumes there are m channel parallel datas, m=16, and data dislocation value x is 7, and data selector series n is 2, and n1 =n2=4.

7 character positions as shown in figure 3,16 channel parallel datas have misplaced, this example will carry out data pair to T2 groups data Together, will data shift 7 character positions successively so that the T2 groups data after alignment again for normal condition { D [1], D [2], D [3] ..., D [15], D [16], concrete operation step is as follows：

(1) 16 channel parallel data of T2 groups and the T2 groups adjacent 16 channel parallel data of T1 groups is carried out with data register Two-level cache；

(2) select 1 selector that 2 data slots, the first half of the fragment 1 for T2 group data are selected from data cached with 2 The m-x=9 data divided, x=7 data of the fragment 2 for the latter half of T1 group data.Again the two data slots are spliced 16 circuit-switched data of new one group is reassembled as, A groups are denoted as.As shown in figure 3, A=D [8], D [9] ... D [16], D [1], D [2]……D[7]}.As can be seen that only 7 data { D [1], D [2] ... D [7] } last in A need to be moved integrally D [8] Results needed is obtained before：{D[1]、D[2]、D[3]、……、D[15]、D[16]}.

(3) select 1 selector to carry out aliging in piecemeal and block by A groups data with 4, be as a result denoted as B.As shown in figure 4, first by M and n1 can obtain piecemeal sizeDefinition block E={ D [1], D [2], D [3], D [4] }, F={ D [5], D [6], D [7], D [8] }, G={ D [9], D [10], D [11], D [12] }, H={ D [13], D [14], D [15], D [16] }.It is wrong according to data Place value x, defines positive integer y=xmod4, and wherein mod represents modulus computing.In this example, y=7mod4=3.Then with A In nethermost y=3 data and A, uppermost 4-y=1 data are spliced into one piece, obtain block F.Finally, its remainder of A According to blocking G, H and E successively from top to bottom.Then B={ F, G, H, E }.

(4) it is last, as shown in figure 5, C is as a result denoted as according to carrying out sorting between block 4 block numbers of B, then C={ E, F, G, H }= D [1], D [2], D [3] ..., D [15], D [16] be final alignment data.

Claims

1. a kind of data alignment method, it is characterised in that comprise the steps:

S1, according to m channel parallel datas and actual hardware platform situation, determine number n and the n data of data selector The type parameter n1 of selector, n2, n3 ..., nn, wherein, n >=2, m=2a, the natural number that a is not zero；

S2, according to S1 the type parameter n1 of n data selector, n2, n3 ..., nn constitute n DBMS selectores, I.e. first data selector selects 1 for n1, and second data selector selects 1 for n2, and the 3rd data selector is selected for n3 1 ... ..., nth data selector selects 1 for nn, wherein, n1 × n2 × n3 × ... × nn=m；

S4, according to data dislocation value, selected with 2 and in two-level cache described in 1 selector S3, select 2 data slots, fragment 1 be T2 M-x=9 data of the top half of group data, x=7 data of the fragment 2 for the latter half of T1 group data；Again by this Two data fragment assemblies are reassembled as 16 circuit-switched data of new one group, wherein, data dislocation value is obtained according to actual measurement；

S5, according to the value of m and n1 determines S4 recombination data block piecemeal size, i.e.,

S6, that data dislocation value and piecemeal size described in S5 according to S4 is carried out to recombination data block described in S4 is right in piecemeal and block Together, obtain block data；

S7, according to S4 data dislocation value and n size, by block data described in S6 carry out between block sort, output data.

2. a kind of data alignment method according to claim 1, it is characterised in that：The type ginseng of data selector described in S2 Several factually border hardware conditions are selected, and are empirical values.