CN104023202A - Framework of high-definition video processing unit - Google Patents
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Abstract
The invention relates to a framework of a high-definition video processing unit. The framework comprises the high-definition video processing unit, an image acquisition peripheral, a liquid crystal displayer, an ARM microprocessor, an SDRAM memory, and an AXI system bus interface connected with an image acquisition interface of the image acquisition peripheral and a liquid crystal displayer display interface as well as connected with the ARM microprocessor and the SDRAM memory . The high-definition video processing unit comprises a video processing module, a desquaring filtration module, a DMA control module, a system control module, a video adjustment control module and a high-definition display module. Different parts of the same type of chips can be selected to use according to the demands of different users, thereby meeting the demands of the majority of users well and solving the problem of functional requirements of the majority of users through reasonable configuration of a type of chips; and for the cost aspect, the design cost of a plurality of electronic products can be greatly reduced, so that the design is allowed to have better competitive edge, and the framework has wide application values.
Description
Technical field
The present invention relates to the framework of HD video processing unit, belong to the technical field of HD video processing.
Background technology
Along with the construction of the heavy construction such as development and safe city of video and image correlation industry, intelligence easily video image processing technology receives increasing concern.Video image processing technology is derived from computer vision technique, and the gatherer process of video image is the basis of computer vision technique.By the sequence of video images of video camera or the collection of IMAQ transducer is analyzed, to reach operations such as the target localization in special scenes, target identification, target followings, and understand on this basis and describe the behavior of target.
The research of video image processing technology is increasingly mature, and video image processing system is gradually to intellectuality, high Qinghua and networking future development.High clear video image can comprise a large amount of useful image informations, and this has also just established and processed basis to the development of abstract semantics direction for video image processing technology.But HD video need to be processed mass data, this meets the requirement of system with regard to causing the processing speed of software systems to be difficult to, thereby has reduced the real-time of HD video processing.
Along with the demand of market to high definition product, HD video treatment technology has obtained the development of advancing by leaps and bounds.A lot of companies all combine with asic technology with HD video treatment technology, have released one after another the solution of oneself, have designed the outstanding HD video process chip of many moneys.In several years of future, the development trend of HD video process chip comprises: chip power-consumption is lower, and chip integration is higher, the video processnig algorithms of the intellectual analysis of semantic abstraction layer and more high coding efficiency.
Summary of the invention
For the deficiencies in the prior art, the invention provides the framework of HD video processing unit.The framework of HD video processing unit of the present invention can be realized collection, processing and the Presentation Function of HD video.
Technical scheme of the present invention is as follows:
A framework for HD video processing unit, comprises HD video processing unit, IMAQ peripheral hardware, liquid crystal display, ARM microprocessor, SDRAM memory, with the image capture interface of IMAQ peripheral hardware, with liquid crystal display display interface and the AXI system bus interface being connected with SDRAM memory with ARM microprocessor respectively;
Described HD video processing unit comprises video acquisition module, deblocking filtering module, DMA control module, system control module, video adjustment control module and high definition display module;
Described IMAQ peripheral hardware is connected with the video acquisition module of HD video processing unit inside, completes the acquisition tasks of high-definition data;
Described liquid crystal display is connected with the HD video display module of HD video processing unit, completes the demonstration task of HD video;
Described ARM microprocessor is connected with system control module by AXI bus interface, and effect is that the control register of system is read and write, and controls task and the parameter of described framework;
The chip external memory that described SDRAM memory is video data, DMA control module writes SDRAM memory by AXI interface by the video data of finishing dealing with on the one hand, and DMA control module reads the pending video data in SDRAM memory module by AXI interface on the other hand;
The task of described DMA control module be realize between described framework internal module and described framework inner with framework outside SDRAM memory between the direct access of video data; Described DMA control module can be configured at most 16 passages, the transfer of data that each passage is corresponding different.Channel parameters memory cell is storing the needed parameter of transfer of data, the address of the channel parameters value calculated data access of address arithmetic unit fetch channel parameter storage unit.The parameter that channel control unit generates by address algorithm unit and channel parameters memory cell, controls fifo controller, and reading video data is also stored in the interior FIFO of sheet.AXI master controller is connected with AXI system bus interface, realizes the exchanges data between DMA control module and outside SDRM memory;
Described video acquisition module comprises acquisition interface control unit and video type converting unit, and described acquisition interface control unit is by the control of docking port signal, and reading images gathers the video data of peripheral hardware output; The data of described collection are carried out YUV and RGB chrominance space in video type converting unit, video sampling, the processing of video data mapping; The data of finishing dealing with, are stored in SDRAM memory by DMA control module;
Described deblocking filtering module comprises that filtering flow process control unit, filtering storage control unit and filtering algorithm realize unit, the process of the whole filtering of described filtering flow process control unit control, the control signal control filtering algorithm of generation is realized unit and is completed concrete filter task; Filtering storage control unit reading out data from filtering memory is sent to filtering algorithm and realizes unit, and filtering algorithm is realized in the data writing filtering memory that cell processing completes; Described DMA control module writes video data to be filtered and reads the video data of finishing dealing with to deblocking filtering module;
Described system control module comprises interrupt control register and task control register; The interrupting information of described interrupt control register control system, task control register completes enabling and configuring of corresponding task; Register can be controlled by the read-write of ARM microprocessor by AXI interface.
Described video adjustment control module completes convergent-divergent and the rotation of video frame image; Pending video data is put into input FIFO by described DMA control module, and convergent-divergent algorithm unit reads the data of input FIFO and carries out interpolation or sampling processing, and result is write to output FIFO, and DMA control module reads the video data of output FIFO; The implementation procedure of the whole task of described flow process control unit control; The needed processing parameter of algorithm parameter FIFO storage convergent-divergent algorithm unit; Video rotation comprises rotation storage control unit, rotation FIFO and rotation control unit; Rotation memory cell control rotation FIFO, completes the access of video data; Rotation control unit completes the rotation task to rotation storage control unit data streams read;
Described HD video display module comprises simultaneous display unit, asynchronous display unit, display adapter and interface sequence converter unit; The simultaneous display of real-time video is supported in described simultaneous display unit; The asynchronous display that described asynchronous display support is not high to requirement of real-time; Described synchronous or asynchronous display unit receives the display video data of described DMA control module, through synchronous or asynchronous process, video data transmitting is delivered to the sequential that display adapter completes the capable synchronous sequence of video data frame and physical interface and change; Between described interface sequence converter unit and adapter, arbitrate and reply, the interface conversion of transfer of data and sequencing control, delivers to outside liquid crystal display by display video data and shows.
The invention has the beneficial effects as follows:
1, the present invention is the design object based on a large-scale SOC, by design cycles such as design, checking, comprehensive and domains, finally carries out flow volume production.The first, HD video processing unit is realized in devices at full hardware mode, has wherein realized numerous conventional software algorithms.The theoretical research of these algorithms and innovation are realized and have important reference the hardware of other algorithms.The second, native system target is HD video, need to, to googol according to carrying out respective handling, have very high requirement to the access bandwidth of system data.The research of system storage framework is conducive to for other large data chips.The 3rd, system control structure complexity, simple register can not be stored the required parameter of all systems operations, so introduce needed parameter in parameter storage stored algorithm implementation, and access at any time, has improved the operational efficiency of system greatly.The 4th, data buffer storage, as memory cell in sheet, is the synchronous great function of having brought into play of clock between different submodules, has well realized the function of chip design by technology such as streamline, state machine and ping-pong operations.
2, in the present invention, the design focal point of video processing unit has been considered the aspects such as the hardware realization of storage, framework composition, bus, arbitration scheme, algorithm.The pre-treatment of video and processing procedure are the necessary parts of all processing system for video, as video monitoring system must be using the acquisition and display of video as element.ASIC method for designing is integrated into the function that will realize on a little chip, whole system has performance advantage, the low energy consumption advantage that Software for Design is not enough, low complex degree, advantage etc., from the many aspects such as the stability of whole system and design price consider also to have traditional software design unlike advantage.For selecting different parts to use according to the demand of different user with a chip, can well meet most of user's function, thereby a chip has solved the functional requirement of a large number of users by reasonable disposition, from cost, will greatly reduce the design cost of a lot of electronic products, thereby make design obtain larger competitive advantage, there is wide using value.
Brief description of the drawings
Fig. 1 is the system block diagram of HD video processing unit framework.
Embodiment
Below in conjunction with embodiment and Figure of description, the present invention is described in detail, but is not limited to this.
Embodiment,
A framework for HD video processing unit, comprises HD video processing unit, IMAQ peripheral hardware, liquid crystal display, ARM microprocessor, SDRAM memory, with the image capture interface of IMAQ peripheral hardware, with liquid crystal display display interface and the AXI system bus interface being connected with SDRAM memory with ARM microprocessor respectively;
Described HD video processing unit comprises video acquisition module, deblocking filtering module, DMA control module, system control module, video adjustment control module and high definition display module;
Described IMAQ peripheral hardware is connected with the video acquisition module of HD video processing unit inside, completes the acquisition tasks of high-definition data;
Described liquid crystal display is connected with the HD video display module of HD video processing unit, completes the demonstration task of HD video;
Described ARM microprocessor is connected with system control module by AXI bus interface, and effect is that the control register of system is read and write, and controls task and the parameter of described framework;
The chip external memory that described SDRAM memory is video data, DMA control module writes SDRAM memory by AXI interface by the video data of finishing dealing with on the one hand, and DMA control module reads the pending video data in SDRAM memory module by AXI interface on the other hand;
The task of described DMA control module be realize between described framework internal module and described framework inner with framework outside SDRAM memory between the direct access of video data; Described DMA control module can be configured at most 16 passages, the transfer of data that each passage is corresponding different.Channel parameters memory cell is storing the needed parameter of transfer of data, the address of the channel parameters value calculated data access of address arithmetic unit fetch channel parameter storage unit.The parameter that channel control unit generates by address algorithm unit and channel parameters memory cell, controls fifo controller, and reading video data is also stored in the interior FIFO of sheet.AXI master controller is connected with AXI system bus interface, realizes the exchanges data between DMA control module and outside SDRM memory;
Described video acquisition module comprises acquisition interface control unit and video type converting unit, and described acquisition interface control unit is by the control of docking port signal, and reading images gathers the video data of peripheral hardware output; The data of described collection are carried out YUV and RGB chrominance space in video type converting unit, video sampling, the processing of video data mapping; The data of finishing dealing with, are stored in SDRAM memory by DMA control module;
Described deblocking filtering module comprises that filtering flow process control unit, filtering storage control unit and filtering algorithm realize unit, the process of the whole filtering of described filtering flow process control unit control, the control signal control filtering algorithm of generation is realized unit and is completed concrete filter task; Filtering storage control unit reading out data from filtering memory is sent to filtering algorithm and realizes unit, and filtering algorithm is realized in the data writing filtering memory that cell processing completes; Described DMA control module writes video data to be filtered and reads the video data of finishing dealing with to deblocking filtering module;
Described system control module comprises interrupt control register and task control register; The interrupting information of described interrupt control register control system, task control register completes enabling and configuring of corresponding task; Register can be controlled by the read-write of ARM microprocessor by AXI interface.
Described video adjustment control module completes convergent-divergent and the rotation of video frame image; Pending video data is put into input FIFO by described DMA control module, and convergent-divergent algorithm unit reads the data of input FIFO and carries out interpolation or sampling processing, and result is write to output FIFO, and DMA control module reads the video data of output FIFO; The implementation procedure of the whole task of described flow process control unit control; The needed processing parameter of algorithm parameter FIFO storage convergent-divergent algorithm unit; Video rotation comprises rotation storage control unit, rotation FIFO and rotation control unit; Rotation memory cell control rotation FIFO, completes the access of video data; Rotation control unit completes the rotation task to rotation storage control unit data streams read;
Described HD video display module comprises simultaneous display unit, asynchronous display unit, display adapter and interface sequence converter unit; The simultaneous display of real-time video is supported in described simultaneous display unit; The asynchronous display that described asynchronous display support is not high to requirement of real-time; Described synchronous or asynchronous display unit receives the display video data of described DMA control module, through synchronous or asynchronous process, video data transmitting is delivered to the sequential that display adapter completes the capable synchronous sequence of video data frame and physical interface and change; Between described interface sequence converter unit and adapter, arbitrate and reply, the interface conversion of transfer of data and sequencing control, delivers to outside liquid crystal display by display video data and shows.
Claims (1)
1. the framework of a HD video processing unit, it is characterized in that, the framework of this HD video processing unit comprises HD video processing unit, IMAQ peripheral hardware, liquid crystal display, ARM microprocessor, SDRAM memory, with the image capture interface of IMAQ peripheral hardware, with liquid crystal display display interface and the AXI system bus interface being connected with SDRAM memory with ARM microprocessor respectively;
Described HD video processing unit comprises video acquisition module, deblocking filtering module, DMA control module, system control module, video adjustment control module and high definition display module;
Described IMAQ peripheral hardware is connected with the video acquisition module of HD video processing unit inside, completes the acquisition tasks of high-definition data;
Described liquid crystal display is connected with the HD video display module of HD video processing unit, completes the demonstration task of HD video;
Described ARM microprocessor is connected with system control module by AXI bus interface, and effect is that the control register of system is read and write, and controls task and the parameter of described framework;
The chip external memory that described SDRAM memory is video data, DMA control module writes SDRAM memory by AXI interface by the video data of finishing dealing with on the one hand, and DMA control module reads the pending video data in SDRAM memory module by AXI interface on the other hand;
The task of described DMA control module be realize between described framework internal module and described framework inner with framework outside SDRAM memory between the direct access of video data;
Described video acquisition module comprises acquisition interface control unit and video type converting unit, and described acquisition interface control unit is by the control of docking port signal, and reading images gathers the video data of peripheral hardware output; The data of described collection are carried out YUV and RGB chrominance space in video type converting unit, video sampling, the processing of video data mapping; The data of finishing dealing with, are stored in SDRAM memory by DMA control module;
Described deblocking filtering module comprises that filtering flow process control unit, filtering storage control unit and filtering algorithm realize unit, the process of the whole filtering of described filtering flow process control unit control, the control signal control filtering algorithm of generation is realized unit and is completed concrete filter task; Filtering storage control unit reading out data from filtering memory is sent to filtering algorithm and realizes unit, and filtering algorithm is realized in the data writing filtering memory that cell processing completes; Described DMA control module writes video data to be filtered and reads the video data of finishing dealing with to deblocking filtering module;
Described system control module comprises interrupt control register and task control register; The interrupting information of described interrupt control register control system, task control register completes enabling and configuring of corresponding task;
Described video adjustment control module completes convergent-divergent and the rotation of video frame image; Pending video data is put into input FIFO by described DMA control module, and convergent-divergent algorithm unit reads the data of input FIFO and carries out interpolation or sampling processing, and result is write to output FIFO, and DMA control module reads the video data of output FIFO; The implementation procedure of the whole task of described flow process control unit control; The needed processing parameter of algorithm parameter FIFO storage convergent-divergent algorithm unit; Video rotation comprises rotation storage control unit, rotation FIFO and rotation control unit; Rotation memory cell control rotation FIFO, completes the access of video data; Rotation control unit completes the rotation task to rotation storage control unit data streams read;
Described HD video display module comprises simultaneous display unit, asynchronous display unit, display adapter and interface sequence converter unit; The simultaneous display of real-time video is supported in described simultaneous display unit; The asynchronous display that described asynchronous display support is not high to requirement of real-time; Described synchronous or asynchronous display unit receives the display video data of described DMA control module, through synchronous or asynchronous process, video data transmitting is delivered to the sequential that display adapter completes the capable synchronous sequence of video data frame and physical interface and change; Between described interface sequence converter unit and adapter, arbitrate and reply, the interface conversion of transfer of data and sequencing control, delivers to outside liquid crystal display by display video data and shows.
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| CN109194847A (en) * | 2018-09-12 | 2019-01-11 | 深圳市风扇屏技术有限公司 | A kind of integrated chip for holographic fan screen |
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