CN103944372B - A kind of IGBT Drive Protecting Circuit - Google Patents
A kind of IGBT Drive Protecting Circuit Download PDFInfo
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Abstract
The present invention discloses a kind of IGBT Drive Protecting Circuit, comprise: be arranged between input terminal with output terminal for controlling upper pipe IGBT and the input terminal being connected successively, upper pipe short pulse suppression circuit, upper pipe firstorder circuit, upper pipe dead band time delay circuit, upper pipe clamping protective circuit, and control lower pipe IGBT and the lower pipe short pulse suppression circuit connected successively, lower pipe firstorder circuit, lower pipe dead band time delay circuit, lower pipe clamping protective circuit; The IGBT Drive Protecting Circuit of the present invention adopts simple hardware circuit, suppresses short pulse, it is achieved IGBT upper, lower tube dead band delays time to control, and it is anti-interference to have diode clamping circuit, and not only cost is low, and reliability is also high.
Description
Technical field
The present invention relates to current transformer, especially a kind of IGBT Drive Protecting Circuit of the inner power cell of current transformer.
Background technology
When current transformer works, upper pipe IGBT and lower pipe IGBT on the inner same bridge arm of its power cell can not be simultaneously open-minded when driving, and when upper and lower two pipes replace switch, a pipe is opened to turn off with another pipe and must be ensured to have certain dead band time delay in time.
The scheme solving at present above-mentioned dead band time delay problem has: 1, adopt special integrated drive, but this kind of special integrated drive price height, for delivery date length, maintainable poor; 2, adopting software control, but software control freedom from jamming is poor, software runs IGBT after flying or crashing and easily damages.
Summary of the invention
For solving the problems of the technologies described above, it is an object of the invention to provide the IGBT Drive Protecting Circuit that a kind of price is lower, be convenient to maintenance, strong interference immunity.
The technical solution used in the present invention is:
A kind of IGBT Drive Protecting Circuit, it is characterised in that comprising:
One input terminal, this input terminal receives the two-way pwm signal that external control device exports, and this two-way pwm signal is designated as PWM-A, PWM-B;
Pipe short pulse suppression circuit on one, its input terminus is connected with the PWM-A signal end of input terminal;
Pipe short pulse suppression circuit once, its input terminus is connected with the PWM-B signal end of input terminal;
Pipe firstorder circuit on one, it is connected to pipe short pulse suppression circuit output end, for providing time constant t1;
Pipe firstorder circuit once, it is connected to lower pipe short pulse suppression circuit output end, for providing time constant t2;
Pipe dead band time delay circuit on one, its input terminus is connected to pipe short pulse suppression circuit output end;
Pipe dead band time delay circuit once, its input terminus is connected to lower pipe short pulse suppression circuit output end;
Pipe clamping protective circuit on one, its input terminus is connected to the output terminal of pipe dead band time delay circuit;
Pipe clamping protective circuit once, its input terminus is connected to the output terminal of lower pipe dead band time delay circuit;
One output terminal, this output terminal comprises two-way pwm signal end, is respectively PWM1, PWM2, and wherein, PWM1 signal end connects upper pipe clamping protective circuit, and PWM2 signal end connects lower pipe clamping protective circuit.
Further, described upper pipe short pulse suppression circuit comprises the first electric capacity, the first comparer, the 3rd resistance, the first diode; This first electric capacity one end connects PWM-A signal end, the other end ground connection; Between the positive input terminal that 3rd resistance and the first diode are connected on the first comparer and output terminal, the positive input terminal of this first comparer is also connected with PWM-A signal end, the negative input end of this first comparer is threshold voltage input terminus, and the output terminal of this first comparer is the output terminal of upper pipe short pulse suppression circuit.
Further, described lower pipe short pulse suppression circuit comprises the 2nd electric capacity, the 2nd comparer, the 4th resistance, the 2nd diode; 2nd electric capacity one end connects PWM-B signal end, the other end ground connection; Between the positive input terminal that 4th resistance and the 2nd diode are connected on the 2nd comparer and output terminal, the positive input terminal of the 2nd comparer is also connected with PWM-B signal end, the negative input end of the 2nd comparer is threshold voltage input terminus, and the output terminal of the 2nd comparer is the output terminal of lower pipe short pulse suppression circuit.
Further, described upper pipe firstorder circuit comprise connect successively from power input+VCC the 5th resistance, the 3rd electric capacity, 3rd electric capacity ground connection, tie point Q1 between 5th resistance and the 3rd electric capacity is connected with upper pipe short pulse suppression circuit output end, and time constant t1 equals the 5th resistance and the product of the 3rd electric capacity.
Further, described upper pipe dead band time delay circuit comprises the 3rd comparer, the first schmitt inverter, the 7th resistance, the 9th resistance; 3rd comparer power supply is input as+VCC and ground, the reverse input terminus of the 3rd comparer is connected with upper pipe short pulse suppression circuit output end, its positive input is threshold V T H2 input terminus and the 7th resistance, the 9th resistance extremely+VCC that connects successively, its output terminal respectively tie point Q3 with the input terminus of the first schmitt inverter, the 7th resistance and the 9th resistance be connected, the output terminal of the first schmitt inverter is the output terminal of upper pipe dead band time delay circuit; It is dead band time Td that 3rd comparator output terminal lags behind the difference of the 3rd comparer input time flip-flop transition, and the funtcional relationship of Td and threshold V T H2 is VTH2=VCC* [1-exp (-Td/t1)].
Further, described lower pipe firstorder circuit comprise connect successively from power input+VCC the 6th resistance, the 4th electric capacity, 4th electric capacity ground connection, tie point Q2 between 6th resistance and the 4th electric capacity is connected with upper pipe short pulse suppression circuit output end, and time constant t2 equals the 6th resistance and the product of the 4th electric capacity.
Further, described lower pipe dead band time delay circuit comprises the 4th comparer, the 2nd schmitt inverter, the 8th resistance, the tenth resistance; 4th comparer power supply is input as+VCC and ground, the reverse input terminus of the 4th comparer is connected with lower pipe short pulse suppression circuit output end, its positive input is threshold V T H2 input terminus and the 8th resistance, the tenth resistance extremely+VCC that connects successively, its output terminal respectively tie point Q4 with the input terminus of the 2nd schmitt inverter, the 8th resistance and the tenth resistance be connected, the output terminal of the 2nd schmitt inverter is the output terminal of lower pipe dead band time delay circuit; It is dead band time Td that 4th comparator output terminal lags behind the difference of the 4th comparer input time flip-flop transition, and the funtcional relationship of Td and threshold V T H2 is VTH2=VCC* [1-exp (-Td/t1)].
Further, described upper pipe clamping protective circuit comprise connect successively from power supply+VCC the 3rd diode, the 4th diode, the 4th diode ground connection, the tie point Q5 between its 3rd diode the 4th diode is connected to the output terminal of pipe dead band time delay circuit; Described lower pipe clamping protective circuit comprise connect successively from power supply+VCC the 5th diode, the 6th diode, the 6th diode ground connection, the tie point Q6 between its 5th diode, the 6th diode is connected to the output terminal of lower pipe dead band time delay circuit.
Further, it is connected with the first resistance between the positive input terminal of the first comparer and PWM-A signal end.
Further, it is connected with the 2nd resistance between the positive input terminal of described 2nd comparer and PWM-B signal end.
The useful effect of the present invention:
The IGBT Drive Protecting Circuit of the present invention adopts simple hardware circuit, suppresses short pulse, it is achieved IGBT upper, lower tube dead band delays time to control, and it is anti-interference to have diode clamping circuit, and not only cost is low, and reliability is also high.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further.
Fig. 1 is the schematic circuit of IGBT Drive Protecting Circuit of the present invention;
Fig. 2 is the 3rd comparer U1D and the input voltage waveform figure of the 4th comparer U1A;
Fig. 3 is the oscillogram that PWM width modulation signal generates dead band time Td.
Embodiment
With reference to, shown in Fig. 1, a kind of IGBT Drive Protecting Circuit, comprising:
One input terminal J1, this input terminal receives the two-way pwm signal that external control device exports, and this two-way pwm signal is designated as PWM-A, PWM-B;
Pipe short pulse suppression circuit 10 on one, on this, pipe short pulse suppression circuit 10 comprises the first electric capacity C1, the first comparer U1C, the 3rd resistance R3, the first diode D1; This first electric capacity C1 one end connects PWM-A signal end, the other end ground connection; Between the positive input terminal that 3rd resistance R3 and the first diode D1 is connected on the first comparer U1C and output terminal, the first resistance R1 it is connected with between the positive input terminal of the first comparer U1C and PWM-A signal end, the negative input end of this first comparer U1C is threshold V T H1 input terminus, and the output terminal of this first comparer U1C is the output terminal of upper pipe short pulse suppression circuit 10;
Pipe short pulse suppression circuit 20 once, this lower pipe short pulse suppression circuit 20 comprises the 2nd electric capacity C2, the 2nd comparer U1B, the 4th resistance R4, the 2nd diode D2; 2nd electric capacity C2 one end connects PWM-B signal end, the other end ground connection; Between the positive input terminal that 4th resistance R4 and the 2nd diode D2 is connected on the 2nd comparer U1B and output terminal, the 2nd resistance R2 it is connected with between the positive input terminal of the 2nd comparer U1B and PWM-B signal end, the negative input end of the 2nd comparer U1B is threshold voltage input terminus, and the output terminal of the 2nd comparer U1B is the output terminal of lower pipe short pulse suppression circuit 20;
Pipe firstorder circuit 30 on one; for providing time constant t1; on this, pipe firstorder circuit 30 comprises the 5th resistance R5, the 3rd electric capacity C3 that connect successively from power input+VCC; 3rd electric capacity C3 ground connection; tie point Q1 between 5th resistance R5 and the 3rd electric capacity C3 is connected with upper pipe short pulse suppression circuit 10 output terminal, and time constant t1 equals the 5th resistance R5 and the product of the 3rd electric capacity C3;
Pipe firstorder circuit 40 once; for providing time constant t2; this lower pipe firstorder circuit 40 comprises the 6th resistance R6, the 4th electric capacity C4 that connect successively from power input+VCC; 4th electric capacity C4 ground connection; tie point Q2 between 6th resistance R6 and the 4th electric capacity C4 is connected with upper pipe short pulse suppression circuit 10 output terminal, and time constant t2 equals the 6th resistance R6 and the product of the 4th electric capacity C4;
Pipe dead band time delay circuit 50 on one, on this, pipe dead band time delay circuit 50 comprises the 3rd comparer U1D, the first schmitt inverter U2A, the 7th resistance R7, the 9th resistance R9;3rd comparer U1D power supply is input as+VCC and ground, the reverse input terminus of the 3rd comparer U1D is connected with upper pipe short pulse suppression circuit 10 output terminal, its positive input is threshold V T H2 input terminus and the 7th resistance R7, the 9th resistance R9 extremely+VCC that connects successively, its output terminal is connected with the input terminus of the first schmitt inverter U2A, the tie point Q3 of the 7th resistance R7 and the 9th resistance R9 respectively, and the output terminal of the first schmitt inverter U2A is the output terminal of upper pipe dead band time delay circuit 50; It is dead band time Td that 3rd comparer U1D output terminal lags behind the difference of the 3rd comparer U1D input time flip-flop transition, and the funtcional relationship of Td and threshold V T H2 is VTH2=VCC* [1-exp (-Td/t1)];
Pipe dead band time delay circuit 60 once, this lower pipe dead band time delay circuit 60 comprises the 4th comparer U1A, the 2nd schmitt inverter U2B, the 8th resistance R8, the tenth resistance R10; 4th comparer U1A power supply is input as+VCC and ground, the reverse input terminus of the 4th comparer U1A is connected with lower pipe short pulse suppression circuit 20 output terminal, its positive input is threshold V T H2 input terminus and the 8th resistance R8, the tenth resistance R10 extremely+VCC that connects successively, its output terminal is connected with the input terminus of the 2nd schmitt inverter U2B, the tie point Q4 of the 8th resistance R8 and the tenth resistance R10 respectively, and the output terminal of the 2nd schmitt inverter U2B is the output terminal of lower pipe dead band time delay circuit 60; It is dead band time Td that 4th comparer U1A output terminal lags behind the difference of the 4th comparer U1A input time flip-flop transition, and the funtcional relationship of Td and threshold V T H2 is VTH2=VCC* [1-exp (-Td/t1)];
Pipe clamping protective circuit 70 on one, upper pipe clamping protective circuit 70 comprises the 3rd diode D3, the 4th diode D4 that connect successively from power supply+VCC, 4th diode D4 ground connection, the tie point Q5 between its 3rd diode D3 and the 4th diode D4 is connected to the output terminal of pipe dead band time delay circuit 50;
Pipe clamping protective circuit 80 once, this lower pipe clamping protective circuit 80 comprises the 5th diode D5, the 6th diode D6 that connect successively from power supply+VCC, 6th diode D6 ground connection, the tie point Q6 between its 5th diode D5, the 6th diode D6 is connected to the output terminal of lower pipe dead band time delay circuit 60;
One output terminal J2, this output terminal comprises two-way pwm signal end, is respectively PWM1, PWM2, and wherein, PWM1 signal end connects upper pipe clamping protective circuit 70, PWM2 signal end and connects lower pipe clamping protective circuit 80.
As shown in Figure 2, being the 3rd comparer U1D and the input voltage waveform of the 4th comparer U1A, transverse axis is time t, and the longitudinal axis is input voltage amplitude V, Vs is crest voltage.
The principle of work of the present invention is:
IGBT Drive Protecting Circuit of the present invention is placed in external control device (such as DSP, control IC etc.) and isolate between optocoupler, isolation optocoupler connects, pipe IGBT, by in the input of external control device, the width modulation signal PWM-A of lower pipe IGBT, PWM-B is to input terminal J1, and the upper pipe short pulse suppression circuit 10 through the present invention, lower pipe short pulse suppression circuit 20 carries out short pulse suppression, and upper pipe dead band time delay circuit 50, the effect of lower pipe dead band time delay circuit 60 produces dead band time Td, spread out of supreme through output terminal J2, lower two pipe IGBT, make, when lower two pipe IGBT replace switch, one pipe is opened to turn off with another pipe certain dead band time delay time Td in time, the effect of diode clamping circuit simultaneously is the PWM1 that can prevent from exporting, PWM2 signal is too high or too low, enhance anti-interference performance.
Concrete, first electric capacity C1, the 2nd electric capacity C2 of input terminus are as filter capacitor, can the unnecessary ripple of filtering, the first resistance R1 and the 2nd resistance R2 of input terminus are for finely tuning input voltage, first comparer U1C and the 2nd comparer U1B is for suppressing short pulse, and by the setting of threshold V T H1, comparer U1C, U1B can suppress the short pulse lower than VTH1, wherein VTH1 can value be 5V, 8V, 10V, 12V, and VTH1 value principle is the VCC of 0.7 ~ 0.8 times;
As shown in Figure 3, and composition graphs 1, it is that input is complementary without width modulation signal PWM-A, PWM-B of IGBT Drive Protecting Circuit of the present invention process, without dead band; When pwm signal inputs from terminal JI, through R1, C1; The positive input terminal of comparer U1 is entered, i.e. the 7,9th pin after R2, C2 filtering. Above pipe circuit is example, when PWM-A positive rise arrives, first comparer U1C the 14th pin exports as open collector, comparer U1D inputs (the 10th pin) and puts current potential by R5, the firstorder circuit time constant that C3 is formed determines, regulate VTH2 value, comparer U1D can be made to export (the 13rd pin) and to lag behind comparer U1D input (the 10th pin) time flip-flop transition, this time Td is the dead band time (Deadtime), and dead band time Td and VTH2 funtcional relationship are Vth2=VCC* [1-exp (-Td/R5*C3)]; When PWM negative edge arrives, 14th pin exports as lower level, comparer U1D input (the 10th pin) puts current potential and is pulled low to rapidly low potential (Fig. 2), show that the dead band time delay of comparer U1D only acts on the positive rise of pwm signal, because the high level of positive rise is only the signal triggering IGBT upper, lower tube switch;
Such as Fig. 1, comparer U1D and U1A is oppositely input, and after its dead band time-lag action, pwm signal is reverse, in order to make output phase place and comparer input phase place be consistent, is provided with schmitt inverter U2A and U2B; If certainly not arranging schmitt inverter U2A and U2B, and by comparer U1D and U1A just to input, being also the effect that can realize dead band time delay, this just belongs to another embodiment of this scheme; But this scheme arranges schmitt inverter U2A and U2B can carry out shaping to output waveform, it is possible to make waveform more level and smooth.
The foregoing is only the preferred embodiments of the present invention, the present invention is not limited to above-mentioned enforcement mode, as long as the technical scheme realizing the object of the invention with basic same approach all belongs within protection scope of the present invention.
Claims (3)
1. an IGBT Drive Protecting Circuit, it is characterised in that comprising:
One input terminal (J1), this input terminal receives the two-way pwm signal that external control device exports, and this two-way pwm signal is designated as PWM-A, PWM-B;
Pipe short pulse suppression circuit (10) on one, its input terminus is connected with the PWM-A signal end of input terminal (J1); Described upper pipe short pulse suppression circuit (10) comprises the first electric capacity (C1), the first comparer (U1C), the 3rd resistance (R3), the first diode (D1); This first electric capacity (C1) one end connects PWM-A signal end, the other end ground connection; Between the positive input terminal that 3rd resistance (R3) and the first diode (D1) are connected on the first comparer (U1C) and output terminal, the positive input terminal of this first comparer (U1C) is also connected with PWM-A signal end, the negative input end of this first comparer (U1C) is threshold voltage input terminus, and the output terminal of this first comparer (U1C) is the output terminal of upper pipe short pulse suppression circuit (10)
Pipe short pulse suppression circuit (20) once, its input terminus is connected with the PWM-B signal end of input terminal (J1);Described lower pipe short pulse suppression circuit (20) comprises the 2nd electric capacity (C2), the 2nd comparer (U1B), the 4th resistance (R4), the 2nd diode (D2); 2nd electric capacity (C2) one end connects PWM-B signal end, the other end ground connection; Between the positive input terminal that 4th resistance (R4) and the 2nd diode (D2) are connected on the 2nd comparer (U1B) and output terminal, the positive input terminal of the 2nd comparer (U1B) is also connected with PWM-B signal end, the negative input end of the 2nd comparer (U1B) is threshold voltage input terminus, and the output terminal of the 2nd comparer (U1B) is the output terminal of lower pipe short pulse suppression circuit (20);
Pipe firstorder circuit (30) on one, it is connected to pipe short pulse suppression circuit (10) output terminal, for providing time constant t1; Described upper pipe firstorder circuit (30) comprise connect successively from power input+VCC the 5th resistance (R5), the 3rd electric capacity (C3), 3rd electric capacity (C3) ground connection, tie point Q1 between 5th resistance (R5) and the 3rd electric capacity (C3) is connected with upper pipe short pulse suppression circuit (10) output terminal, and time constant t1 equals the product of the 5th resistance (R5) with the 3rd electric capacity (C3);
Pipe firstorder circuit (40) once, it is connected to lower pipe short pulse suppression circuit (20) output terminal, for providing time constant t2; Described lower pipe firstorder circuit (40) comprise connect successively from power input+VCC the 6th resistance (R6), the 4th electric capacity (C4), 4th electric capacity (C4) ground connection, tie point Q2 between 6th resistance (R6) and the 4th electric capacity (C4) is connected with upper pipe short pulse suppression circuit (10) output terminal, and time constant t2 equals the 6th resistance (R6) and the product of the 4th electric capacity (C4);
Pipe dead band time delay circuit (50) on one, its input terminus is connected to pipe short pulse suppression circuit (10) output terminal; Described upper pipe dead band time delay circuit (50) comprises the 3rd comparer (U1D), the first schmitt inverter (U2A), the 7th resistance (R7), the 9th resistance (R9); 3rd comparer (U1D) power supply is input as+VCC and ground, the reverse input terminus of the 3rd comparer (U1D) is connected with upper pipe short pulse suppression circuit (10) output terminal, its positive input is threshold V T H2 input terminus and the 7th resistance (R7), the 9th resistance (R9) extremely+VCC that connects successively, its output terminal respectively tie point Q3 with the input terminus of the first schmitt inverter (U2A), the 7th resistance (R7) and the 9th resistance (R9) be connected, the output terminal of the first schmitt inverter (U2A) is the output terminal of upper pipe dead band time delay circuit (50); 3rd comparer (U1D) output terminal lags behind the 3rd comparer (U1D) flip-flop transition, and to input the difference of time be dead band time Td, and the funtcional relationship of Td and threshold V T H2 is VTH2=VCC* [1-exp (-Td/t1)];
Pipe dead band time delay circuit (60) once, its input terminus is connected to lower pipe short pulse suppression circuit (20) output terminal; Described lower pipe dead band time delay circuit (60) comprises the 4th comparer (U1A), the 2nd schmitt inverter (U2B), the 8th resistance (R8), the tenth resistance (R10); 4th comparer (U1A) power supply is input as+VCC and ground, the reverse input terminus of the 4th comparer (U1A) is connected with lower pipe short pulse suppression circuit (20) output terminal, its positive input is threshold V T H2 input terminus and the 8th resistance (R8), the tenth resistance (R10) extremely+VCC that connects successively, its output terminal respectively tie point Q4 with the input terminus of the 2nd schmitt inverter (U2B), the 8th resistance (R8) and the tenth resistance (R10) be connected, the output terminal of the 2nd schmitt inverter (U2B) is the output terminal of lower pipe dead band time delay circuit (60);4th comparer (U1A) output terminal lags behind the 4th comparer (U1A) flip-flop transition, and to input the difference of time be dead band time Td, and the funtcional relationship of Td and threshold V T H2 is VTH2=VCC* [1-exp (-Td/t1)];
Pipe clamping protective circuit (70) on one, its input terminus is connected to the output terminal in pipe dead band time delay circuit (50); Described upper pipe clamping protective circuit (70) comprise connect successively from power supply+VCC the 3rd diode (D3), the 4th diode (D4), 4th diode (D4) ground connection, the tie point Q5 between its 3rd diode (D3) and the 4th diode (D4) is connected to the output terminal in pipe dead band time delay circuit (50);
Pipe clamping protective circuit (80) once, its input terminus is connected to the output terminal of lower pipe dead band time delay circuit (60); Described lower pipe clamping protective circuit (80) comprise connect successively from power supply+VCC the 5th diode (D5), the 6th diode (D6), 6th diode (D6) ground connection, the tie point Q6 between its 5th diode (D5), the 6th diode (D6) is connected to the output terminal of lower pipe dead band time delay circuit (60);
One output terminal (J2), this output terminal comprises two-way pwm signal end, is respectively PWM1, PWM2, and wherein, PWM1 signal end connects upper pipe clamping protective circuit (70), and PWM2 signal end connects lower pipe clamping protective circuit (80).
2. a kind of IGBT Drive Protecting Circuit according to claim 1, it is characterised in that: it is connected with the first resistance (R1) between the positive input terminal of the first comparer (U1C) and PWM-A signal end.
3. a kind of IGBT Drive Protecting Circuit according to claim 1, it is characterised in that: it is connected with the 2nd resistance (R2) between the positive input terminal of described 2nd comparer (U1B) and PWM-B signal end.
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| CN104678327B (en) * | 2015-03-24 | 2018-04-24 | 陕西夸克自控科技有限公司 | A kind of high voltage pulse load circuit and method of work |
| CN109347467B (en) * | 2015-11-16 | 2022-11-29 | 许继集团有限公司 | IGBT (insulated Gate Bipolar transistor) turn-on control method and IGBT turn-off control method |
| CN106787641B (en) * | 2016-12-28 | 2019-05-28 | 湘潭大学 | A kind of expansible isolated power supply circuit of On-off signal for protective relaying device |
| WO2023059767A1 (en) * | 2021-10-06 | 2023-04-13 | Retela Leasing, Llc | Power converters using precise timing control |
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| CN103701439A (en) * | 2013-12-24 | 2014-04-02 | 深圳市汇川技术股份有限公司 | Single-input double-output pulse width modulation (PWM) signal producing circuit |
| CN203859677U (en) * | 2014-04-11 | 2014-10-01 | 广东明阳龙源电力电子有限公司 | IGBT drive protective circuit |
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|---|---|
| CN103944372A (en) | 2014-07-23 |
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