CN103887191A - Semiconductor device and method of making bumpless flipchip interconnect structures - Google Patents

Semiconductor device and method of making bumpless flipchip interconnect structures Download PDF

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Publication number
CN103887191A
CN103887191A CN201310651453.6A CN201310651453A CN103887191A CN 103887191 A CN103887191 A CN 103887191A CN 201310651453 A CN201310651453 A CN 201310651453A CN 103887191 A CN103887191 A CN 103887191A
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China
Prior art keywords
substrate
contact pad
semiconductor element
conductive layer
electrocondution slurry
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CN201310651453.6A
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Chinese (zh)
Inventor
金敬文
李求鸿
李在学
金永澈
L.洪
P.C.马里穆图
S.安德森
林诗轩
池熺朝
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Priority claimed from US14/039,418 external-priority patent/US9240331B2/en
Application filed by Stats Chippac Pte Ltd filed Critical Stats Chippac Pte Ltd
Publication of CN103887191A publication Critical patent/CN103887191A/en
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Abstract

The invention relates to a semiconductor device and a method of making bumpless flipchip interconnect structures. The semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over the contact pads of the substrate. The contact pads include aluminum. Contact pads of the semiconductor die are disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure between the contact pads of the semiconductor die and the contact pads of the substrate. The interconnect structure is formed directly on the contact pads of the substrate and semiconductor die. The contact pads of the semiconductor die are etched prior to reflowing the aluminum-wettable conductive paste. An epoxy pre-dot maintains a separation between the semiconductor die and substrate.

Description

Semiconductor device and the method for making bumpless flipchip interconnect structure
Claimed national priority
The U.S. Provisional Application No.61/740 that the application submits on December 20th, 1,395 rights and interests, are herein incorporated this application by reference.
Technical field
Present invention relates in general to semiconductor device, and relate more particularly to semiconductor device and form the method for bumpless (bumpless) flipchip interconnect structure.
Background technology
Semiconductor device is common in modern electronic product.Semiconductor device changes aspect the number of electric component and density.Discrete semiconductor device comprises the electric component of a type conventionally, for example light-emitting diode (LED), small-sized signal transistor, resistor, capacitor, inductor and power metal oxide semiconductor field-effect transistor (MOSFET).Integrated-semiconductor device typically comprises hundreds of to millions of electric components.The example of integrated-semiconductor device comprises microcontroller, microprocessor, charge-coupled device (CCD), solar cell and Digital Micromirror Device (DMD).
Semiconductor device carry out permitted several functions, such as signal processing, supercomputing, transmit and receive electromagnetic signal, control electronic device, by sunlight be transformed into electricity and for TV show establishment visual projection.Semiconductor device sees in the field of amusement, communication, power transfer, network, computer and consumer products.Semiconductor device also sees in Military Application, aircraft industry, automobile, industrial control unit (ICU) and office equipment.
Semiconductor device has utilized the electrical properties of semi-conducting material.The structure of semi-conducting material allows by applying electric field or substrate current or handling its conductivity by doping process.Doping is incorporated in semi-conducting material impurity to handle and control the conductivity of semiconductor device.
Semiconductor device comprises active and passive electric structure.Comprise the flowing of active structure control electric current of ambipolar and field-effect transistor.By changing applying of doping level and electric field or substrate current, transistor promotes or the flowing of about beam electronic current.The passive structures that comprises resistor, capacitor and inductor has created the relation of carrying out between the necessary voltage and current of various electric functions.Passive and active structure is electrically connected to form circuit, and this circuit makes semiconductor device can carry out supercomputing and other useful functions.
Conventionally use two complex fabrication process (being that manufacture front end manufacture and rear end) to manufacture semiconductor device, each in this front end manufacture and rear end manufacture comprises a hundreds of step potentially.Front end manufacture comprises multiple tube cores is formed on the surface of semiconductor wafer.Each semiconductor element is conventionally identical and comprise by being electrically connected circuit active and that passive component forms.Rear end is manufactured the wafer list comprising from completing and is cut (singulate) individual semiconductor element and encapsulate this tube core so that support structure and environment isolation to be provided.Term as used herein " semiconductor element " refer to the odd number of this word and plural form the two, and correspondingly can refer to single semiconductor device and multiple semiconductor device the two.
A target of semiconductor manufacture is to produce less semiconductor device.More gadget expends still less power conventionally, has more high-performance, and can be produced more efficiently.In addition, less semiconductor device has the less area of coverage, and this expects for less final products.Can realize less semi-conductor die size by the improvement that obtains having in the front-end process of semiconductor element of less, more highdensity active and passive component.Backend process can obtain having by the improvement in electrical interconnection and encapsulating material the semiconductor packages of the less area of coverage.
Semiconductor maker also attempts to reduce the cost of producing this device in reducing the required time of production semiconductor device.Semiconductor manufacture needs many processing steps, comprises some steps of setting up simply the interconnection between semiconductor element and other electronic devices.Each additional process steps increased produce required time of semiconductor device and cost the two.Each processing step has also been introduced in formation technique abnormal chance has been occurred.For example, the technique of formation flip chip interconnects is relatively consuming time and expensive.
Summary of the invention
There are the needs of simple, the low cost interconnection structure to flip chip devices.Correspondingly, in one embodiment, the present invention is a kind of method of making semiconductor device, comprises the steps: to provide the substrate that comprises contact pad; Mask is arranged on substrate; Aluminium wettability electrocondution slurry is printed on the contact pad of substrate; Semiconductor element is arranged on aluminium wettability electrocondution slurry; And aluminium wettability electrocondution slurry is refluxed to form interconnection structure on the contact pad of substrate.
In another embodiment, the present invention is a kind of method of making semiconductor device, comprises the steps: to provide substrate; Mask is arranged on substrate; Aluminium wettability electrocondution slurry is deposited on substrate; Semiconductor element is arranged on aluminium wettability electrocondution slurry; And aluminium wettability electrocondution slurry is refluxed to form interconnection structure on substrate.
In another embodiment, the present invention is a kind of method of making semiconductor device, comprises the steps: to provide substrate; Electrocondution slurry is deposited on substrate to form interconnection structure; And semiconductor element is arranged on electrocondution slurry.
In another embodiment, the present invention is a kind of semiconductor device that comprises substrate, and this substrate comprises contact pad.Electrocondution slurry is deposited on contact pad.Semiconductor element is arranged on electrocondution slurry.
Brief description of the drawings
Fig. 1 illustrates a kind of printed circuit board (PCB) (PCB), has the dissimilar encapsulation that is installed to its surface;
Fig. 2 a-2c diagram is installed to the further details of the representative semiconductor packages of PCB;
Fig. 3 a-3c diagram has the semiconductor wafer of multiple semiconductor elements of You Ju road (saw street) separation;
Fig. 4 a-4e diagram is used and is directly printed on the flip chip interconnects that the slurry on contact pad forms on substrate;
Fig. 5 a-5e diagram is used and is directly printed on the flip chip interconnects that the slurry on contact pad forms on substrate;
Fig. 6 a-6e diagram is used and is directly printed on the flip chip interconnects that the slurry on contact pad forms on substrate;
Fig. 7 diagram joins the flip chip devices of the substrate with the electrocondution slurry directly contacting with contact pad to; And
Fig. 8 a-8f diagram is used the further details of the flip chip interconnects of Fig. 6 a-6e that is directly printed on the slurry on contact pad and form.
Embodiment
In one or more embodiment in the following description, with reference to accompanying drawing, the present invention is described, in the accompanying drawings, the same or similar element of similar numeral.Although according to describing the present invention for the optimal mode of realizing the object of the invention, but those skilled in the art will recognize that, the invention is intended to cover as can be included in as by as obtain replacement, amendment and the equivalent in the claims of open and accompanying drawing support below and spirit and scope of the invention that equivalent limits thereof.
Conventionally use two complex fabrication process (manufacture front end manufacture and rear end) to manufacture semiconductor device.Front end manufacture comprises multiple tube cores is formed on the surface of semiconductor wafer.Each tube core on wafer comprises active and electrical passive components, and they are electrically connected to form functional circuit.Active electric component (such as transistor and diode) has the mobile ability of controlling electric current.Electrical passive components (such as capacitor, inductor and resistor) creates the relation between the necessary voltage and current of executive circuit function.
By series of process step (comprising doping, deposition, photoetching, etching and planarization), passive and active parts are formed on the surface of semiconductor wafer.Doping is incorporated into impurity in semi-conducting material by the technology such as Implantation or thermal diffusion.Doping process is revised the conductivity of semi-conducting material in active device by dynamically changing semi-conducting material conductivity in response to electric field or substrate current.Transistor comprise as transistor can be promoted in the time applying electric field or substrate current or about beam electronic current mobile necessary the type of the change doping of arranging and the district of degree.
Active and passive component is formed by the layer of the material with different electrical propertiess.Can form these layers by various deposition techniques, described deposition technique is partly determined by the type of deposited material.For example, thin film deposition can comprise chemical vapor deposition (CVD), physical vapor deposition (PVD), metallide and electroless plating technique.Each layer is patterned conventionally to be formed with the electrical connections between source block part, passive component part or each parts.
Can carry out patterning to layer with photoetching, this photoetching comprise by light-sensitive material (for example photoresist) be deposited on to be patterned layer on.Make to use up pattern is transferred to photoresist from photomask.In one embodiment, use solvent to remove the part that is subject to light of photoresist pattern, thereby expose the part of the lower surface layer that will be patterned.In another embodiment, use solvent to remove the part that is not subject to light (negative photoresist) of photoresist pattern, thereby expose the part of the lower surface layer that will be patterned.Remove the remainder of photoresist, thereby leave the layer through patterning.Alternatively, in the region by the technology of using such as electroless plating and metallide, material Direct precipitation being formed to previous deposition/etch processes or blank, the material of some type is carried out to patterning.
Patterning is following basic operation: the part that removes the top layer on semiconductor wafer surface by this basic operation.Can use photoetching, photomask, mask, oxide or metal removal, photography and mould printing and micro-lithography to remove the part of semiconductor wafer.Photoetching be included in light shield (reticle) or photomask, form pattern and by this pattern transfer in the superficial layer of semiconductor wafer.Photoetching is formed on active and horizontal scale passive component on the surface of semiconductor wafer with two step process.First, by the pattern transfer on light shield or mask in photoresist layer.Photoresist is a kind of light-sensitive material, and it is being exposed to the light time and stands the change of structure and character.Changing the structure of photoresist and the technique of character occurs as negative effects photoresist or positivity effect photoresist.Secondly, photoresist layer is transferred in wafer surface.In the time that the semiconductor wafer top layer part not covered by photoresist is removed in etching, there is transfer printing.The chemical composition of photoresist makes: in the removed while of semiconductor wafer top layer part not covered by photoresist, photoresist keeps perfect and prevention substantially to be removed by chemical etching liquor.Can revise formation, expose and remove the technique of photoresist and remove the technique of the part of semiconductor wafer according to the result of used specific resist and expectation.
In negative effects photoresist, photoresist is exposed to light and becomes soluble situation from solvable situation in the technique that is called as polymerization.In polymerization, unpolymerized material is exposed to light or energy source, and polymer forms the etched cross-linked material of prevention.In most of negative resists, polymer is polyisoprene.Utilize chemical solvent or developer to remove soluble fraction (, not being exposed to the part of light) and can in resist layer, leave the hole corresponding with opaque pattern on light shield.The mask that its pattern is present in opacity is called as bright field (clear-field) mask.
In positivity effect photoresist, photoresist is exposed to light and becomes much solvable situation from relatively soluble situation being called as in the technique that light dissolves.In light dissolves, relatively soluble resist is exposed to suitable light energy and is converted into more soluble state.Can remove by the solvent in developing process the light dissolving part of resist.Basic positive photoresist polymer is novolac polymer, is also referred to as novolaks (novolak) resin.Utilize chemical solvent or developer to remove soluble fraction (, being exposed to the part of light) and can in resist layer, leave the hole corresponding with transparent pattern on light shield.The mask that its pattern is present in opacity is called as details in a play not acted out on stage, but told through dialogues (dark-field) mask.
After the top of removing the semiconductor wafer not covered by photoresist is divided, remove the remainder of photoresist, thereby leave the layer through patterning.Alternatively, in the region by the technology of using such as electroless plating and metallide, material Direct precipitation being formed to previous deposition/etch processes or blank, the material of some type is carried out to patterning.
Thin-film material deposition can be made on existing pattern bottom graph case expand and create non-homogeneous flat surfaces.Need even flat surfaces to produce the active and passive component of less and more intensive packaging.Planarization can be used to from the remove materials of wafer and produce even flat surfaces.Planarization comprises the surface that utilizes polishing pad to carry out polished wafer.The surface of adding grinding-material and eroding chemical to wafer during polishing.Any irregular terrain profiles has been removed in the combined machine effect of the grinding of chemicals and corrosiveness, thereby obtains even flat surfaces.
Rear end is manufactured and is referred to the wafer cutting completing or be singly cut into individual semiconductor element and then encapsulate this semiconductor element for support structure and environment isolation.In order singly to cut semiconductor element, along the wafer nonfunctional area that is called as saw road or trace to wafer notch (score) and make its fracture.Carry out wafer singulation with laser cutting instrument or saw blade.After singly cutting, by individual semiconductor element be installed to comprise for the contact pad of other system parts interconnection or the package substrate of pin.Then the contact pad forming is connected to the contact pad in encapsulation on semiconductor element.Can utilize soldering projection, stud bumps (stud bump), electrocondution slurry or line to engage to be electrically connected.Sealant or other moulding materials are deposited on to encapsulation above so that physical support and electrical isolation to be provided.Then the encapsulation completing be inserted in electrical system and make the function of semiconductor device available concerning other system parts.
Fig. 1 diagram has the electronic device 50 of chip carrier substrate or printed circuit board (PCB) (PCB) 52, on the surface of described chip carrier substrate or printed circuit board (PCB) (PCB) 52, multiple semiconductor packages is installed.According to application, electronic device 50 can have semiconductor packages or polytype semiconductor packages of one type.For illustration purpose, dissimilar semiconductor packages shown in Figure 1.
Electronic device 50 can be system independently, and it carries out one or more electric functions by semiconductor packages.Alternatively, electronic device 50 can be the subassembly of larger system.For example, electronic device 50 can be a part for cell phone, PDA(Personal Digital Assistant), digital video camcorder (DVC) or other electronic communication equipments.Alternatively, electronic device 50 can be that graphics card, network interface unit maybe can be inserted into other signal processing cards in computer.Semiconductor packages can comprise microprocessor, memory, application-specific integrated circuit (ASIC) (ASIC), logical circuit, analog circuit, radio frequency (RF) circuit, discrete device or other semiconductor elements or electric component.For product is accepted by market, miniaturization and weight saving are basic.The distance that can reduce between semiconductor device realizes more high density.
In Fig. 1, PCB 52 provides the general substrate of support structure and the electrical interconnection of the semiconductor packages for installing on PCB.With evaporation, metallide, electroless plating, silk screen printing other applicable metal deposition process are come from the teeth outwards or PCB 52 layer in formation conductive signal trace 54.Signal traces 54 provides the telecommunication between each in semiconductor packages, the parts of installing and other external system components.Trace 54 also provides to the power supply of each semiconductor packages and has connected and grounding connection.
In certain embodiments, semiconductor device has two package levels.First order encapsulation is a kind of for semiconductor element machinery and electricity being attached to the technology of intermediate carrier.Second level encapsulation comprises intermediate carrier machinery and electricity is attached to PCB.In other embodiments, semiconductor device can only have first order encapsulation, and tube core direct mechanical and electricity are installed to PCB therein.
For illustrative purposes, the first order encapsulation of several type is shown on PCB 52, comprises closing line encapsulation 56 and flip-chip 58.In addition, the second level encapsulation that several type has been installed is shown on PCB 52, comprise ball grid array (BGA) 60, bump chip carrier (BCC) 62, dual in-line package (DIP) 64, land grid array (LGA, land grid array) 66, multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70 and quad flat package 72.According to system requirements, the semiconductor packages of any combination and any combination of other electronic units that are configured with first and second grades of packaged types can be connected to PCB 52.In certain embodiments, electronic device 50 comprises single semiconductor packages of adhering to, and other embodiment require multiple interconnect package.By combine one or more semiconductor packages on single substrate, manufacturer can merge to prefabricated parts in electronic device and system.Because semiconductor packages comprises perfect function, so can manufacture electronic device by not too expensive parts and streamlined manufacturing process.The device obtaining unlikely breaks down and is not too expensive on manufacturing, thereby causes consumer's cost.
Fig. 2 a-2c illustrates exemplary semiconductor encapsulation.Fig. 2 a diagram is arranged on the further details of the DIP 64 on PCB 52.Semiconductor element 74 includes source region, and it comprises and is implemented as according to the electrical design of tube core and in tube core, forms and the analog or digital circuit of dielectric layer, conductive layer, passive device and the active device of electrical interconnection.For example, this circuit can comprise one or more transistors, diode, inductor, capacitor, resistor and other circuit elements that form in the active area of semiconductor element 74.Contact pad 76 is that electric conducting material (such as one or more layers of aluminium (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au) or silver (Ag), and is electrically connected to the circuit element in semiconductor element 74 interior formation.At the assembly process of DIP 64, use gold-silicon congruent melting layer or adhesion material (such as hot epoxy or epoxy resin) that semiconductor element 74 is installed to intermediate carrier 78.Package main body comprises the insulation-encapsulated material such as polymer or pottery.Lead wire of conductor 80 and closing line 82 provide the electrical interconnection between semiconductor element 74 and PCB 52.Sealant 84 is deposited on to encapsulation upper so that by preventing that moisture and particle from entering encapsulation and pollution semiconductor element 74 or closing line 82 and carrying out environmental protection.
Fig. 2 b diagram is arranged on the further details of the BCC 62 on PCB 52.Use bottom filling or epoxy resin adhesion material 92 that semiconductor element 88 is arranged on carrier 90.Closing line 94 provides the first order packaging interconnection between contact pad 96 and 98.Moulding compound or sealant 100 are deposited on semiconductor element 88 and closing line 94 to isolate for this device provides physical support and electricity.Use suitable metal depositing operation such as metallide or electroless plating contact pad 102 to be formed on the surface of PCB 52 in case oxidation.Contact pad 102 is electrically connected to the one or more conductive signal trace 54 in PCB 52.Between the contact pad 98 of BCC 62 and the contact pad 102 of PCB 52, form projection 104.
In Fig. 2 c, utilize the encapsulation of the flip chip first order that semiconductor element 58 is installed to intermediate carrier 106 face-down.The active area 108 of semiconductor element 58 comprises the analog or digital circuit that is implemented as the dielectric layer, conductive layer, passive device and the active device that form according to the electrical design of tube core.For example, this circuit can comprise other circuit elements in one or more transistors, diode, inductor, capacitor, resistor and active area 108.By projection 110, semiconductor element 58 electrical and mechanical connections are arrived to carrier 106.
Utilize and use the BGA mode second level encapsulation of projection 112 that BGA 60 electrical and mechanical connections are arrived to PCB 52.By projection 110, holding wire 114 and projection 112 by semiconductor element 58 be electrically connected to PCB 52 in conductive signal trace 54.Moulding compound or sealant 116 are deposited on semiconductor element 58 and carrier 106 to provide physical support and electrical isolation for device.Flip-chip semiconductor device provides active device from semiconductor element 58 the short-range missile power path to the conductive trace on PCB 52, to reduce signal propagation distance, reduce electric capacity and improve overall circuit performance.In another embodiment, in the situation that there is no intermediate carrier 106, can use the encapsulation of the flip chip first order by semiconductor element 58 direct mechanical and be electrically connected to PCB 52.
Fig. 3 a illustrates to have the base substrate material 122(for support structure such as silicon, germanium, GaAs, indium phosphide or carborundum) semiconductor wafer 120.On the wafer 120 that wafer area Huo Ju road 126 separates between as mentioned above by non-active, tube core, form multiple semiconductor elements or parts 124.Saw road 126 provides cutting zone to semiconductor wafer 120 is singly cut into individual semiconductor element 124.
Fig. 3 b illustrates the viewgraph of cross-section of a part for semiconductor wafer 120.Each semiconductor element 124 has back of the body surface 128 and active surperficial 130, and it comprises to be implemented as and forms in tube core according to the electrical design of tube core and function and the analog or digital circuit of dielectric layer, conductive layer, passive device and the active device of electrical interconnection.For example, this circuit can comprise one or more transistors, diode and other circuit elements with enforcement analog or digital circuit (such as digital signal processor (DSP), ASIC, memory or other signal processing circuits) in active surperficial 130 interior formation.Semiconductor element 124 can also comprise for the integrated passive devices of RF signal processing (IPD), such as inductor, capacitor and resistor.
Use PVD, CVD, metallide, electroless plating technique or other applicable metal deposition process that conductive layer 132 is formed on active surperficial 130.Conductive layer 132 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, Pd, Pt or other applicable electric conducting materials.Conductive layer 132 is operating as the contact pad that is electrically connected to the circuit on active surperficial 130.Conductive layer 132 can be formed in the contact pad being arranged side by side apart from edge first distance of semiconductor element 124, as shown in Fig. 3 b.Alternatively, conductive layer 132 can be formed contact pad, this contact pad is offset that in multiple row the first row contact pad is configured to apart from die edge the first distance, and is configured to apart from die edge second distance with the second row contact pad that the first row replaces.
Semiconductor wafer 120 stands as the electric test of a part for quality control technique and inspection.Artificial visual inspection and automation optical system are used to semiconductor wafer 120 to carry out and check.Can in the automation optical analysis of semiconductor wafer 120, use software.Visual examination method can adopt the equipment such as scanning electron microscopy, high strength or ultraviolet light or metallomicroscope.Check semiconductor wafer 120 for architectural characteristic (comprise warpage, varied in thickness, surface particles, scrambling, crack, delamination and fade).
Active and passive component in semiconductor element 124 stands the test at the wafer scale place to electric property and circuit function.Next for function and the each semiconductor element 124 of electrical parameters measure with probe or other test components.Probe be used to carry out with each semiconductor element 124 on node or the electrically contacting and provide contact pad 132 from electrostimulation to contact pad.Semiconductor element 124 is made a response to this electrostimulation, measures this reaction and itself and anticipation reaction are compared to the function with measuring semiconductor tube core.Electric test can comprise circuit function, lead-in wire integrality, resistivity, continuity, reliability, junction depth, Electrostatic Discharge, radio frequency (RF) performance, drive current, threshold current, leakage current and the special operating parameter of unit type.The inspection of semiconductor wafer 120 and electric test make the semiconductor element 124 can be by be designated as for the finished product tube core in semiconductor packages (KGD, known good die).
In Fig. 3 c, use saw blade or laser cutting instrument 134, by saw road 126, semiconductor wafer 120 is singly cut into individual semiconductor element 124.Can check and this individuality semiconductor element 124 of electric test for the mark of singly cutting after KGD.
Fig. 4 a-4e diagram is used slurry to be printed on substrate and forms flip chip interconnects to semiconductor element is arranged on this substrate.In Fig. 4 a, substrate 140 comprises the conductive layer 142 that uses PVD, CVD, metallide, electroless plating technique or other applicable metal deposition process to form on substrate.Conductive layer 142 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, Pd, Pt or other applicable electric conducting materials.Conductive layer 142 is operating as the circuit that is electrically connected on substrate 140 or the contact pad of trace.Conductive layer 142 can be formed in the contact pad being arranged side by side apart from edge first distance of substrate 140, as shown in Fig. 4 a.Alternatively, conductive layer 142 can be formed contact pad, this contact pad is offset that in multiple row the first row contact pad is configured to apart from edges of substrate the first distance, and is configured to apart from edges of substrate second distance with the second row contact pad that the first row replaces.In one embodiment, conductive layer 142 is to comprise being suitable for the compound that engages with aluminium wettability electrocondution slurry or scaling powder (flux) or the contact pad of alloy (comprising aluminium, copper and silicon).
In Fig. 4 b, mask or template 150 are arranged on the first surface of substrate 140.Mask 150 can be the insulating barrier that uses PVD, CVD, printing, spin coating, spraying, slot coated, cylinder coating, lamination, sintering or thermal oxidation to form.Mask 150 comprises SiO 2, Si 3n 4, SiON, Ta 2o 5, Al 2o 3, hafnium oxide (HfO 2), benzocyclobutene (BCB), polyimides (PI), polybenzoxazole (PBO), there is filler or fiber or do not there is the polymer dielectric resist of filler or fiber or there is similar structures and the one or more layer of the other materials of dielectric property.Alternatively, form template or mask 150 by etching, electroforming or laser cutting cause Al, Cu, Sn, Ni, Au, Ag, Ti, W, Pd, Pt or other applicable materials, to form the continuous mask with opening 152.Mask 150 has the opening 152 forming in the precalculated position corresponding with the conductive layer 142 of substrate 140.Preformed mask 150 is placed on substrate 140 to cover the predetermined portions of substrate 140 and expose opening 152 conductive layer 142 below.In one embodiment, mask 150 has and is less than 200 microns of (μ thickness m).Mask 150 can be that disposable use maybe can re-use to be printed on respectively on single substrate or multiple substrate, and should between using, clean the mask 150 that can re-use to prevent from polluting substrate 140.
In Fig. 4 c, the electric conducting material 160 that uses typography that electrocondution slurry maybe can be smeared is deposited in the opening 152 of the mask 150 on conductive layer 142.Doctor blade 162 or extrusion technique are used to electrocondution slurry 160 to deposit in opening 152.Electrocondution slurry can comprise Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, scolder and combination thereof and optional flux solvent.For example, grout material can be direct aluminum conductive electric slurry or aluminium wettability electrocondution slurry.In one embodiment, electrocondution slurry is the aluminium compound that comprises the combination of aluminium between 97% and 100% and silicon, copper, manganese and chromium, is directly bonded on aluminium contact pad 142 for improvement of ground.Electrocondution slurry 160 is applied directly on contact pad or conductive layer 142 to form electrical interconnection.Electrocondution slurry is directly printed on contact pad 142 and allows, by eliminating, the needs of under-bump metallization and projection cube structure are formed to interconnection structure with the cost and the improved manufacturing cycle time that reduce.
In Fig. 4 d, remove mask 150 from substrate 140, thereby leave electrocondution slurry 160 on the conductive layer 142 of substrate 140.In the time using the mask 150 that can re-use, promote mask 150 to leave electrocondution slurry 160 at conductive layer 142 from substrate 140 at a predetermined velocity.Electrocondution slurry 160 directly contacts with the conductive layer 142 of substrate 140.On the surface of substrate 140, form the pre-point of epoxy (epoxy pre-dot) 170 around the circumference of contact pad 142.The pre-point 140 of epoxy has predetermined altitude so that in (standoff) distance prevent interconnect failure of being separated by keeping between joint aging time between substrate 140 and semiconductor element 124.
Fig. 4 e diagram utilizes the contact pad 132 directly contacting with interconnection structure 180 to be arranged on the flip-chip semiconductor tube core 124 on substrate 140.Before engaging, can utilize plasma etching or chemical etching to carry out preliminary treatment to the contact pad 132 of semiconductor element 124 to remove any oxidation, corrosion or the impurity on contact pad 132.In one embodiment, carry out optionally etching with the aluminium oxide remover that comprises fluoride and remove any organic or oxide etch residue and control the etching of contaminated oxide surface.Sentence the process time enforcement chemical etching lower than five minutes in ambient temperature with dipping or spraycan.Aluminium oxide remover has the extremely low etch-rate of 4 dusts approximately per minute (A) to sensitive metal (such as Cu, Al, Ti and W).Etching conductive layer 132 has been eliminated stream galvano-cautery, to improve the further corrosion that engages and prevent between electrocondution slurry 160 and conductive layer 132.
Utilize the conductive layer 132 that aligns with conductive layer 142 and for the electrocondution slurry 160 between conductive layer 132 and conductive layer 142 that substrate 140 and contact pad 132 are electrically connected, semiconductor element 124 is arranged on to substrate 140.Except electrocondution slurry 160 is deposited on contact pad 142 or as the replacement to it, optional aluminium wettability electrocondution slurry can be deposited on the contact pad 132 of the semiconductor element 124 with wafer form.In one embodiment, by material is heated to its fusing point with on make electrocondution slurry reflux so that form interconnection structure 180.In some applications, interconnection structure 180 is refluxed to improve and the electrically contacting of conductive layer 132 and 142 for the second time.By making aluminium wettability slurry reflux interconnection structure 180 is formed directly on contact pad 132 and 142 between semiconductor element 124 and substrate 140.Interconnection structure 180 can also compressed joint or hot compression join conductive layer 132 and 142 to.The surface of the pre-point of epoxy 170 contact semiconductor tube cores 124 to keep standoff distance and reduce the defect in interconnection structure 180 between joint aging time.
Interconnection structure 180 is formed directly on contact pad 142 and 132 by printing aluminium wettability electrocondution slurry and it is refluxed between semiconductor element 124 and substrate 140, so that low cost interconnection solution to be provided.Interconnection structure 180 is formed directly into and on contact pad 142 and 132, has eliminated the needs to form under-bump metallization and projection on the contact pad of semiconductor element.Therefore the technique that, forms interconnection structure 180 by slurry printing provides the cost of improved manufacturing cycle time and reduction.
Fig. 5 a-5e diagram is used slurry to be printed on substrate and forms flip chip interconnects to semiconductor element is arranged on this substrate.In Fig. 5 a, substrate 200 comprises the conductive layer 202 that uses PVD, CVD, metallide, electroless plating technique or other applicable metal deposition process to form on substrate.Conductive layer 202 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, Pd, Pt or other applicable electric conducting materials.Conductive layer 202 is operating as the circuit that is electrically connected on substrate 200 or the contact pad of trace.Conductive layer 202 can be formed in the contact pad being arranged side by side apart from edge first distance of substrate 200, as shown in Fig. 5 a.Alternatively, conductive layer 202 can be formed contact pad, this contact pad is offset that in multiple row the first row contact pad is configured to apart from edges of substrate the first distance, and is configured to apart from edges of substrate second distance with the second row contact pad that the first row replaces.In one embodiment, conductive layer 202 is to be suitable for the aluminium contact pad that engages with aluminium wettability electrocondution slurry or scaling powder.Conductive pole 204 is formed on conductive layer 202 to keep the height of being separated by between joint aging time.
In Fig. 5 b, mask or template 210 are arranged on the first surface of substrate 200.Mask 210 can be the insulating barrier that uses PVD, CVD, printing, spin coating, spraying, slot coated, cylinder coating, lamination, sintering or thermal oxidation to form.Mask 210 comprises SiO 2, Si 3n 4, SiON, Ta 2o 5, Al 2o 3, hafnium oxide, benzocyclobutene, polyimides, polybenzoxazole, there is filler or fiber or do not there is the polymer dielectric resist of filler or fiber or there is similar structures and the one or more layer of the other materials of dielectric property.
Alternatively, form template or mask 210 by etching, electroforming or laser cutting cause Al, Cu, Sn, Ni, Au, Ag, Ti, W, Pd, Pt or other applicable materials, to form the continuous mask with opening 212.Mask 210 has the opening 212 forming in the precalculated position corresponding with the conductive layer 202 of substrate 200.Mask 210 is placed on substrate 200 to cover the predetermined portions of substrate 200 and expose opening 212 conductive layer 202 below.Mask 210 has the thickness that is less than 200 μ m.Mask 210 can be that disposable use maybe can re-use to be printed on respectively on single substrate or multiple substrate, and should between using, clean the mask 210 that can re-use to prevent from polluting substrate 200.
In Fig. 5 c, the electric conducting material 220 that uses slurry typography that electrocondution slurry maybe can be smeared is deposited in the opening 212 of the mask 210 on conductive layer 202.Doctor blade 222 or extrusion technique are used to electrocondution slurry 220 to deposit in opening 212.Electrocondution slurry can comprise Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, scolder and combination thereof and optional flux solvent.For example, grout material can be direct aluminum conductive electric slurry or aluminium wettability electrocondution slurry.In one embodiment, electrocondution slurry is the aluminium compound that comprises the combination of aluminium between 97% and 100% and silicon, copper, manganese and chromium, is directly bonded on aluminium contact pad 202 for improvement of ground.Electrocondution slurry 220 is applied directly on contact pad or conductive layer 202 to form electrical interconnection.Electrocondution slurry is directly printed on contact pad 202 and allows, by eliminating, the needs of under-bump metallization and projection cube structure are formed to interconnection structure with the cost and the improved manufacturing cycle time that reduce.
In Fig. 5 d, remove mask 210 from substrate 200 at a predetermined velocity, thereby leave electrocondution slurry 220 on the conductive layer 202 of substrate 200.Electrocondution slurry 220 directly contacts with the contact pad 202 of substrate 200.On the surface of substrate 200, form the pre-point 170 of epoxy around the circumference of contact pad 202.The pre-point 200 of epoxy has predetermined altitude to keeping the standoff distance between substrate 200 and semiconductor element 124 between joint aging time and preventing interconnect failure.
Fig. 5 e diagram is arranged on the flip-chip semiconductor tube core 124 on substrate 200.Before engaging, can utilize plasma etching or chemical etching to carry out preliminary treatment to the contact pad 132 of semiconductor element 124, to remove any oxidation or corrosion on contact pad 132.In one embodiment, carry out optionally etching with the aluminium oxide remover that comprises fluoride and remove any organic or oxide etch residue and control the etching of contaminated oxide surface.Sentence the process time enforcement chemical etching lower than five minutes in ambient temperature with dipping or spraycan.Aluminium oxide remover has extremely low etch-rate to sensitive metal (such as Cu, Al, Ti and W).Etching conductive layer 132 has been eliminated stream galvano-cautery to improve the further corrosion that engages and prevent between electrocondution slurry 220 and conductive layer 132.
Utilize the conductive layer 132 that aligns with conductive layer 202 and for the electrocondution slurry 220 between conductive layer 132 and conductive layer 202 that substrate 200 and contact pad 132 are electrically connected, semiconductor element 124 is arranged on to substrate 200.In one embodiment, by material is heated to its fusing point with on make electrocondution slurry reflux so that form interconnection structure 230.In some applications, interconnection structure 230 is refluxed to improve and the electrically contacting of conductive layer 132 and 202 for the second time.In one embodiment, by making aluminium wettability slurry reflux interconnection structure 230 is formed directly on contact pad 132 and 202 between semiconductor element 124 and substrate 200.Interconnection structure 230 can also compressed joint or hot compression join conductive layer 132 and 202 to.Conductive pole 204 is formed on the contact pad 202 of substrate 140 and in interconnection structure 230, to keep standoff distance and reduce the defect in interconnection structure 230 between joint aging time.
Interconnection structure 230 is formed directly on contact pad 202 and 132 by printing aluminium wettability electrocondution slurry and it is refluxed between semiconductor element 124 and substrate 200, so that low cost interconnection solution to be provided.Interconnection structure 230 is formed directly on contact pad 202 and 132 and has eliminated the needs to form under-bump metallization and projection on contact pad.Therefore the technique that, forms interconnection structure 230 by slurry printing provides the cost of improved manufacturing cycle time and reduction.
Fig. 6 a-6e diagram is used slurry to be printed on substrate and forms flip chip interconnects to semiconductor element is arranged on this substrate.In Fig. 6 a, substrate 240 comprises the conductive layer 242 that uses PVD, CVD, metallide, electroless plating technique or other applicable metal deposition process to form on substrate.Conductive layer 242 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, Pd, Pt or other applicable electric conducting materials.Conductive layer 242 is operating as the circuit that is electrically connected on substrate 240 or the contact pad of trace.Conductive layer 242 can be formed in the contact pad being arranged side by side apart from edge first distance of substrate 240, as shown in Fig. 6 a.Alternatively, conductive layer 242 can be formed contact pad, this contact pad is offset that in multiple row the first row contact pad is configured to apart from edges of substrate the first distance, and is configured to apart from edges of substrate second distance with the second row contact pad that the first row replaces.In one embodiment, conductive layer 242 is to be suitable for the aluminium contact pad that engages with aluminium wettability electrocondution slurry or scaling powder.
In Fig. 6 b, mask or template 250 are arranged on the first surface of substrate 240.Mask 250 can be the insulating barrier that uses PVD, CVD, printing, spin coating, spraying, slot coated, cylinder coating, lamination, sintering or thermal oxidation to form.Mask 250 comprises SiO 2, Si 3n 4, SiON, Ta 2o 5, Al 2o 3, hafnium oxide, benzocyclobutene, polyimides, polybenzoxazole, there is filler or fiber or do not there is the polymer dielectric resist of filler or fiber or there is similar structures and the one or more layer of the other materials of dielectric property.
Alternatively, form template or mask 250 by etching, electroforming or laser cutting cause Al, Cu, Sn, Ni, Au, Ag, Ti, W, Pd, Pt or other applicable materials, to form the continuous mask with opening 252.Mask 250 has the opening 252 forming in the precalculated position corresponding with the conductive layer 242 of substrate 240.Mask 250 is placed on substrate 240 to cover the predetermined portions of substrate 240 and expose opening 252 conductive layer 242 below.Mask 250 has the thickness that is less than 200 μ m.Mask 250 can be that disposable use maybe can re-use to be printed on respectively on single substrate or multiple substrate, and should between using, clean the mask 250 that can re-use to prevent from polluting substrate 240.
In Fig. 6 c, the electric conducting material 260 that uses slurry typography that electrocondution slurry maybe can be smeared is deposited in the opening 252 of the mask 250 on conductive layer 242.Doctor blade 262 or extrusion technique are used to electrocondution slurry 260 to deposit in opening 252.Electrocondution slurry can comprise Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, scolder and combination thereof and optional flux solvent.For example, grout material can be direct aluminum conductive electric slurry or aluminium wettability electrocondution slurry.In one embodiment, electrocondution slurry is the aluminium compound that comprises the combination of aluminium between 97% and 100% and silicon, copper, manganese and chromium, is directly bonded on aluminium contact pad 242 for improvement of ground.Electrocondution slurry 260 is applied directly on contact pad or conductive layer 242 to form electrical interconnection.Electrocondution slurry is directly printed on contact pad 242 and allows, by eliminating, the needs of under-bump metallization and projection cube structure are formed to interconnection structure with the cost and the improved manufacturing cycle time that reduce.
In Fig. 6 d, remove mask 250 from substrate 240 at a predetermined velocity, thereby leave electrocondution slurry 260 on the conductive layer 242 of substrate 240.Electrocondution slurry 260 directly contacts with the contact pad 242 of substrate 240.On contact pad 242, make electrocondution slurry 260 reflux to form scolder on pad (SOP) interconnection structure 270.Flux material 272 is applied on SOP interconnection structure 270, to improve the joint between interconnection structure 270 and semiconductor element.In one embodiment, flux material 272 is aluminium wettability flux material to improve and the engaging of aluminium contact pad.
Fig. 6 e diagram is arranged on the flip-chip semiconductor tube core 124 on substrate 240.Before engaging, can utilize plasma etching or chemical etching to carry out preliminary treatment to the contact pad 132 of semiconductor element 124, to remove any oxidation or corrosion on contact pad 132.In one embodiment, carry out optionally etching with the aluminium oxide remover that comprises fluoride and remove any organic or oxide etch residue and control the etching of contaminated oxide surface.Sentence the process time enforcement chemical etching lower than five minutes in ambient temperature with dipping or spraycan.Aluminium oxide remover has extremely low etch-rate to sensitive metal (such as Cu, Al, Ti and W).Etching conductive layer 132 has been eliminated stream galvano-cautery to improve the further corrosion that engages and prevent between electrocondution slurry 250 and conductive layer 132.
Utilize the conductive layer 132 that aligns with conductive layer 242 and for the electrocondution slurry 250 between conductive layer 132 and conductive layer 242 that substrate 240 and contact pad 132 are electrically connected, semiconductor element 124 is arranged on to substrate 240.In one embodiment, by material is heated to its fusing point with on make electrocondution slurry reflux so that form interconnection structure 280.In some applications, interconnection structure 280 is refluxed to improve and the electrically contacting of conductive layer 132 and 242 for the second time.In one embodiment, by making aluminium wettability slurry reflux interconnection structure 280 is formed directly on contact pad 132 and 242 between semiconductor element 124 and substrate 240.Projection can also compressed joint or hot compression join conductive layer 132 and 242 to.
Interconnection structure 280 is formed directly on contact pad 242 and 132 by printing aluminium wettability electrocondution slurry and it is refluxed between semiconductor element 124 and substrate 240, so that low cost interconnection solution to be provided.Interconnection structure 280 is formed directly into and on contact pad 242 and 132, has eliminated the needs to form under-bump metallization and projection on the contact pad of semiconductor element.Therefore the technique that, forms interconnection structure 280 by slurry printing provides the cost of improved manufacturing cycle time and reduction.
The similar flip-chip semiconductor device of device of Fig. 7 diagram and Fig. 6 a-6e.Substrate 290 comprises having the conductive layer 292 that uses the interconnection structure 294 that slurry printing forms with depositing electrically conductive slurry, and described electrocondution slurry is refluxed to form interconnection structure 294.Interconnection structure 294 is electrically connected to the contact pad of substrate 290 292 contact pad 132 of semiconductor element 124.On the surface of substrate 290, form the pre-point 298 of epoxy around the circumference of contact pad 292.The pre-point 298 of epoxy there is predetermined altitude so as between joint aging time, to keep substrate 290 and semiconductor element 124 between standoff distance and prevent the defect in interconnection structure 294.Conductive pole 300 is formed on the contact pad 292 of substrate 290 and in interconnection structure 294 to keep standoff distance and reduce the defect in interconnection structure 294 between joint aging time.
By printing conductive slurry between semiconductor element 124 and substrate 290 and make electrocondution slurry and aluminium wettability scaling powder refluxes and interconnection structure 294 is formed directly on contact pad 292 and 132, so that low cost interconnection solution to be provided.Interconnection structure 294 is formed directly into and on contact pad 292 and 132, has eliminated the needs to forming under-bump metallization and projection on the contact pad at semiconductor element or substrate.Therefore the technique that, forms interconnection structure 294 by slurry printing provides the cost of improved manufacturing cycle time and reduction.
Fig. 8 a-8f diagram is used slurry to be printed on and on substrate, forms the flipchip interconnect structure of Fig. 6 a-6e to semiconductor element is arranged on this substrate.In Fig. 8 a, substrate 310 comprises the conductive layer 312 that uses PVD, CVD, metallide, electroless plating technique or other applicable metal deposition process to form on substrate.Conductive layer 312 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, Pd, Pt or other applicable electric conducting materials.Conductive layer 312 is operating as the circuit that is electrically connected on substrate 310 or the contact pad of trace.Conductive layer 312 can be formed in the contact pad being arranged side by side apart from edge first distance of substrate 310, as shown in Fig. 8 a.Alternatively, conductive layer 312 can be formed contact pad, this contact pad is offset that in multiple row the first row contact pad is configured to apart from edges of substrate the first distance, and is configured to apart from edges of substrate second distance with the second row contact pad that the first row replaces.In one embodiment, conductive layer 312 is to be suitable for the aluminium contact pad that engages with aluminium wettability electrocondution slurry or scaling powder.
Use PVD, CVD, printing, spin coating, spraying, slot coated, cylinder coating, lamination, sintering or thermal oxidation that insulation or passivation layer 314 are formed on the first surface and conductive layer 312 of substrate 310.Insulating barrier 314 comprises SiO 2, Si 3n 4, SiON, Ta 2o 5, Al 2o 3, hafnium oxide, benzocyclobutene, polyimides, polybenzoxazole, there is filler or fiber or do not there is the polymer dielectric resist of filler or fiber or there is similar structures and the one or more layer of the other materials of dielectric property.
Mask or template 316 are arranged on the upper surface of substrate 310.Mask 316 can be the insulating barrier that uses PVD, CVD, printing, spin coating, spraying, slot coated, cylinder coating, lamination, sintering or thermal oxidation to form.Mask 316 comprises SiO 2, Si 3n 4, SiON, Ta 2o 5, Al 2o 3, hafnium oxide, benzocyclobutene, polyimides, polybenzoxazole, there is filler or fiber or do not there is the polymer dielectric resist of filler or fiber or there is similar structures and the one or more layer of the other materials of dielectric property.
Alternatively, form template or mask 316 by etching, electroforming or laser cutting cause Al, Cu, Sn, Ni, Au, Ag, Ti, W, Pd, Pt or other applicable materials, to form the continuous mask with opening.Mask 316 has the opening forming in the precalculated position corresponding with the conductive layer 312 of substrate 310.Mask 316 is placed on substrate 310 so that the conductive layer 312 below the predetermined portions of covering substrate 310 and exposure opening.Mask 316 has the thickness that is less than 200 μ m.Mask 316 can be that disposable use maybe can re-use to be printed on respectively on single substrate or multiple substrate, and should between using, clean the mask 316 that can re-use to prevent from polluting substrate 310.
The electric conducting material 318 that uses slurry typography that electrocondution slurry maybe can be smeared is deposited in the opening of the mask 316 on conductive layer 312.Doctor blade 262 or extrusion technique are used to electrocondution slurry 318 to deposit in opening.Electrocondution slurry can comprise Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, scolder and combination thereof and optional flux solvent.For example, grout material can be direct aluminum conductive electric slurry or aluminium wettability electrocondution slurry.In one embodiment, electrocondution slurry is the aluminium compound that comprises the combination of aluminium between 97% and 100% and silicon, copper, manganese and chromium, is directly bonded on aluminium contact pad 312 for improvement of ground.Electrocondution slurry 318 is applied directly on contact pad or conductive layer 312 to form electrical interconnection.Electrocondution slurry is directly printed on contact pad 312 and allows, by eliminating, the needs of under-bump metallization and projection cube structure are formed to interconnection structure with the cost and the improved manufacturing cycle time that reduce.
In Fig. 8 b, remove mask 316 from substrate 310 at a predetermined velocity, thereby leave electrocondution slurry 318 on the conductive layer 312 of substrate 310.Electrocondution slurry 318 directly contacts with the contact pad 312 of substrate 310.In Fig. 8 c, by material is heated to its fusing point with on electrocondution slurry 318 is refluxed to form SOP interconnection structure 320.In some applications, SOP interconnection structure 320 is refluxed for the second time to improve and the electrically contacting of conductive layer 312.In one embodiment, by aluminium wettability backflow of slurry is formed directly into SOP interconnection structure 320 on contact pad 312 by substrate 310.In Fig. 8 d, flux material is deposited on SOP interconnection structure 320 to improve the joint between interconnection structure 320 and semiconductor element.In one embodiment, flux material 322 is aluminium wettability flux material to improve and the engaging of aluminium contact pad.
Fig. 8 e diagram is arranged on the flip-chip semiconductor tube core on substrate 310.Before engaging, can utilize plasma etching or chemical etching to carry out preliminary treatment to the contact pad 324 of semiconductor element to remove any oxidation or the corrosion on contact pad 324.In one embodiment, carry out optionally etching with the aluminium oxide remover that comprises fluoride and remove any organic or oxide etch residue and control the etching of contaminated oxide surface.Sentence the process time enforcement chemical etching lower than five minutes in ambient temperature with dipping or spraycan.Aluminium oxide remover has extremely low etch-rate to sensitive metal (such as Cu, Al, Ti and W).Etching conductive layer 132 has been eliminated stream galvano-cautery to improve the further corrosion that engages and prevent between electrocondution slurry 318 and conductive layer 132.
Utilize the conductive layer 324 that aligns with conductive layer 312 and for the electrocondution slurry 318 between conductive layer 324 and conductive layer 312 that substrate 310 and contact pad 324 are electrically connected, semiconductor element is arranged on to substrate 310.By material is heated to its fusing point with on the interconnection structure 320 with flux material 322 is refluxed so that form interconnection structure 330.In some applications, interconnection structure 330 is refluxed to improve and the electrically contacting of conductive layer 324 and 312 for the second time.
By printing conductive slurry between semiconductor element and substrate 310 and make electrocondution slurry and aluminium wettability scaling powder refluxes and interconnection structure 330 is formed directly on contact pad 324 and 312, so that low cost interconnection solution to be provided.Interconnection structure 330 is formed directly into and on contact pad 324 and 312, has eliminated the needs to form under-bump metallization and projection on the contact pad of semiconductor element.Therefore the technique that, forms interconnection structure 330 by slurry printing provides the cost of improved manufacturing cycle time and reduction.
Although described one or more embodiment of the present invention in detail, those skilled in the art will recognize that, can make amendment and reorganization to these embodiment in the case of not departing from the scope of the invention as set forth in claim subsequently.

Claims (15)

1. a method of making semiconductor device, comprising:
Substrate is provided;
Mask is arranged on described substrate;
By described mask and on the contact pad of described substrate printing conductive slurry;
Semiconductor element is arranged on described electrocondution slurry; And
Described electrocondution slurry is refluxed to form interconnection structure on the contact pad of described substrate.
2. according to the process of claim 1 wherein that the contact pad of described electrocondution slurry and described substrate comprises aluminium.
3. according to the method for claim 1, also comprise:
The contact pad of described semiconductor element is arranged on described electrocondution slurry; And
Described electrocondution slurry is refluxed to form interconnection structure between the contact pad at described semiconductor element and the contact pad of described substrate.
4. according to the method for claim 3, wherein said interconnection structure is formed directly on the contact pad of described substrate and is formed directly on the contact pad of described semiconductor element.
5. according to the method for claim 3, be also included on described substrate and form the pre-point of epoxy to keep the separation between described semiconductor element and described substrate.
6. a method of making semiconductor device, comprising:
Substrate is provided;
Mask is arranged on described substrate;
Can smear electric conducting material is deposited on described substrate;
Semiconductor element is arranged on to described can smearing on electric conducting material; And
Described in making, can smear electric conducting material refluxes to form interconnection structure on described substrate.
7. according to the method for claim 6, also comprise:
At the described contact pad that described semiconductor element is set on electric conducting material of smearing; And
Described in making, can smear electric conducting material refluxes to form interconnection structure between the contact pad at described semiconductor element and the contact pad of described substrate.
8. according to the method for claim 7, wherein said interconnection structure is formed directly on the contact pad of described substrate and is formed directly on the contact pad of described semiconductor element.
9. according to the method for claim 7, be also included in and make the described electric conducting material of can smearing carry out etching to the contact pad of described semiconductor element before refluxing.
10. according to the method for claim 6, be also included on the contact pad of described substrate and form conductive pole to keep the separation between described semiconductor element and described substrate.
11. 1 kinds of semiconductor device, comprising:
Substrate;
Be deposited on the electric conducting material on the contact pad of described substrate; And
Be arranged on the semiconductor element on described electric conducting material.
12. according to the semiconductor device of claim 11, also comprises the pre-point of the epoxy being arranged between described semiconductor element and described substrate.
13. according to the semiconductor device of claim 11, also comprises the conductive pole extending in described electric conducting material.
14. according to the semiconductor device of claim 11, and wherein said electric conducting material is deposited on the contact pad of described semiconductor device.
15. according to the semiconductor device of claim 14, and the contact pad of wherein said substrate comprises aluminium.
CN201310651453.6A 2012-12-20 2013-12-06 Semiconductor device and method of making bumpless flipchip interconnect structures Pending CN103887191A (en)

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US14/039,418 US9240331B2 (en) 2012-12-20 2013-09-27 Semiconductor device and method of making bumpless flipchip interconnect structures

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