CN103850968A - Rotating speed control device for fan - Google Patents
Rotating speed control device for fan Download PDFInfo
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- CN103850968A CN103850968A CN201210514518.8A CN201210514518A CN103850968A CN 103850968 A CN103850968 A CN 103850968A CN 201210514518 A CN201210514518 A CN 201210514518A CN 103850968 A CN103850968 A CN 103850968A
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Abstract
The invention discloses a rotating speed control device for a fan. The rotating speed control device comprises a control chip, a phase detection circuit, a first counter, a second counter and a feedback comparator, wherein the control chip is used for generating a pulse signal with a corresponding duty ratio according to the current temperature of an electronic device and outputting the pulse signal to the fan; the phase detection circuit is connected with the output end of the control chip and the output end of the fan and is used for detecting phases of the pulse signal output from the output end of the control chip and the pulse signal output by the fan so as to generate and output a first phase signal and a second phase signal; the first counter and the second counter are respectively used for counting high potentials of the first phase signal and the second phase signal so as to generate a first counted value and a second counted value; the feedback comparator is used for comparing the first counted value with the second counted value and generating a comparison result output to the control chip; the control chip adjusts the rotating speed of the fan according to the comparison result, so that the rotating speed of the fan is adjusted according to a feedback value of the fan.
Description
Technical field
The present invention relates to fan rotation speed control apparatus, particularly a kind of fan rotation speed control apparatus that can adjust by the value of feedback of fan rotation speed of the fan.
Background technique
At present the common employing temperature-sensitive sticker of electronic equipment carrys out the temperature of sensing heat dissipation element, and is load heat radiation according to the rotating speed that the temperature of this sensing is controlled radiation fan.But due to the difference of model, manufacturer and the service time of fan, in the time that electronic equipment is exported identical signal to fan, the rotating speed of fan is also different, thereby the rotating speed of part fan can not reach predetermined rotating speed, make load heat radiation bad, and then may cause electronic equipment to burn.
Summary of the invention
In view of above content, be necessary to provide a kind of circuit for controlling speed of fan, can adjust by the value of feedback of fan the fan rotation speed control apparatus of rotation speed of the fan.
A kind of fan rotation speed control apparatus, for controlling the rotating speed of a fan, this fan is used to an electronic equipment heat radiation, this fan rotation speed control apparatus comprises a Temperature sampler and a control chip, this Temperature sampler is for gathering the Current Temperatures of this electronic equipment and producing a temperature signal, this control chip produces the pulse signal with corresponding dutycycle and exports this fan to by the output terminal of this control chip to drive this fan be the electronic equipment heat radiation in this temperature for the temperature signal producing according to this Temperature sampler, this fan rotation speed control apparatus also comprises: a detecting phase circuit, this detecting phase circuit comprises one first sense terminal, one second sense terminal, one first feedback end and one second feedback end, this detecting phase circuit is connected with the output terminal of this control chip by this first sense terminal, be connected with the output terminal of this fan by this second sense terminal, thereby the pulse signal of the pulse signal to the output of control chip output terminal and the output of this fan carries out detecting phase, produce one first phase signal and one second phase signal, and export this first phase signal and export this second phase signal by this second feedback end by this first feedback end, one first counter, this first counter is connected with the first feedback end of this detecting phase circuit, for the high petential of this first phase signal is counted, produces the first count value, one second counter, this second counter is connected with the second feedback end of this detecting phase circuit, for the high petential of this second phase signal is counted, produces the second count value, and a feedback comparator, this feedback comparator is connected with the output terminal of this first counter and this second counter, for relatively this first count value and this second count value, and produces a comparative result to this control chip, wherein, this control chip, according to the dutycycle of the pulse signal of this comparative result adjustment output, is adjusted the rotating speed of this fan.
The pulse signal of the pulse signal that the present invention exports a control chip output terminal by a detecting phase circuit and fan output carries out detecting phase, produces and export one first phase signal and one second phase signal; By one first counter and one second counter, respectively the high petential of this first phase signal and this second phase signal is counted, produce the first count value and the second count value; And by this feedback comparator, relatively this first count value and this second count value, and produce comparative result to this control chip, make this control chip according to the dutycycle of the pulse signal of this comparative result adjustment output, adjust the rotating speed of this fan, thereby can adjust rotation speed of the fan by the value of feedback of fan.
Accompanying drawing explanation
Fig. 1 is the block diagram of an embodiment of the present invention fan revolution speed control device.
Fig. 2 is the circuit diagram of the detecting phase circuit of fan rotation speed control apparatus as shown in Figure 1.
Fig. 3 is the simulation schematic diagram of fan rotation speed control apparatus as shown in Figure 1.
Fig. 4 is the circuit diagram of the first counter of fan rotation speed control apparatus as shown in Figure 1.
Fig. 5 is the circuit diagram of the second counter of fan rotation speed control apparatus as shown in Figure 1.
Fig. 6 is the circuit diagram of the feedback comparator of fan rotation speed control apparatus as shown in Figure 1.
Fig. 7 is the dutycycle offset schematic diagram of an embodiment of the present invention.
Primary component symbol description
| Fan rotation |
1 |
| |
2 |
| |
3 |
| |
10 |
| |
20 |
| Detecting |
30 |
| The |
301 |
| The |
302 |
| The |
303 |
| The second feedback end | 304 |
| The |
40 |
| The |
50 |
| |
60 |
| With |
31 |
| The |
32 |
| The |
33 |
| The first clock end | 41 |
| The first |
42 |
| The |
43 |
| The |
44 |
| Second clock end | 51 |
| The second Enable Pin | 52 |
| The second reset end | 53 |
| The second output terminal | 54 |
| Comparator | 61 |
| First input end | 611 |
| The second input end | 612 |
| The 3rd output terminal | 613 |
| The 4th output terminal | 614 |
| D type flip flop | 62 |
| The 3rd input end | 621 |
| Four-input terminal | 622 |
| Enable Pin | 623 |
| Clock end | 624 |
| The 5th output terminal | 625 |
| The 6th output terminal | 626 |
| |
21 |
| Analog- |
70 |
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Refer to Fig. 1-Fig. 3, a fan rotation speed control apparatus 1 is for controlling the rotating speed of a fan 2, and this fan 2 is for dispelling the heat to an electronic equipment 3.This fan rotation speed control apparatus 1 comprises a Temperature sampler 10, a control chip 20, a detecting phase circuit 30, one first counter 40, one second counter 50 and a feedback comparator 60.
This Temperature sampler 10 is for gathering the Current Temperatures of this electronic equipment 3 and producing a temperature signal.This control chip 20 is connected with this Temperature sampler 10, and pulse signal to the fan 2 that has a corresponding dutycycle for the temperature signal output producing according to this Temperature sampler 10 drives this fan 2 to dispel the heat for the electronic equipment 3 in this temperature.Wherein, the temperature difference of this electronic equipment 3, the dutycycle of the pulse signal that this control chip 20 is exported is also different, thus the rotating speed that fan 2 rotates is also different.This detecting phase circuit 30 comprises one first sense terminal 301, one second sense terminal 302, one first feedback end 303 and one second feedback end 304, this detecting phase circuit 30 is connected with the output terminal of this control chip 20 by this first sense terminal 301, be connected with the output terminal of this fan 2 by this second sense terminal 302, thus the pulse signal f that this control chip 20 is exported
dutythe pulse signal f exporting with this fan 2
tachcarry out detecting phase, produce one first phase signal Q
dwith one second phase signal Q
t, and respectively by this first feedback end 303 this first phase signal of output Q
dwith by this second feedback end 304 this second phase signal of output Q
t.This first counter 40 is connected with the first feedback end 303 of this detecting phase circuit 30, for to this first phase signal Q
dhigh petential count, produce one first count value T
d.This second counter 50 is connected with the second feedback end 304 of this detecting phase circuit 30, for to this second phase signal Q
thigh petential count, produce one second count value T
t.This feedback comparator 60 is connected with the output terminal of this first counter 40 and this second counter 50, for this first count value T relatively
dwith this second count value T
t, and produce a comparative result Y0Y1 to this control chip 20.Wherein, this control chip 20 is also adjusted the dutycycle of the pulse signal of output according to this comparative result Y0Y1, adjusts the rotating speed of this fan 2.Wherein, when control chip 20 receives relatively this first count value T of feedback comparator 60
dbe less than this second count value T
tproduce comparative result Y0Y1 time, this control chip 20 reduces the dutycycle of this pulse signal that exports fan 2 to, thereby turns down the rotating speed of this fan 2, when control chip 20 receives relatively this first count value T of feedback comparator 60
dbe greater than this second count value T
tproduce comparative result Y0Y1 time, increase this and export the dutycycle of the pulse signal of fan 2 to, thereby heighten the rotating speed of this fan 2.
Please continue to refer to Fig. 2, this detecting phase circuit 30 comprise one with door 31, one first gate 32 and one second gate 33.Should be connected with the output terminal of this control chip 20 and the output terminal of this fan 2 respectively with two input ends of door 31 (in figure not label).Wherein, the input end that should be connected with the output terminal of this control chip 20 with door 31 forms the first sense terminal 301 of this detecting phase circuit 30, and the input end that should be connected with the output terminal of this fan 2 with door 31 forms the second sense terminal 302 of this detecting phase circuit 30.This first gate 32 simultaneously with this and door 31 input ends that are connected with the output terminal of this control chip 20, and this be connected with the output terminal of door 31, for exporting this first phase signal QD.This second gate 33 simultaneously with this and door 31 input ends that are connected with the output terminal of this fan 2, and this be connected with the output terminal of door 31, for exporting this second phase signal QT.
Please continue to refer to Fig. 3, easily know the pulse signal f exporting when this control chip 20
dutythe pulse signal f exporting with this fan 2
tachwhile being all high level or low level, the first phase signal Q that this detecting phase circuit 30 is exported
dand this second phase signal Q
tbe all low level.The pulse signal f exporting when this control chip 20
dutyfor high level, and the pulse signal f that this fan 2 is exported
tachduring for low level, the first phase signal Q that this detecting phase circuit 30 is exported
dfor high level, this second phase signal Q
tfor low level.The pulse signal f exporting when this control chip 20
dutyfor low level, and the pulse signal f that this fan 2 is exported
tachduring for high level, the first phase signal Q that this detecting phase circuit 30 is exported
dfor low level, this second phase signal Q
tfor high level.
Please refer to Fig. 4, this first counter 40 comprises one first clock end 41, one first Enable Pin 42, one first reset end 43 and one first output terminal 44.This first clock end 41 is connected with a system clock, for receiving the clock signal of system clk of this system clock output.This first Enable Pin 42 is connected with the output terminal of the first gate 32 of this detecting phase circuit 30.This first reset end 43 is connected with control chip 20, a control signal fpc who produces for receiving control chip 20, and wherein, this control chip is at the pulse signal f of this control chip output
dutywhile variation from low level to high level, produce the control signal of a high level, in other cases, this control chip is exported a low level control signal.This first output terminal 44 is connected with this feedback comparator 60, for exporting current counted this first count value T
d.
Please continue to refer to Fig. 3, in the time that this control signal fpc becomes high level from low level, that is, when control signal experiences a rising edge, this first counter 40 is by this first count value T
dzero clearing.When this control signal, fpc does not change or becomes low level from high level, when this clock signal of system clk experiences a rising edge, and this first phase signal Q
dduring for high level, this first counter 40 will be counted increases by one.In other cases, the counting of this first counter 40 is constant.
Please refer to Fig. 5, this second counter 50 comprises a second clock end 51, one second Enable Pin 52, one second reset end 53 and one second output terminal 54.This second clock end 51 is connected with this system clock, for receiving the clock signal of system clk of this system clock output, this second Enable Pin 52 is connected with the output terminal of this second gate 33, this second reset end 53 is connected with this control chip 20 equally, for receiving this control signal fpc that this control chip 20 is exported, this second output terminal 54 is connected with this feedback comparator 60, for exporting current counted this second count value T
t.
Please continue to refer to Fig. 3, in the time that this control signal fpc becomes high level from low level, that is, when control signal experiences a rising edge, this second counter 50 is by this second count value T
tzero clearing.When this control signal, fpc does not change or becomes low level from high level, when this clock signal of system clk experiences a rising edge, and this second phase signal Q
tduring for high level, this second counter 50 will be counted increases by one.In other cases, the counting of this second counter 50 is constant.
Please refer to Fig. 6, in the first mode of execution of the present invention, this feedback comparator 60 comprises a comparator 61, and this comparator 61 comprises a first input end 611, one second input end 612, one the 3rd output terminal 613 and one the 4th output terminal 614.The first input end 611 of this comparator 61 is connected with the first output terminal 44 of this first counter 40, and the second input end 612 of this comparator 61 is connected with the second output terminal 54 of this second counter 50.The 3rd output terminal 613 of this comparator 61 is for exporting one first comparison value Y0, and the 4th output terminal 614 of this comparator 61 is for exporting one second comparison value Y1.This first comparison value Y0 and this second comparison value Y1 form this comparative result Y0Y1.
As this first count value T
dbe greater than this second count value T
ttime, the first comparison value Y0 that the 3rd output terminal 613 of this comparator 61 is exported is high level, the second comparison value Y1 that the 4th output terminal 614 of this comparator 61 is exported is low level.As this first count value T
dequal this second count value T
ttime, the first comparison value Y0 that the 3rd output terminal 613 of this comparator 61 is exported is low level, the second comparison value Y1 that the 4th output terminal 614 of this comparator 61 is exported is low level.As this first count value T
dbe less than this second count value T
ttime, the first comparison value Y0 that the 3rd output terminal 613 of this comparator 61 is exported is low level, the second comparison value Y1 that the 4th output terminal 614 of this comparator 61 is exported is high level.
Please continue to refer to Fig. 6, in the second mode of execution of the present invention, this feedback comparator 60 comprises a comparator 61 and a d type flip flop 62.This comparator 61 comprises a first input end 611, one second input end 612, one the 3rd output terminal 613 and one the 4th output terminal 614.The first input end 611 of this comparator 61 is connected with the first output terminal 44 of this first counter 40, and the second input end 612 of this comparator 61 is connected with the second output terminal 54 of this second counter 50.The 3rd output terminal 613 of this comparator 61 is for exporting one first comparison value, and the 4th output terminal 614 of this comparator 61 is for exporting one second comparison value.This d type flip flop 62 comprises one the 3rd input end 621, a four-input terminal 622, an Enable Pin 623, a clock end 624, one the 5th output terminal 625 and one the 6th output terminal 626.The 3rd input end 621 of this d type flip flop 62 is connected with the 3rd output terminal 613 of this comparator 61, the four-input terminal 622 of this d type flip flop 62 is connected with the 4th output terminal 614 of this comparator 61, this Enable Pin 623 is connected with this control chip 20 equally, for receiving the control signal fpc that control chip 20 is exported, this clock end 624 is connected with this system clock, for receiving the clock signal of system clk of this system clock output, the 5th output terminal 625 of this d type flip flop 62 is for exporting one the 3rd comparison value Q0, the 6th output terminal 626 of this d type flip flop 62 is for exporting one the 4th comparison value Q1, the 3rd comparison value Q0 and the 4th comparison value Q1 form this comparative result Y0Y1.By increasing this d type flip flop, make only this first count value T relatively in the time that this control signal fpc becomes high level from low level of this feedback comparator 60
dand this second count value T
t, i.e. this feedback comparator 60 last first count value T that only relatively this first counter 40 is exported before zero clearing
dand last second count value T of exporting before zero clearing of this second counter 50
t.
Please continue to refer to Fig. 3, same, as this first count value T
dbe greater than this second count value T
ttime, the first comparison value that the 3rd output terminal 613 of this comparator 61 is exported is high level, the second comparison value that the 4th output terminal 614 of this comparator 61 is exported is low level.As this first count value T
dequal this second count value T
ttime, the first comparison value that the 3rd output terminal 613 of this comparator 61 is exported is low level, the second comparison value that the 4th output terminal 614 of this comparator 61 is exported is low level.As this first count value T
dbe less than this second count value T
ttime, the first comparison value that the 3rd output terminal 613 of this comparator 61 is exported is low level, the second comparison value that the 4th output terminal 614 of this comparator 61 is exported is high level.When Enable Pin 623 is high level, when this clock signal of system is high level, the first comparison value that the 3rd comparison value Q0 that the 5th output terminal 625 of this d type flip flop 62 is exported and the 3rd output terminal 613 of this comparator 61 are exported is consistent, and the 4th comparison value Q 1 that the 6th output terminal 626 of this d type flip flop 62 is exported is consistent with the second comparison value that the 4th output terminal 614 of this comparator 61 is exported.In the time that Enable Pin 623 is low level for low level or this system clock, the 3rd comparison value Q0 of the 3rd comparison value that the 5th output terminal 625 of this d type flip flop 62 is exported and the output of last time remains unchanged, and the 4th comparison value of the 4th comparison value Q1 that the 6th output terminal 626 of this d type flip flop 62 is exported and the output of last time remains unchanged.
In this control chip 20, store a dutycycle compensation meter 21(as shown in Figure 7).Wherein, this dutycycle compensation meter 21 can be acquiescence, or can be read laggard edlin, and is again burned onto this control chip 20.In this dutycycle compensation meter 21, record the corresponding relation of comparative result and dutycycle offset.This control chip 20 is determined the corresponding dutycycle offset of this comparative result according to this dutycycle compensation meter 21, and the dutycycle of the pulse signal that this control chip 20 is exported increases this dutycycle offset to obtain a total dutycycle, and recently drive this fan 2 according to this total duty.For example: in the time that this comparative result Y1Y0 is 10, i.e. this first count value T
dbe greater than this second count value T
ttime, this control chip 20 determines that according to this dutycycle compensation meter 21 the corresponding dutycycle offset of comparative result Y1Y0 is for reducing 10, the dutycycle of the pulse signal that this control chip 20 is exported reduces 10 to obtain a total dutycycle, and recently drives this fan 2 according to this total duty.
In the present embodiment, this fan rotation speed control apparatus 1 also comprises an analog-digital converter 70, changes into digital signal for the temperature signal that this Temperature sampler 10 is gathered.
Claims (8)
1. a fan rotation speed control apparatus, for controlling the rotating speed of a fan, this fan is used to an electronic equipment heat radiation; This fan rotation speed control apparatus comprises a Temperature sampler and a control chip, this Temperature sampler is for gathering the Current Temperatures of this electronic equipment and producing a temperature signal, this control chip produces the pulse signal with corresponding dutycycle and exports this fan to by the output terminal of this control chip to drive this fan be the electronic equipment heat radiation in this temperature for the temperature signal producing according to this Temperature sampler, it is characterized in that, this fan rotation speed control apparatus also comprises:
One detecting phase circuit, this detecting phase circuit comprises one first sense terminal, one second sense terminal, one first feedback end and one second feedback end, this detecting phase circuit is connected with the output terminal of this control chip by this first sense terminal, be connected with the output terminal of this fan by this second sense terminal, thereby the pulse signal of the pulse signal to the output of control chip output terminal and the output of this fan carries out detecting phase, produce one first phase signal and one second phase signal, and export this first phase signal and export this second phase signal by this second feedback end by this first feedback end,
One first counter, this first counter is connected with the first feedback end of this detecting phase circuit, for the high petential of this first phase signal is counted, produces the first count value;
One second counter, this second counter is connected with the second feedback end of this detecting phase circuit, for the high petential of this second phase signal is counted, produces the second count value; And
One feedback comparator, this feedback comparator is connected with the output terminal of this first counter and this second counter, for relatively this first count value and this second count value, and produces a comparative result to this control chip;
Wherein, this control chip, according to the dutycycle of the pulse signal of this comparative result adjustment output, is adjusted the rotating speed of this fan.
2. fan rotation speed control apparatus as claimed in claim 1, it is characterized in that: this detecting phase circuit comprise one with door, one first gate and one second gate, should be connected with the output terminal of this control chip and the output terminal of this fan respectively with two input ends of door, wherein, the input end that should be connected with the output terminal of this control chip with door forms the first sense terminal of this detecting phase circuit, and the input end that should be connected with the output terminal of this fan with door forms the second sense terminal of this detecting phase circuit; The input end that this first gate while is connected with the output terminal of control chip with this and door, and should be connected with the output terminal of door, for exporting this first phase signal; This second gate and the input end that should be connected with the output terminal of this fan with door, and should be connected with the output terminal of door, for exporting this second phase signal.
3. fan rotation speed control apparatus as claimed in claim 2, is characterized in that: this first counter comprises one first clock end, one first Enable Pin, one first reset end and one first output terminal; This first clock end is connected with this system clock, for receiving the clock signal of system of this system clock output; This first Enable Pin is connected with the output terminal of this first gate; This first reset end is connected with this control chip, the control signal connection producing for receiving this control chip, wherein, this control chip at the pulse signal of this control chip output when low level becomes high level, produce the control signal of a high level, in other cases, this control chip is exported a low level control signal; This first output terminal is connected with this feedback comparator, for exporting this current counted first count value.
4. fan rotation speed control apparatus as claimed in claim 3, is characterized in that: this second counter comprises a second clock end, one second Enable Pin, one second reset end and one second output terminal; This second clock end is connected with this system clock, for receiving the clock signal of system of this system clock output; This second Enable Pin is connected with the output terminal of this second gate; This second reset end is connected with this control chip, this control signal producing for receiving this control chip; This second output terminal is connected with this feedback comparator, for exporting this current counted second count value.
5. fan rotation speed control apparatus as claimed in claim 4, is characterized in that: this feedback comparator comprises a comparator; This comparator comprises a first input end, one second input end, one the 3rd output terminal and one the 4th output terminal; The first input end of this comparator is connected with the first output terminal of this first counter, and the second input end of this comparator is connected with the second output terminal of this second counter; The 3rd output terminal of this comparator is used for exporting one first comparison value, and the 4th output terminal of this comparator is used for exporting one second comparison value; This first comparison value and this second comparison value form this comparative result.
6. fan rotation speed control apparatus as claimed in claim 4, is characterized in that: this feedback comparator comprises a comparator and a d type flip flop; This comparator comprises a first input end, one second input end, one the 3rd output terminal and one the 4th output terminal; The first input end of this comparator is connected with the first output terminal of this first counter, and the second input end of this comparator is connected with the second output terminal of this second counter; The 3rd output terminal of this comparator is used for exporting one first comparison value, and the 4th output terminal of this comparator is used for exporting one second comparison value; This d type flip flop comprises one the 3rd input end, a four-input terminal, an Enable Pin, a clock end, one the 5th output terminal and one the 6th output terminal; The 3rd input end of this d type flip flop is connected with the 3rd output terminal of this comparator, the four-input terminal of this d type flip flop is connected with the 4th output terminal of this comparator, this Enable Pin is connected with this control chip, for receiving this control signal of this control chip output, this clock end is connected with this system clock, for receiving the clock signal of system of this system clock output; The 5th output terminal of this d type flip flop is used for exporting one the 3rd comparison value, and the 6th output terminal of this d type flip flop is used for exporting one the 4th comparison value, and the 3rd comparison value and the 4th comparison value form this comparative result.
7. as claim 5 or fan rotation speed control apparatus claimed in claim 6, it is characterized in that: in this control chip, store a dutycycle compensation meter, in this dutycycle compensation meter, record the corresponding relation of comparative result and dutycycle offset, this control chip is determined the corresponding dutycycle offset of this comparative result according to this dutycycle compensation meter, the dutycycle of this pulse signal is increased to this dutycycle offset to obtain a total dutycycle, and recently drive this fan according to this total duty.
8. fan rotation speed control apparatus as claimed in claim 1, is characterized in that: this fan rotation speed control apparatus also comprises an analog-digital converter, changes into digital signal for the temperature signal that this Temperature sampler is gathered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210514518.8A CN103850968B (en) | 2012-12-05 | 2012-12-05 | Fan rotation speed control apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210514518.8A CN103850968B (en) | 2012-12-05 | 2012-12-05 | Fan rotation speed control apparatus |
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| Publication Number | Publication Date |
|---|---|
| CN103850968A true CN103850968A (en) | 2014-06-11 |
| CN103850968B CN103850968B (en) | 2016-05-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210514518.8A Expired - Fee Related CN103850968B (en) | 2012-12-05 | 2012-12-05 | Fan rotation speed control apparatus |
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2012
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|---|---|---|---|---|
| DE2619602A1 (en) * | 1976-05-04 | 1977-11-17 | Creativ Patentanstalt | Airflow control for bubbling water massager - uses phase cutting circuit to air volume instead of pressure |
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| Publication number | Publication date |
|---|---|
| CN103850968B (en) | 2016-05-25 |
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