CN103779263B - A kind of manufacture method of the semiconductor device based on self-aligned double patterning case - Google Patents
A kind of manufacture method of the semiconductor device based on self-aligned double patterning case Download PDFInfo
- Publication number
- CN103779263B CN103779263B CN201210399303.6A CN201210399303A CN103779263B CN 103779263 B CN103779263 B CN 103779263B CN 201210399303 A CN201210399303 A CN 201210399303A CN 103779263 B CN103779263 B CN 103779263B
- Authority
- CN
- China
- Prior art keywords
- material layer
- dielectric layer
- groove
- wire
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a kind of manufacture method of the semiconductor device based on self-aligned double patterning case, including：One back end of line device is provided, at least includes Semiconductor substrate and the dielectric layer being located in described Semiconductor substrate；Pattern described dielectric layer, to remove partly described dielectric layer form groove；Deposition APF material layer simultaneously planarizes, to fill described groove；Etch described APF material layer, to form groove and to be located at the strip core-wire between groove；Deposited sidewalls material layer on substrate, then etches described side-wall material layer, to form spaced walls on the side wall of described strip core-wire；Etching removes described strip core-wire, and the step that no longer individually actuating station is cut, to form parallel strip pattern.The method of the invention makes the back end of line in semiconductor device（BEOL）In no longer actuating station cut step and can obtain target pattern, make process is simple, easily-controllable.
Description
Technical field
A kind of the present invention relates to field of semiconductor manufacture, in particular it relates to partly leading based on self-aligned double patterning case
The manufacture method of body device.
Background technology
For the increasingly increase of the semiconductor storage demand of high power capacity, the integration density of these semiconductor storages
Paid close attention to by people, in order to increase the integration density of semiconductor storage, in prior art, employed many different sides
Method, such as by reducing wafer size and/or changing inner structure unit and multiple memory element are formed on single wafer, for
Increase the method for integration density by changing cellular construction for, carry out attempting the horizontal layout that ditch passes through change active area
Or change cell layout reducing cellar area.
Nand flash memory is a kind of more more preferable storage scheme than hard disk drive, because nand flash memory reads and writes number in units of page
According to, so being suitable for storing continuous data, such as picture, audio frequency or alternative document data；Simultaneously because its low cost, capacity are big and
The advantage that writing speed is fast, the erasing time is short obtains extensively in the field of storage of device for mobile communication and portable multimedia device
Application.At present, in order to improve the capacity of nand flash memory, need to improve the integration density of nand flash memory in preparation process.
During preparing nand flash memory, spacer patterns technology (Spacer patterning technology,
) and self-aligned double patterning case technology (self aligned double patterning, SaDPT) all can be used to prepare SPT
The transistor of nanoscale, is usually used known patterning and etch process during the chip processing quasiconductor using methods described
Form the feature of semiconductor device in the wafer, in these photoetching processes, Other substrate materials are deposited on chip, then expose
In the light filtering through reticule, after reticule, the surface of this this Other substrate materials of light contacts, this light changes
Become the chemical composition of this Other substrate materials thus developing machine can remove a part for this Other substrate materials, the figure required for obtaining
Case.
At present in semiconductor back-end processing procedure (The back end of line, BEOL), generally select self-aligned double patterning
The method of case technology (self aligned double patterning, SaDPT) forms clearance wall, and the clearance wall being formed is such as
Shown in Fig. 9, described core-wire (core line) is surrounded by described clearance wall 11 completely, needs in institute after forming described clearance wall
State and other one layer of mask is formed on substrate, then carry out end and cut (line end cut), to expose described core-wire (core
Line), need in this process to form extra mask layer, make mask stack more complicated, and carry out end cut, pattern transfer
During wayward so that whole technical process is more difficult.
Therefore, in prior art from self-aligned double patterning case technology formed clearance wall all inevitably one end to be executed cut
Step is so that whole preparation process is more loaded down with trivial details, and wayward, and the production efficiency of product and yield are all affected,
Need current technology is improved.
Content of the invention
Introduce a series of concept of reduced forms in Summary, this will specific embodiment partly in enter
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme required for protection
Key feature and essential features, more do not mean that the protection domain attempting to determine technical scheme required for protection.
Cut step in order to need in the back end of line (BEOL) of semiconductor device in the prior art described in solving to execute one end
Suddenly, make whole manufacturing process complicated, wayward, cause the not high problem of semiconductor device yield, the invention provides one
Plant the manufacture method of the semiconductor device based on self-aligned double patterning case, methods described includes：
One back end of line device is provided, at least includes Semiconductor substrate and the dielectric being located in described Semiconductor substrate
Layer；
Pattern described dielectric layer, to remove partly described dielectric layer form groove；
Deposition APF material layer simultaneously planarizes, to fill described groove；
Etch described APF material layer, to form groove and to be located at the strip core-wire between groove；
Deposited sidewalls material layer on substrate, then etches described side-wall material layer, with the side in described strip core-wire
Spaced walls are formed on wall；
Etching removes described strip core-wire, and the step that no longer individually actuating station is cut, to form parallel strip pattern.
Preferably, methods described is further comprising the steps of：
Fill the groove between strip pattern from conductive material and planarized.
Preferably, methods described is further comprising the steps of：
Dielectric layer described in described parallel strip pattern as mask etch, described strip pattern is transferred to and is given an account of
In electric layer.
Preferably, described side-wall material layer is the oxide of silicon, the nitride of silicon, the nitrogen oxides of silicon.
Preferably, described side-wall material layer is SiC, SiCN or SiO2.
Preferably, the method depositing described side-wall material layer is atomic layer deposition method.
Preferably, the method etching described side-wall material layer is dry etching.
Preferably, etch selecting C-F etchant during described side-wall material layer.
Preferably, described C-F etchant is CF4、CHF3、C4F8And C5F8One or more of.
Preferably, etching removes selects O base etchant during described strip core-wire.
Preferably, the step forming described groove includes forming the photoresist mask of patterning on described dielectric layer
Layer, then patterns described dielectric layer again.
Preferably, the photoresist mask layer of patterning is formed on described APF material layer, then etch described APF again
Material layer, to form strip core-wire.
Preferably, described dielectric layer is non-ultra low-K material layer.
Adopt spacer patterns technology and self-aligned double patterning case technology in the present invention, and existing method is changed
Enter so that no longer actuating station is cut step and can be obtained target pattern in the back end of line (BEOL) of semiconductor device, realize good
Good connection, solves and has to carry out the step that end is cut in prior art, make whole manufacturing process complicated, wayward, cause
The not high problem of semiconductor device yield.
Brief description
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Shown in the drawings of this
Bright embodiment and its description, for explaining assembly of the invention and principle.In the accompanying drawings,
The schematic diagram based on self-aligned double patterning case semiconductor device making method for Fig. 1-8 present invention；
Fig. 9 is the schematic diagram manufacturing semiconductor device in prior art；
Figure 10 is the process chart based on self-aligned double patterning case method for the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can one or more of these details and be able to
Implement.In other examples, in order to avoid obscuring with the present invention, some technical characteristics well known in the art are not entered
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, so that base of the present invention to be described
Manufacture method in the semiconductor device of self-aligned double patterning case.Obviously, the execution of the present invention is not limited to the skill of semiconductor applications
The specific details that art personnel are familiar with.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these describe in detail,
The present invention can also have other embodiment.
Should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
Exemplary embodiment according to the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
It is intended to include plural form.Additionally, it should be understood that, when in this manual using term "comprising" and/or " inclusion "
When, it indicates there is described feature, entirety, step, operation, element and/or assembly, but does not preclude the presence or addition of one or many
Other features individual, entirety, step, operation, element, assembly and/or combinations thereof.
Now, it is more fully described the exemplary embodiment according to the present invention with reference to the accompanying drawings.However, these exemplary realities
Apply example to implement with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.Should
Be understood by, these embodiments are provided so that disclosure of the invention is thoroughly and complete, and by these exemplary enforcements
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region
Degree, and make to be presented with like reference characters identical element, thus description of them will be omitted.
Understand for convenience, the invention provides a kind of process chart of specific embodiment, as shown in figure 9, simultaneously
The process schematic of the manufacture method of the present invention being given in conjunction with Fig. 1-8 is further explained.
As shown in figure 1, providing the device of back end of line first, described device includes at least with Semiconductor substrate (not shown)
And the dielectric layer 101 being located in described Semiconductor substrate, specifically：
Described Semiconductor substrate can be at least one in the following material being previously mentioned：Silicon, silicon-on-insulator (SOI),
Stacking silicon (SSOI) on insulator, stacking SiGe (S-SiGeOI) on insulator, germanium on insulator SiClx (SiGeOI) and
Germanium on insulator (GeOI) etc..
Preferably, isolation structure can also be formed in described Semiconductor substrate, described isolation structure be shallow trench every
From (STI) structure or selective oxidation silicon (LOCOS) isolation structure.It is preferably formed as shallow trench in the present invention to isolate, described half
It is also formed with the channel layer of various traps (well) structure and substrate surface in conductor substrate.In general, form trap (well) knot
The ion doping conduction type of structure is identical with channel layer ion doping conduction type, but concentration is low compared with gate channel layer, ion
The depth of injection is general to enclose relatively extensively, needs to reach the depth more than isolation structure simultaneously.
Additionally, active area can be defined on Semiconductor substrate.Can also include other active on the active region
Device, for convenience, does not indicate in shown figure.
Preferably, described grid structure can be formed further on described substrate, can also be further contained in grid
The step that both sides form source-drain area, specifically, can form described source-drain area by the method for ion implanting or diffusion, make
For step that is further preferred, can further include a thermal annealing after carrying out ion implanting or diffusion.Described grid
The forming process of pole can select method commonly used in the art, will not be described here.
With continued reference to Fig. 1, comprise upper and lower two parts in FIG, wherein part above is the top view of described device,
Described below portion is corresponding profile, and part is one-to-one relationship as shown by arrows in FIG..
After forming dielectric layer, the mask layer of the photoresist of patterning as described in Figure 1 is formed on described dielectric layer
102, wherein, described dielectric layer 101 selects the dielectric material beyond ultralow dielectric dielectric material.Described dielectric layer can be oxygen
SiClx layer, manufactures work including using thermal chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma (HDP)
The material layer having doped or undoped silicon oxide that skill is formed, described dielectric layer can be with use example in an embodiment of the present invention
As SiO2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc..Or, it is possible to use in carbon
Film of SiCN thin film etc. is defined on fluorine compounds (CF).Fluorocarbon is with fluorine (F) and carbon (C) as main component.Carbon is fluorinated
Compound can also use has the material that noncrystal (amorphism) constructs.Interlayer dielectric layer can also be using the oxidation of such as carbon dope
The Porous such as silicon (SiOC) construct.
With reference to Fig. 2, with described photoresist mask layer as mask, pattern described dielectric layer, to remove partly described dielectric
Layer, forms groove, and specifically, described engraving method is dry etching or wet etching, selects and described Semiconductor substrate tool
There are the engraving method of larger etching selectivity and etchant it is not limited to a certain kind.
Then deposition APF material layer 103 (Advanced pattern film, APF), to fill described groove, the present invention
From APF material, with respect to traditional ArF, SiON, for TEOS, Poly mask, neutral in semiconductor device preparation process
Can be more superior, CDU becomes controlled and stable, and described APF material layer is preferably amorphous carbon material in the present invention, described
The deposition of APF material layer can be from chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD) method or ald
(ALD) low-pressure chemical vapor deposition (LPCVD) of the formation such as method, laser ablation deposition (LAD) and selective epitaxy growth (SEG)
One of.Preferred ald (ALD) method in the present invention.Preferably, executing chemistry after deposition APF material layer 103
Mechanical planarization step, to obtain more flat surface.
With reference to Fig. 3, the second photoresist mask layer 104 of patterning, described second photoetching are formed on described APF material layer
CD and the number of groove to be formed are defined on glue mask layer, then with described second photoresist mask layer as mask etch
Described APF material layer, forms the core-wire 13 (core line) between groove and groove, as shown in figure 4, then etching is gone
Except described photoresist mask layer.
Specifically, select APF material layer described in O base etchant etching in this step, in one embodiment of this invention
From O2Atmosphere, other a small amount of gas such as CF can also be simultaneously introduced4、CO2、N2, described etching pressure can be 50-
200mTorr, preferably 100-150mTorr, power is 200-600W, and described etching period is 5-80s in the present invention, more excellent
Select 10-60s, select larger gas flow in the present invention simultaneously, preferably, in O of the present invention2Flow be 30-
300sccm, more preferably 50-100sccm.
With reference to Fig. 5, deposited sidewalls material layer 105 on substrate, to cover described dielectric layer and described core-wire 13
(core line), wherein said side-wall material layer is silicide, and specifically, described silicide can be the oxide of silicon, silicon
Nitride, the nitrogen oxides of silicon, preferably SiC, SiCN or SiO2, the deposition of described side-wall material layer can be from chemical gas
The mutually low-pressure chemical vapor deposition of the formation such as deposition (CVD) method, physical vapour deposition (PVD) (PVD) method or ald (ALD) method
(LPCVD), one of laser ablation deposition (LAD) and selective epitaxy growth (SEG).Preferred atomic layer deposition in the present invention
Long-pending (ALD) method.
With reference to Fig. 6, etch described side-wall material layer, so that spaced walls to be formed on the side wall of described strip core-wire；Specifically
Ground, to etch described side-wall material layer from dry etching, and preferably C-F etchant is etching described side-wall material in the present invention
Layer, described C-F etchant is CF4、CHF3、C4F8And C5F8One or more of.In a specific embodiment of the present invention,
Described dry etching can select CF4、CHF3, in addition add N2、CO2One of as etching atmosphere, wherein gas flow is
CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, described etching pressure is 30-150mTorr,
Etching period is 5-120s, preferably 5-60s, more preferably 5-30s.
With reference to Fig. 7, etching removes described strip core-wire, and the step that no longer individually actuating station is cut, to form parallel bar
Shape pattern, specifically, etching removes described strip core-wire, to form the strip pattern with certain intervals, in the present invention
The minimizing technology of described strip core-wire can select method commonly used in the art.
With reference to Fig. 8, fill the groove between described strip core-wire from conductive material, and planarize, smooth to obtain
Surface, realize and described parallel strip pattern between connection.The preferred metallic copper of described conductive material in the present invention, but
It is not limited to this metal material.
Additionally, in the present invention in addition to fill the groove between described strip core-wire from conductive material, acceptable
Dielectric layer described in described parallel strip pattern as mask etch, described strip pattern is transferred in described dielectric layer.
Can have multiple operating procedures after forming parallel strip pattern it is not limited to two kinds provided by the present invention.
With reference to Figure 10, illustrated therein is the manufacture method of the semiconductor device based on self-aligned double patterning case for the present invention, specifically
Comprise the following steps：
Step 201 provides a back end of line device, at least includes Semiconductor substrate and is located in described Semiconductor substrate
Dielectric layer；
Step 202 patterns described dielectric layer, to remove partly described dielectric layer form groove；
Step 203 deposition APF material layer simultaneously planarizes, to fill described groove；
Step 204 etches described APF material layer, to form groove and to be located at the strip core-wire between groove；
Step 205 deposited sidewalls material layer on substrate, then etches described side-wall material layer, with described strip core
Spaced walls are formed on the side wall of line；
Step 206 etching removes described strip core-wire, and the step that no longer individually actuating station is cut, to form parallel strip
Pattern；
Step 207 is filled the groove between strip pattern from conductive material and is planarized, or with described parallel
Strip pattern is dielectric layer described in mask etch, and described strip pattern is transferred in described dielectric layer.
Adopt spacer patterns technology and self-aligned double patterning case technology in the present invention, and methods described is changed
Enter so that no longer actuating station is cut step and can be obtained target pattern in the back end of line (BEOL) of semiconductor device, simultaneously real
Now good connection, solves and makes whole manufacturing process complicated, wayward in prior art, cause semiconductor device yield
Not high problem.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and descriptive purpose, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member, it is understood that the invention is not limited in above-described embodiment, can also make more kinds of according to the teachings of the present invention
Variants and modifications, within these variants and modifications all fall within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
1. a kind of manufacture method of the semiconductor device based on self-aligned double patterning case, including：
One back end of line device is provided, at least includes Semiconductor substrate and the dielectric layer being located in described Semiconductor substrate；
Pattern described dielectric layer, to remove partly described dielectric layer form groove；
Deposition APF material layer simultaneously planarizes, to fill described groove；
Etch described APF material layer, to form groove and to be located at the strip core-wire between groove；
Deposited sidewalls material layer on substrate, then etches described side-wall material layer, with the side wall of described strip core-wire
Form spaced walls；
Etching removes described strip core-wire, to form parallel strip pattern；
Fill the groove between described parallel strip pattern from conductive material and planarized, no longer actuating station cuts step
Obtain target pattern.
2. method according to claim 1 is it is characterised in that methods described is further comprising the steps of：
Dielectric layer described in described parallel strip pattern as mask etch, described strip pattern is transferred to described dielectric layer
In.
3. method according to claim 1 is it is characterised in that described side-wall material layer is the oxide of silicon, the nitridation of silicon
Thing or the nitrogen oxides of silicon.
4. method according to claim 1 is it is characterised in that described side-wall material layer is SiC, SiCN or SiO2.
5. method according to claim 1 is it is characterised in that the method depositing described side-wall material layer is ald
Method.
6. method according to claim 1 is it is characterised in that the method etching described side-wall material layer is dry etching.
7. method according to claim 1 selects C-F etchant it is characterised in that etching during described side-wall material layer.
8. method according to claim 7 is it is characterised in that described C-F etchant is CF4、CHF3、C4F8And C5F8In
One or more.
9. method according to claim 1 is it is characterised in that etching removes during described strip core-wire from the etching of O base
Agent.
10. method according to claim 1 is it is characterised in that the step forming described groove is included in described dielectric layer
The upper photoresist mask layer forming patterning, then patterns described dielectric layer again.
11. methods according to claim 1 are it is characterised in that form the photoresist of patterning in described APF material layer
Mask layer, then etches described APF material layer, again to form strip core-wire.
12. methods according to claim 1 are it is characterised in that described dielectric layer is non-ultra low-K material layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210399303.6A CN103779263B (en) | 2012-10-18 | 2012-10-18 | A kind of manufacture method of the semiconductor device based on self-aligned double patterning case |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210399303.6A CN103779263B (en) | 2012-10-18 | 2012-10-18 | A kind of manufacture method of the semiconductor device based on self-aligned double patterning case |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103779263A CN103779263A (en) | 2014-05-07 |
| CN103779263B true CN103779263B (en) | 2017-03-08 |
Family
ID=50571368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210399303.6A Active CN103779263B (en) | 2012-10-18 | 2012-10-18 | A kind of manufacture method of the semiconductor device based on self-aligned double patterning case |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103779263B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9779944B1 (en) | 2016-09-13 | 2017-10-03 | International Business Machines Corporation | Method and structure for cut material selection |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6638441B2 (en) * | 2002-01-07 | 2003-10-28 | Macronix International Co., Ltd. | Method for pitch reduction |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8123968B2 (en) * | 2005-08-25 | 2012-02-28 | Round Rock Research, Llc | Multiple deposition for integration of spacers in pitch multiplication process |
| JP4976977B2 (en) * | 2007-10-17 | 2012-07-18 | 株式会社東芝 | Manufacturing method of semiconductor device |
| US7786015B2 (en) * | 2008-04-28 | 2010-08-31 | Sandisk 3D Llc | Method for fabricating self-aligned complementary pillar structures and wiring |
| US8026172B2 (en) * | 2009-06-29 | 2011-09-27 | Sandisk 3D Llc | Method of forming contact hole arrays using a hybrid spacer technique |
-
2012
- 2012-10-18 CN CN201210399303.6A patent/CN103779263B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6638441B2 (en) * | 2002-01-07 | 2003-10-28 | Macronix International Co., Ltd. | Method for pitch reduction |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103779263A (en) | 2014-05-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9385046B2 (en) | Voids in STI regions for forming bulk FinFETs | |
| CN101878521B (en) | Methods of etching trenches into silicon of a semiconductor subtrate, methods of forming trench isolation in silicon of a semiconductor substrate, and methods of forming a plurality of diodes | |
| CN105304715B (en) | FinFET and manufacture method thereof | |
| CN104347423B (en) | The formation of integrated knot and contact is to form transistor | |
| CN103545188B (en) | Method, semi-conductor device manufacturing method | |
| US20210265196A1 (en) | Semiconductor Device and Method | |
| CN103296069A (en) | FinFET and method of fabricating the same | |
| JP2011129872A (en) | Semiconductor device | |
| CN103035712B (en) | Semiconductor device and manufacture method thereof | |
| TW201427021A (en) | Semiconductor devices and methods of manufacture thereof | |
| CN103531475A (en) | Semiconductor device and manufacturing method therefor | |
| CN105428238A (en) | FinFET device, manufacturing method thereof, and electronic device | |
| CN208819879U (en) | Integrated circuit memory | |
| CN105244379A (en) | Semiconductor device and manufacturing method thereof | |
| US6699746B2 (en) | Method for manufacturing semiconductor device | |
| CN103839820A (en) | Method for manufacturing semiconductor device | |
| CN103681291B (en) | A kind of forming method of metal silicide | |
| CN104916639A (en) | Semi-floating gate memory structure and manufacturing method thereof | |
| CN103779263B (en) | A kind of manufacture method of the semiconductor device based on self-aligned double patterning case | |
| CN103681275B (en) | A kind of semiconductor device with highly controllable fin and preparation method | |
| US20220059411A1 (en) | Method for fabricating semiconductor device with porous dielectric structure | |
| CN106531741B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN104752175A (en) | Method for manufacturing semiconductor device | |
| CN105470296A (en) | Semiconductor device and manufacturing method thereof and electronic device | |
| CN104851834A (en) | Semiconductor device preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |