CN103779263A - Semiconductor device manufacturing method based on self-aligned double patterning - Google Patents
Semiconductor device manufacturing method based on self-aligned double patterning Download PDFInfo
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- CN103779263A CN103779263A CN201210399303.6A CN201210399303A CN103779263A CN 103779263 A CN103779263 A CN 103779263A CN 201210399303 A CN201210399303 A CN 201210399303A CN 103779263 A CN103779263 A CN 103779263A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a semiconductor device manufacturing method based on self-aligned double patterning. The method comprises the following steps: a back-end-of-line device is provided, and a semiconductor substrate and a dielectric layer located on the semiconductor substrate are at least comprised; the dielectric layer is patterned to remove a part of the dielectric layer and form grooves; an APF material layer is deposited and planarized to fill the grooves; the APF material layer is etched to form grooves and strip-like core lines located between the grooves; a sidewall material layer is deposited on the substrate, and then the sidewall material layer is etched to form spacing walls on sidewalls of the strip-like core lines; and the strip-like core lines are removed through etching to form a parallel strip-like pattern without performing the end cutting step separately. According to the method of the invention, a target pattern can be obtained in the back-end-of-line (BEOL) of the semiconductor device without performing the end cutting step, so the process is simple and easy to control.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly, the present invention relates to a kind of manufacture method of the semiconductor device based on self-aligned double patterning case.
Background technology
For the increase day by day of the semiconductor storage demand of high power capacity, the integration density of these semiconductor storages receives people's concern, in order to increase the integration density of semiconductor storage, available technology adopting many diverse ways, for example on single wafer, form multiple memory cell by reducing wafer size and/or change inner structure unit, for the method that increases integration density by changing cellular construction, attempt ditch and reduced cellar area by changing the floor plan of active area or changing cell layout.
Nand flash memory is a kind of than the better storage scheme of hard disk drive, because nand flash memory reads and writes data take page as unit, thus be suitable for storing continuous data, as picture, audio frequency or alternative document data; Simultaneously because the advantage that its cost is low, capacity is large and writing speed is fast, the erasing time is short is widely used in the field of storage of device for mobile communication and portable multimedia device.At present, in order to improve the capacity of nand flash memory, need in preparation process, improve the integration density of nand flash memory.
Preparing in nand flash memory process, spacer patterns technology (Spacer patterning technology, and self-aligned double patterning case technology (self aligned double patterning SPT), SaDPT) all can be used for preparing the transistor of nanoscale, while adopting described method to process semi-conductive wafer, conventionally use known patterning and etch process in wafer, to form the feature of semiconductor device, in these photoetching processes, photoresist deposition of material is on wafer, then be exposed to the light filtering through reticule, after reticule, this light contacts the surface of this photoresist material, thereby changing the chemical composition developing machine of this photoresist material, this light can remove the part of this photoresist material, obtain needed pattern.
At present at semiconductor back-end processing procedure (The back end of line, BEOL) in, conventionally select self-aligned double patterning case technology (selfaligned double patterning, SaDPT) method forms clearance wall, the clearance wall forming as shown in Figure 9, described clearance wall 11 surrounds described core-wire (core line) completely, after forming described clearance wall, need on described substrate, form other one deck mask, then carry out end-grain cutting (line end cut), to expose described core-wire (core line), in this process, need to form extra mask layer, make mask lamination more complicated, and carry out end-grain cutting, wayward in the process of design transfer, make whole technical process more difficult.
Therefore, in prior art, select self-aligned double patterning case technology to form clearance wall and all inevitably will carry out an end-grain cutting step, make whole preparation process more loaded down with trivial details, and wayward, production efficiency and the yield of product are all affected, and need to improve current technology.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to need to carry out an end-grain cutting step in the rear end processing procedure (BEOL) of semiconductor device in the prior art described in solving, make whole manufacturing process complexity, wayward, cause the problem that semiconductor device yield is not high, the invention provides a kind of manufacture method of the semiconductor device based on self-aligned double patterning case, described method comprises:
One rear end processing procedure device is provided, at least comprises Semiconductor substrate and be positioned at the dielectric layer in described Semiconductor substrate;
Dielectric layer described in patterning, to remove the described dielectric layer of part and to form groove;
Deposition APF material layer planarization, to fill described groove;
APF material layer described in etching, to form groove and the strip core-wire between groove;
Deposited sidewalls material layer on substrate, then side-wall material layer described in etching, to form spaced walls on the sidewall at described strip core-wire;
Described strip core-wire is removed in etching, carries out no longer separately the step of end-grain cutting, to form parallel strip pattern.
As preferably, described method is further comprising the steps of:
Select electric conducting material fill the groove between strip pattern and carry out planarization.
As preferably, described method is further comprising the steps of:
Take described parallel strip pattern as dielectric layer described in mask etch, so that described strip pattern is transferred in described dielectric layer.
As preferably, the oxide that described side-wall material layer is silicon, the nitride of silicon, the nitrogen oxide of silicon.
As preferably, described side-wall material layer is SiC, SiCN or SiO
2.
As preferably, the method that deposits described side-wall material layer is atomic layer deposition method.
As preferably, the method for side-wall material layer is dry etching described in etching.
As preferably, select C-F etchant described in etching when side-wall material layer.
As preferably, described C-F etchant is CF
4, CHF
3, C
4f
8and C
5f
8in one or more.
As preferably, when removing described strip core-wire, etching selects O base etchant.
As preferably, the step that forms described groove is included in the photoresist mask layer that forms patterning on described dielectric layer, and then dielectric layer described in patterning.
As preferably, on described APF material layer, form the photoresist mask layer of patterning, and then APF material layer described in etching, to form strip core-wire.
As preferably, described dielectric layer is non-ultralow K material layer.
Adopt in the present invention spacer patterns technology and self-aligned double patterning case technology, and existing method is improved, make no longer to carry out end-grain cutting step in the rear end of semiconductor device processing procedure (BEOL) and can obtain target pattern, realize good connection, solve the step that must carry out end-grain cutting in prior art, make whole manufacturing process complexity, wayward, cause the problem that semiconductor device yield is not high.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1-8 the present invention is based on the schematic diagram of self-aligned double patterning case semiconductor device making method;
Fig. 9 is the schematic diagram of manufacturing semiconductor device in prior art;
Figure 10 is the process chart that the present invention is based on self-aligned double patterning case method.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, by propose detailed description in following description, so that the manufacture method of the semiconductor device based on self-aligned double patterning case of the present invention to be described.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give attention, the term that used is here only in order to describe specific embodiment, but not intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative is also intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, entirety, step, operation, element and/or assembly, exists or additional one or more other features, entirety, step, operation, element, assembly and/or their combination but do not get rid of.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skills.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and region, and used the identical Reference numeral to represent identical element, thereby will omit description of them.
Understand for convenient, the invention provides a kind of process chart of embodiment, as shown in Figure 9, the process schematic diagram of the manufacture method of the present invention providing in conjunction with Fig. 1-8 is further explained simultaneously.
As shown in Figure 1, first provide the device of rear end processing procedure, described device at least comprises with Semiconductor substrate (not shown) and is positioned at the dielectric layer 101 in described Semiconductor substrate, particularly:
Described Semiconductor substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
As preferably, can also in described Semiconductor substrate, form isolation structure, described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Be preferably formed in the present invention shallow trench isolation from, in described Semiconductor substrate, be also formed with the channel layer of various traps (well) structure and substrate surface.In general, the ion doping conduction type that forms trap (well) structure is identical with channel layer ion doping conduction type, but concentration is low compared with gate channel layer, and the degree of depth of Implantation is general encloses extensivelyr, needs to reach the degree of depth that is greater than isolation structure simultaneously.
In addition, in Semiconductor substrate, can be defined active area.On this active area, can also include other active device, for convenient, shown in do not indicate in figure.
As preferably, on described substrate, can further form described grid structure, can also further be included in the step that grid both sides form source-drain area, particularly, can form described source-drain area by the method for Implantation or diffusion, as further preferably, in the step of carrying out can further include after Implantation or diffusion a thermal annealing.The forming process of described grid can be selected this area common method, does not repeat them here.
Continue with reference to Fig. 1, in Fig. 1, comprise upper and lower two parts, the vertical view that wherein part is above described device, described part is below corresponding profile, part is one-to-one relationship as shown by arrows in FIG..
After forming dielectric layer, on described dielectric layer, form the mask layer 102 of the photoresist of patterning as described in Figure 1, wherein, described dielectric layer 101 is selected the dielectric material beyond ultralow dielectric dielectric material.Described dielectric layer can be silicon oxide layer, comprise the material layer that has doping or unadulterated silica that utilizes thermal chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma (HDP) manufacturing process to form, described dielectric layer can use for example SiO in an embodiment of the present invention
2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc.Or, also can use film having formed SiCN film etc. on fluorocarbon (CF).Fluorocarbon is take fluorine (F) and carbon (C) as main component.Fluorocarbon also can use the material with noncrystal (amorphism) structure.Interlayer dielectric layer can also use the Porous structures such as such as carbon doped silicon oxide (SiOC).
With reference to Fig. 2, take described photoresist mask layer as mask, dielectric layer described in patterning, to remove the described dielectric layer of part, form groove, particularly, described engraving method is dry etching or wet etching, select engraving method and the etchant with described Semiconductor substrate with larger etching selectivity, be not limited to a certain.
Then deposit APF material layer 103(Advanced pattern film, APF), to fill described groove, the APF material that the present invention selects, with respect to traditional ArF, SiON, TEOS, Poly mask, more superior at semiconductor device preparation process performance, it is controlled and stable that CDU becomes, described APF material layer is preferably amorphous carbon material in the present invention, the deposition of described APF material layer can be selected chemical vapor deposition (CVD) method, the low-pressure chemical vapor deposition (LPCVD) that physical vapor deposition (PVD) method or ald (ALD) method etc. form, one in laser ablation deposition (LAD) and selective epitaxy growth (SEG).Preferred ald (ALD) method in the present invention.As preferably, deposit APF material layer 103 rear execution chemical-mechanical planarization steps, to obtain flat surface more.
With reference to Fig. 3, on described APF material layer, form the second photoresist mask layer 104 of patterning, CD and the number that will form groove on described the second photoresist mask layer, are defined, then take described the second photoresist mask layer as APF material layer described in mask etch, form the core-wire 13(core line between groove and groove), as shown in Figure 4, then described photoresist mask layer is removed in etching.
Particularly, in this step, select APF material layer described in O base etchant etching, select in one embodiment of this invention O
2atmosphere, can also add such as CF of other a small amount of gas simultaneously
4, CO
2, N
2, described etching pressure can be 50-200mTorr, is preferably 100-150mTorr, power is 200-600W, and described etching period is 5-80s, more preferably 10-60s in the present invention, select in the present invention larger gas flow, as preferably, at O of the present invention simultaneously
2flow be 30-300sccm, more preferably 50-100sccm.
With reference to Fig. 5, deposited sidewalls material layer 105 on substrate, to cover described dielectric layer and described core-wire 13(core line), wherein said side-wall material layer is silicide, particularly, described silicide can be the oxide of silicon, the nitride of silicon, the nitrogen oxide of silicon, be preferably SiC, SiCN or SiO2, the deposition of described side-wall material layer can be selected chemical vapor deposition (CVD) method, the low-pressure chemical vapor deposition (LPCVD) that physical vapor deposition (PVD) method or ald (ALD) method etc. form, one in laser ablation deposition (LAD) and selective epitaxy growth (SEG).Preferred ald (ALD) method in the present invention.
With reference to Fig. 6, side-wall material layer described in etching, to form spaced walls on the sidewall at described strip core-wire; Particularly, select dry etching to carry out side-wall material layer described in etching, preferably C-F etchant carrys out side-wall material layer described in etching in the present invention, and described C-F etchant is CF
4, CHF
3, C
4f
8and C
5f
8in one or more.In an embodiment of the present invention, described dry etching can be selected CF
4, CHF
3, add in addition N
2, CO
2in one as etching atmosphere, wherein gas flow is CF
410-200sccm, CHF
310-200sccm, N
2or CO
2or O
210-400sccm, described etching pressure is 30-150mTorr, etching period is 5-120s, is preferably 5-60s, more preferably 5-30s.
With reference to Fig. 7, described strip core-wire is removed in etching, carry out no longer separately the step of end-grain cutting, to form parallel strip pattern, particularly, described strip core-wire is removed in etching, and to form the strip pattern with certain intervals, the removal method of described strip core-wire can be selected this area common method in the present invention.
With reference to Fig. 8, select electric conducting material to fill the groove between described strip core-wire, and planarization, to obtain even curface, realize the connection between described parallel strip pattern.Described electric conducting material preferable alloy copper in the present invention, but do not limit to and this metal material.
In addition, in the present invention except selecting electric conducting material to fill the groove between described strip core-wire, can also be take described parallel strip pattern as dielectric layer described in mask etch, so that described strip pattern is transferred in described dielectric layer.After the parallel strip pattern of formation, can there is multiple operating procedure, be not limited to two kinds provided by the present invention.
With reference to Figure 10, wherein show the manufacture method of the semiconductor device that the present invention is based on self-aligned double patterning case, comprise the following steps particularly:
Dielectric layer described in step 202 patterning, to remove the described dielectric layer of part and to form groove;
APF material layer described in step 204 etching, to form groove and the strip core-wire between groove;
Step 205 is deposited sidewalls material layer on substrate, and then side-wall material layer described in etching, to form spaced walls on the sidewall at described strip core-wire;
Described strip core-wire is removed in step 206 etching, carries out no longer separately the step of end-grain cutting, to form parallel strip pattern;
Step 207 selects electric conducting material fill the groove between strip pattern and carry out planarization, or take described parallel strip pattern as dielectric layer described in mask etch, so that described strip pattern is transferred in described dielectric layer.
Adopt in the present invention spacer patterns technology and self-aligned double patterning case technology, and described method is improved, make no longer to carry out end-grain cutting step in the rear end of semiconductor device processing procedure (BEOL) and can obtain target pattern, realize good connection simultaneously, solve in prior art and made whole manufacturing process complexity, wayward, caused the problem that semiconductor device yield is not high.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (13)
1. a manufacture method for the semiconductor device based on self-aligned double patterning case, comprising:
One rear end processing procedure device is provided, at least comprises Semiconductor substrate and be positioned at the dielectric layer in described Semiconductor substrate;
Dielectric layer described in patterning, to remove the described dielectric layer of part and to form groove;
Deposition APF material layer planarization, to fill described groove;
APF material layer described in etching, to form groove and the strip core-wire between groove;
Deposited sidewalls material layer on substrate, then side-wall material layer described in etching, to form spaced walls on the sidewall at described strip core-wire;
Described strip core-wire is removed in etching, carries out no longer separately the step of end-grain cutting, to form parallel strip pattern.
2. method according to claim 1, is characterized in that, described method is further comprising the steps of:
Select electric conducting material fill the groove between strip pattern and carry out planarization.
3. method according to claim 1, is characterized in that, described method is further comprising the steps of:
Take described parallel strip pattern as dielectric layer described in mask etch, so that described strip pattern is transferred in described dielectric layer.
4. method according to claim 1, is characterized in that, the oxide that described side-wall material layer is silicon, the nitride of silicon, the nitrogen oxide of silicon.
5. method according to claim 1, is characterized in that, described side-wall material layer is SiC, SiCN or SiO
2.
6. method according to claim 1, is characterized in that, the method that deposits described side-wall material layer is atomic layer deposition method.
7. method according to claim 1, is characterized in that, the method for side-wall material layer is dry etching described in etching.
8. method according to claim 1, is characterized in that, selects C-F etchant described in etching when side-wall material layer.
9. method according to claim 8, is characterized in that, described C-F etchant is CF
4, CHF
3, C
4f
8and C
5f
8in one or more.
10. method according to claim 1, is characterized in that, selects O base etchant when described strip core-wire is removed in etching.
11. methods according to claim 1, is characterized in that, the step that forms described groove is included in the photoresist mask layer that forms patterning on described dielectric layer, and then dielectric layer described in patterning.
12. methods according to claim 1, is characterized in that, form the photoresist mask layer of patterning on described APF material layer, and then APF material layer described in etching, to form strip core-wire.
13. methods according to claim 1, is characterized in that, described dielectric layer is non-ultralow K material layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9779944B1 (en) | 2016-09-13 | 2017-10-03 | International Business Machines Corporation | Method and structure for cut material selection |
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| US6638441B2 (en) * | 2002-01-07 | 2003-10-28 | Macronix International Co., Ltd. | Method for pitch reduction |
| US20080149593A1 (en) * | 2005-08-25 | 2008-06-26 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
| US20090104786A1 (en) * | 2007-10-17 | 2009-04-23 | Kabushiki Kaisha Toshiba | Method of fabricating semiconductor device |
| US20090269932A1 (en) * | 2008-04-28 | 2009-10-29 | Sandisk 3D Llc | Method for fabricating self-aligned complimentary pillar structures and wiring |
| US20100330806A1 (en) * | 2009-06-29 | 2010-12-30 | Sandisk 3D Llc | Method of forming contact hole arrays using a hybrid spacer technique |
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|---|---|---|---|---|
| US6638441B2 (en) * | 2002-01-07 | 2003-10-28 | Macronix International Co., Ltd. | Method for pitch reduction |
| US20080149593A1 (en) * | 2005-08-25 | 2008-06-26 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
| US20090104786A1 (en) * | 2007-10-17 | 2009-04-23 | Kabushiki Kaisha Toshiba | Method of fabricating semiconductor device |
| US20090269932A1 (en) * | 2008-04-28 | 2009-10-29 | Sandisk 3D Llc | Method for fabricating self-aligned complimentary pillar structures and wiring |
| US20100330806A1 (en) * | 2009-06-29 | 2010-12-30 | Sandisk 3D Llc | Method of forming contact hole arrays using a hybrid spacer technique |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9779944B1 (en) | 2016-09-13 | 2017-10-03 | International Business Machines Corporation | Method and structure for cut material selection |
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