CN103777732B - The control method of adapter, adapter and memorizer memory devices - Google Patents
The control method of adapter, adapter and memorizer memory devices Download PDFInfo
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- CN103777732B CN103777732B CN201210405185.5A CN201210405185A CN103777732B CN 103777732 B CN103777732 B CN 103777732B CN 201210405185 A CN201210405185 A CN 201210405185A CN 103777732 B CN103777732 B CN 103777732B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The control method of a kind of adapter, memorizer memory devices and adapter.This control method includes: receive the first train of signal in the case of a squelch detector of adapter is pent；Under the first operation frequency, judge whether this first train of signal includes a burst；If the first train of signal includes burst, start above-mentioned squelch detector, and under the second operation frequency, judged whether secondary signal string is wake-up signal by squelch detector, wherein secondary signal string be received in the first train of signal after, and the second operation frequency is more than the first operation frequency.This control method also includes: if secondary signal string is wake-up signal, changes the mode of operation of adapter to starting state.Thereby, it is possible to reduce the power consumption of adapter.
Description
Technical field
The invention relates to the control method of a kind of adapter and use adapter and the memory storage of the method
Device.
Background technology
Digital camera, mobile phone and MP3 player are the rapidest in growth over the years so that consumer is to storage
The demand of media increases the most rapidly.Due to reproducible nonvolatile memorizer module (such as, flash memory), to have data non-volatile
Property, power saving, volume are little, and the characteristic such as mechanical structure, so being especially suitable for being built into above-mentioned illustrated various portable
In multimedia device.
In general, reproducible nonvolatile memorizer module is to be controlled by a Memory Controller, and deposits
Memory controller can be coupled to a host computer system by an adapter.The standard met according to this adapter, generally connects
The mode of operation connecing device includes starting state and a non-started state to I haven't seen you for ages.In starting state, host computer system can be deposited
Take this reproducible nonvolatile memorizer module.In non-started state, Memory Controller can close the unit of its part
Part or function, thereby save the consumption of power.But, in non-started state, adapter have to detect from host computer system
Signal, thereby determine whether to reply as starting state.It is to say, it is necessary to have the element of part continues fortune in adapter
Make to detect the signal that host computer system transmits.Therefore, how under non-started state, to save the power that adapter consumes further,
For those skilled in the art's subject under discussion of interest.
Summary of the invention
The exemplary embodiment of the present invention proposes the control method of a kind of adapter, adapter and memorizer memory devices,
Adapter power consumption under non-started state can be saved.
The present invention one exemplary embodiment proposes the control method of a kind of adapter.This control method includes: at adapter
The first train of signal is received in the case of one squelch detector is pent；Under the first operation frequency, judge that this first train of signal is
No include a burst；If the first train of signal includes burst, start squelch detector, and by squelch detector the
Two operation frequencies judge whether secondary signal string is wake-up signal, wherein secondary signal string be received in the first train of signal it
After, and the second operation frequency is more than the first operation frequency.This control method also includes: if secondary signal string is wake-up signal,
Change the mode of operation of adapter to starting state.
In an exemplary embodiment, above-mentioned control method also includes: if secondary signal string is not wake-up signal, close quiet
Make an uproar detector, receive the 3rd signal, and judge whether the 3rd signal includes burst.
In an exemplary embodiment, above-mentioned under the first operation frequency, judge whether the first train of signal includes burst
Step includes: judge under the first operation frequency whether the first train of signal includes that length is more than or equal to the son letter of n unit interval
Number, wherein n is the positive integer more than or equal to 2；And if the first train of signal includes described subsignal, it is judged that the first train of signal bag
Include burst.
In an exemplary embodiment, above-mentioned positive integer n is 5.
In an exemplary embodiment, above-mentioned under the second operation frequency, judge that by squelch detector whether secondary signal string is
The step of wake-up signal includes: being judged whether secondary signal string includes m burst by squelch detector, wherein m is the most whole
Number；If secondary signal string includes m burst, squelch detector judge that secondary signal string is wake-up signal.
The present invention one exemplary embodiment proposes a kind of memorizer memory devices.This memorizer memory devices includes connecting
Device, reproducible nonvolatile memorizer module and Memory Controller.Adapter is in order to be coupled to a host computer system.Can answer
The formula non-volatile memory module of writing includes multiple physics erased cell.Memory Controller is coupled to adapter and can make carbon copies
Formula non-volatile memory module.Above-mentioned adapter includes state controller, squelch detector and burst detector.Noise elimination is examined
Survey device and be coupled to state controller.Burst detector is coupled to squelch detector, in order to pent in squelch detector
In the case of receive the first train of signal, and under the first operation frequency, judge whether the first train of signal includes a burst.
If the first train of signal includes burst, burst detector is in order to start squelch detector.After squelch detector is waken up,
Squelch detector is in order to judge under the second operation frequency whether secondary signal string is wake-up signal, wherein a secondary signal string
Be be received in the first train of signal after, and the second operation frequency is more than the first operation frequency.If secondary signal string is for waking up up
Signal, state controller is in order to change the mode of operation of adapter to starting state.
In an exemplary embodiment, if secondary signal string is not wake-up signal, burst detector is also in order to close noise elimination inspection
Survey device, receive the 3rd signal, and judge whether the 3rd signal includes burst.
In an exemplary embodiment, above-mentioned burst detector judges whether the first train of signal includes under the first operation frequency
The operation of burst includes: burst detector judges under the first operation frequency whether the first train of signal includes that length is more than
In the subsignal of n unit interval, wherein n is the positive integer more than or equal to 2；If the first train of signal includes subsignal, noise elimination is examined
Survey device and can judge that the first train of signal includes burst.
In an exemplary embodiment, above-mentioned positive integer n is 5.
In an exemplary embodiment, above-mentioned squelch detector judges that whether secondary signal string is the operation bag of wake-up signal
Include: squelch detector judges whether secondary signal string includes m burst, and wherein m is positive integer；If secondary signal string includes
M burst, squelch detector judges that secondary signal string is wake-up signal.
The present invention one exemplary embodiment proposes a kind of adapter, detects with burst including state controller, squelch detector
Device.Squelch detector is coupled to state controller.Burst detector is coupled to squelch detector, in order in squelch detector
Receive the first train of signal in the case of pent, and under the first operation frequency, judge whether the first train of signal includes a burst
Signal.If the first train of signal includes burst, burst detector can start squelch detector.Squelch detector be waken up with
After, squelch detector is in order to judge under the second operation frequency whether secondary signal string is a wake-up signal, and wherein second believes
Number string be received in the first train of signal after, and the second operation frequency is more than the first operation frequency.If secondary signal string is
Wake-up signal, state controller is in order to change the mode of operation of adapter to starting state.
In an exemplary embodiment, if secondary signal string is not wake-up signal, burst detector is also in order to close noise elimination inspection
Survey device, receive the 3rd signal, and judge whether the 3rd signal includes burst.
In an exemplary embodiment, above-mentioned burst detector judges whether the first train of signal includes under the first operation frequency
The operation of burst includes: burst detector judges under the first operation frequency whether the first train of signal includes that length is more than
In a subsignal of n unit interval, wherein n is the positive integer more than or equal to 2；If the first train of signal includes subsignal, noise elimination
Detector judges that the first train of signal includes burst.
In an exemplary embodiment, above-mentioned positive integer n is 5.
In an exemplary embodiment, above-mentioned squelch detector judges that whether secondary signal string is the operation bag of wake-up signal
Include: squelch detector judges whether secondary signal string includes m burst, and wherein m is positive integer；If secondary signal string includes
M burst, squelch detector judges that secondary signal string is wake-up signal.
In an exemplary embodiment, above-mentioned burst detector includes that low-power squelch detector controls with squelch detector
Circuit.Above-mentioned squelch detector includes squelch detecting circuit and frequency external signal decision circuitry.Squelch detector control circuit is
It is coupled to low-power squelch detector.Squelch detecting circuit is coupled to squelch detector control circuit.Frequently external signal judges electricity
Road is coupled to squelch detecting circuit and state controller.Low-power squelch detector is in order to pent at squelch detecting circuit
In the case of receive the first train of signal, and under the first operation frequency, judge whether the first train of signal includes burst.If the
One train of signal includes burst, and squelch detector control circuit is in order to start squelch detecting circuit.At squelch detecting circuit quilt
After startup, squelch detecting circuit is in order to detect the second burst in secondary signal string and interval under the second operation frequency
Signal, and according to the second burst and blank signal, frequency external signal decision circuitry is in order to judge that whether secondary signal string is for calling out
Awake signal.
The present invention one exemplary embodiment proposes a kind of adapter meeting Serial Advanced Technology Attachment standard.This adapter bag
Include low frequency signal detector, signal detector control circuit, high-frequency detector, high-frequency signal decision circuitry and state controller.
Signal detector control circuit is coupled to low frequency signal detector.High-frequency detector is coupled to signal detector and controls electricity
Road.High-frequency signal decision circuitry is coupled to high-frequency detector.State controller be coupled to signal detector control circuit with
High-frequency signal decision circuitry.Low frequency signal detector in order to receive the first train of signal in the case of high-frequency detector is pent,
And under the first operation frequency, judge whether the first train of signal includes first signal model.If the first train of signal includes
One signal model, signal detector control circuit is in order to start high-frequency detector.After high-frequency detector is actuated to, high frequency is examined
Survey device in order to detect whether secondary signal string includes a secondary signal model under the second operation frequency.Wherein secondary signal string
Be be received in the first train of signal after, the second operation frequency is more than the first operation frequency, and the first signal model is different from
Secondary signal model.If secondary signal string includes secondary signal model, state controller is in order to change the mode of operation of adapter
For starting state.
In an exemplary embodiment, the first above-mentioned operation frequency is not more than the half of the second operation frequency.
Based on above-mentioned, in the control method that the embodiment of the present invention proposes, adapter and memorizer memory devices, due to even
Connecing device squelch detector under non-started state is to be closed, and is to be detected dashing forward from host computer system by burst detector
Signal, therefore can reduce the power that adapter consumes.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate institute's accompanying drawings
It is described in detail below.
Accompanying drawing explanation
Figure 1A is according to the host computer system depicted in an exemplary embodiment and memorizer memory devices.
Figure 1B is according to the computer depicted in an exemplary embodiment, input/output device and memorizer memory devices
Schematic diagram.
Fig. 1 C is the schematic diagram according to the host computer system depicted in an exemplary embodiment Yu memorizer memory devices.
Fig. 2 is the schematic block diagram illustrating the memorizer memory devices shown in Figure 1A.
Fig. 3 is the schematic block diagram according to the Memory Controller depicted in an exemplary embodiment.
Fig. 4 is the circuit block diagram illustrating adapter according to an embodiment.
Fig. 5 is the schematic diagram illustrating wake-up signal, registration signal and D24.3 characteristic signals according to an exemplary embodiment.
Fig. 6 is the flow chart of the control method illustrating adapter according to an exemplary embodiment.
Fig. 7 is the circuit block diagram illustrating adapter according to the second exemplary embodiment.
Fig. 8 illustrates adapter according to the second exemplary embodiment and switches between starting state and part/sleep state
Flow chart.
Fig. 9 is the circuit block diagram illustrating adapter according to the 3rd exemplary embodiment.
[main element label declaration]
1000: host computer system 1100: computer
1102: microprocessor 1104: random access memory
1106: input/output device 1108: system bus
1110: data transmission interface 1202: mouse
1204: keyboard 1206: display
1208: printer 1212: portable disk
1214: storage card 1216: solid state hard disc
1310: digital camera 1312:SD card
1314:MMC card 1316: memory stick
1318:CF card 1320: embedded storage device
100: memorizer memory devices 102,900: adapter
104: Memory Controller 106: reproducible nonvolatile memorizer module
304 (0)～304 (R): physics erased cell 202: memory management circuitry
204: HPI 206: memory interface
252: buffer storage 254: electric power management circuit
256: error checking and correcting circuit 401,901: train of signal
410: burst detector 420: squelch detector
430,930: state controller 510: wake-up signal
511a～511f: burst 512a～512f: blank signal
520: registration signal 530:D24.3 characteristic signals
521,531: subsignal 540: unit interval
The step of the control method of S602, S604, S606, S608, S610: adapter
411: low-power squelch detecting circuit 412: squelch detector control circuit
421: squelch detecting circuit 422: external signal decision circuitry frequently
S802, S804, S806, S808, S810, S812, S814: step
911: low frequency signal detector 912: signal detector control circuit
921: high-frequency signal detector 922: high-frequency signal decision circuitry
Detailed description of the invention
[the first exemplary embodiment]
It is said that in general, memorizer memory devices (also known as, memory storage system) includes duplicative non-volatile memories
Device module and controller (also known as, control circuit).Being commonly stored device storage device is to be used together with host computer system, so that main frame
System can write data into memorizer memory devices or read data from memorizer memory devices.
Figure 1A is according to the host computer system depicted in an exemplary embodiment and memorizer memory devices.
Refer to Figure 1A, host computer system 1000 generally comprises computer 1100 and input/output (input/output, I/
O) device 1106.Computer 1100 include microprocessor 1102, random access memory (random access memory,
RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 includes the mouse such as Figure 1B
1202, keyboard 1204, display 1206 and printer 1208.It will be appreciated that the unrestricted input of device shown in Figure 1B/defeated
Going out device 1106, input/output device 1106 can also include other device.
In embodiments of the present invention, memorizer memory devices 100 is by data transmission interface 1110 and host computer system
Other element of 1000 couples.By microprocessor 1102, random access memory 1104 and the fortune of input/output device 1106
Work can write data into memorizer memory devices 100 or read data from memorizer memory devices 100.Such as, memorizer
Storage device 100 can be portable disk 1212 as shown in Figure 1B, storage card 1214 or solid state hard disc (Solid State
Drive, SSD) the type nonvolatile storage device of 1216 grades.
It is said that in general, host computer system 1000 is for coordinating with memorizer memory devices 100 substantially to store appointing of data
Meaning system.Although in this exemplary embodiment, host computer system 1000 is to explain with computer system, but, in the present invention
In another exemplary embodiment, host computer system 1000 can be that digital camera, camera, communicator, audio player or video are broadcast
Put the systems such as device.Such as, when host computer system is digital camera (camera) 1310, type nonvolatile stores
Device is then by its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedding
Formula storage device 1320 (as shown in Figure 1 C).Embedded storage device 1320 include embedded multi-media card (Embedded MMC,
eMMC).It is noted that embedded multi-media card is to be coupled directly on the substrate of host computer system.
Fig. 2 is the schematic block diagram illustrating the memorizer memory devices shown in Figure 1A.
Refer to Fig. 2, memorizer memory devices 100 includes that adapter 102, Memory Controller 104 are non-with duplicative
Volatile 106.
In this exemplary embodiment, adapter 102 is to be compatible to Serial Advanced Technology Attachment (Serial Advanced
Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not restricted to this, adapter 102 is also
Can be to meet high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI
Express) standard or other standard being suitable for.
Memory Controller 104 refers to hardware pattern or multiple gates of firmware pattern implementation or control in order to performing
Order, and according to the instruction of host computer system 1000 carry out in reproducible nonvolatile memorizer module 106 data write,
Read and erasing etc. operates.
Reproducible nonvolatile memorizer module 106 is coupled to Memory Controller 104, and in order to store main frame
The data that system 1000 is write.Reproducible nonvolatile memorizer module 106 has physics erased cell 304 (0)～304
(R).Such as, physics erased cell 304 (0)～304 (R) can belong to same memory crystal grain (die) or belong to different
Memory crystal grain.Each physics erased cell is respectively provided with multiple physics programming unit, and belongs to same physics and erase list
The physics programming unit of unit can be written independently and simultaneously be erased.Such as, each physics erased cell is by 128 things
Reason programming unit is formed.However, it is necessary to be appreciated that, the invention is not restricted to this, each physics erased cell is can be by 64
Physics programming unit, 256 physics programming units or other arbitrarily physics programming unit are formed.
In more detail, physics erased cell is the least unit erased.That is, each physics erased cell contains minimum
The memory element being erased in the lump of number.Physics programming unit is the minimum unit of programming.That is, physics programming unit is write
The minimum unit of data.Each physics programming unit generally includes data bit district and redundancy function district.Data bit district comprises multiple thing
Reason access address is in order to store the data of user, and redundancy function district (such as, controls information and mistake in order to the data of stocking system
More code by mistake).In this exemplary embodiment, the data bit district of each physics programming unit can comprise 4 physics access ground
Location, and the size of a physics access address is 512 bytes (byte, B).But, in other exemplary embodiment, data bit district
In also can comprise 8,16 or number more or less of physics access address, the present invention is not limiting as physics access address
Size and number.Such as, physics erased cell is physical blocks, and physics programming unit is physical page or physics fan.
In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is multi-level cell memory (Multi
Level Cell, MLC) NAND-type flash memory module, i.e. one memory element can store at least 2 bit data.But, the present invention
Be not limited to this, reproducible nonvolatile memorizer module 106 also single-order memory element (Single Level Cell,
SLC) NAND-type flash memory module, multi-level cell memory (Trinary Level Cell, TLC) NAND-type flash memory module, other sudden strain of a muscle
Storing module or other there is the memory module of identical characteristics.
Fig. 3 is the schematic block diagram according to the Memory Controller depicted in an exemplary embodiment.
Refer to Fig. 3, Memory Controller 104 includes that memory management circuitry 202, HPI 204 connect with memorizer
Mouth 206.
Memory management circuitry 202 is in order to control the overall operation of Memory Controller 104.Specifically, memorizer pipe
Reason circuit 202 has multiple control instruction, and when memorizer memory devices 100 operates, these a little control instructions can be performed
To carry out the write of data, running of reading and erase etc..
In this exemplary embodiment, the control instruction of memory management circuitry 202 is to carry out implementation with firmware pattern.Such as,
Memory management circuitry 202 has microprocessor unit (not illustrating) and read only memory (not illustrating), and this controls to refer to a bit
Order is to be programmed so far in read only memory.When memorizer memory devices 100 operates, these a little control instructions can be by microprocessor
Unit performs to carry out the write of data, running of reading and erase etc..
In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also procedure code pattern
The specific region being stored in reproducible nonvolatile memorizer module 106 (such as, is exclusively used in storage system in memory module
The system area of data) in.Additionally, memory management circuitry 202 has microprocessor unit (not illustrating), read only memory (not
Illustrate) and random access memory (not illustrating).Particularly, this read only memory has driving code, and when memorizer controls
When device 104 is enabled, microprocessor unit can first carry out this and drive code section will to be stored in type nonvolatile
Control instruction in module 106 is loaded onto in the random access memory of memory management circuitry 202.Afterwards, microprocessor list
Unit can operate these a little control instructions to carry out the write of data, running of reading and erase etc..
Additionally, in another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also a hardware
Pattern carrys out implementation.Such as, memory management circuitry 202 include microcontroller, MMU, memorizer writing unit,
Memorizer reads unit, memorizer erased cell and data processing unit.MMU, memorizer writing unit, deposit
Reservoir reads unit, memorizer erased cell is coupled to microcontroller with data processing unit.Wherein, MMU
In order to manage the physical blocks of reproducible nonvolatile memorizer module 106；Memorizer writing unit is in order to duplicative
Non-volatile memory module 106 assigns write instruction to write data into reproducible nonvolatile memorizer module 106
In；Memorizer reads unit in order to reproducible nonvolatile memorizer module 106 to be assigned reading instruction with from duplicative
Non-volatile memory module 106 reads data；Memorizer erased cell is in order to type nonvolatile mould
Block 106 assigns instruction of erasing data to be erased from reproducible nonvolatile memorizer module 106；And data processing unit
It is intended to write to the data of reproducible nonvolatile memorizer module 106 and from duplicative non-volatile memories in order to process
The data read in device module 106.
HPI 204 is coupled to memory management circuitry 202 and in order to receive and to identify host computer system 1000 institute
The instruction transmitted and data.It is to say, the instruction that host computer system 1000 is transmitted can be passed by HPI 204 with data
Deliver to memory management circuitry 202.In this exemplary embodiment, HPI 204 is compatible with SATA standard.However, it is necessary to
Being appreciated that and the invention is not restricted to this, HPI 204 can also be compatible with PCI Express standard or other number being suitable for
According to transmission standard.
Memory interface 206 is coupled to memory management circuitry 202 and duplicative is non-volatile to be deposited in order to access
Memory modules 106.It is to say, the data being intended to write to reproducible nonvolatile memorizer module 106 can be via memorizer
Interface 206 is converted to the receptible form of reproducible nonvolatile memorizer module 106.
In the present invention one exemplary embodiment, Memory Controller 104 also includes buffer storage 252, power management electricity
Road 254 and error checking and correcting circuit 256.
Buffer storage 252 is coupled to memory management circuitry 202 and is configured to temporarily store and comes from host computer system 1000
Data and instruction or come from the data of reproducible nonvolatile memorizer module 106.
Electric power management circuit 254 is coupled to memory management circuitry 202 and in order to control memorizer memory devices 100
Power supply.
Error checking and correcting circuit 256 be coupled to memory management circuitry 202 and in order to perform error checking with
Correction program is to guarantee the correctness of data.Specifically, receive from host computer system 1000 when memory management circuitry 202
During write instruction, error checking and correcting circuit 256 can be the data of this write instruction corresponding produce corresponding error checking and
Correcting code (Error Checking and Correcting Code, ECC Code), and memory management circuitry 202 can be by
The data of this write instruction corresponding write to reproducible nonvolatile memorizer module with correcting code with corresponding error checking
In 106.Afterwards, when memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106 together with
Time read error checking corresponding to these data and correcting code, and error checking can be according to this error checking with correcting circuit 256
Error checking and correction program is performed with the correcting code data to being read.
Fig. 4 is the circuit block diagram illustrating adapter according to an embodiment.
Refer to Fig. 4, adapter 102 includes burst detector 410 (burst detector), squelch detector 420
(squelch detector) and state controller 430.
State controller 430 is the mode of operation in order to control connector.When host computer system 100 is accessing memorizer storage
During cryopreservation device 100, the mode of operation of adapter 102 is starting state.Otherwise, if host computer system 100 memorizer to be accessed
Storage device 100, then state controller 430 can enter a non-started state with control connector 102.At non-started state
In, adapter 102 or Memory Controller 104 can close some of circuit, thereby save the consumption of power.The opposing party
Face, when adapter 102 is at non-started state, if host computer system 100 transmits a wake-up signal to adapter 102, then state
It is starting state that controller 430 can change the mode of operation of adapter 102.In other words, adapter 102 can be compatible with any fixed
The justice standard of wake-up signal.Such as, if adapter 102 is compatible with SATA standard, then the mode of operation of adapter 102 includes opening
Dynamic (active) state, partly (partial) state and sleep (slumber) state.Partial status and sleep state are also closed
It is referred to as non-started state.If it is starting state that adapter 102 to be replied from non-started state, then need to spend a period of time.One
For as, dormant power saving effect is better than the power saving effect of partial status, but replys as starting state institute from sleep state
It is long that the time needed replys the time for starting state than from partial status.
Squelch detector 420 is to detect the power grade of train of signal 401 (power level).Train of signal 401 can wrap
Include one or more signal.If the power grade of train of signal 401 is less than a predetermined level, then squelch detector 420 can be closed not
There is the circuit used.Such as, when the power grade of train of signal 401 is less than predetermined level, squelch detector 420 can send one
Individual message is to state controller 430, and state controller 430 can be according to the mode of operation of this message sets adapter 102
Non-started state.On the other hand, if the power grade of train of signal 401 is higher than predetermined level, (such as, train of signal 401 includes one
Individual wake-up signal), then squelch detector 420 can change the mode of operation of adapter 102 for starting shape by drive state controller 430
State.In an exemplary embodiment, train of signal 401 is frequency external signal (out-of-band signaling, OOB-signaling).
And frequency external signal is a kind of Data Styles (data pattern), there is defined interval (gap) signal and burst (burst) letter
Number.The amplitude of burst can be with a frequency (such as, 1.5G hertz) vertical tremor, and the amplitude of blank signal signal is then tieed up
Hold constant.In other words, train of signal 401 can include one or more blank signal and burst.In frequency external signal, wake up letter up
Number at least including 6 blank signals and 6 bursts, squelch detector 420 can detect these blank signals and burst,
And judge whether train of signal 401 includes wake-up signal.
Burst detector 410 is to start or close squelch detector 420, and detects whether train of signal 401 includes
One burst.Specifically, burst detector 410 operates under the first operation frequency, and squelch detector 420 is behaviour
Make under the second operation frequency, and the second operation frequency can be more than the first operation frequency.Under the second operation frequency, noise elimination is examined
Survey device 420 and blank signal and burst can completely be detected.Under the first operation frequency, burst detector 410 can detect
To blank signal and the subsignal of part in burst.For example, transmission between adapter 102 and host computer system 1000
Blank signal is 1.5G hertz with the peak frequency of burst；Second operation frequency is 1.5G hertz；And the first operation frequency
Rate is 750M hertz.Therefore, burst detector 410 can detect that blank signal and its frequency in burst are less than 750M hertz
Subsignal.
Fig. 5 is the schematic diagram illustrating wake-up signal, registration signal and D24.3 characteristic signals according to an exemplary embodiment.
Refer to Fig. 5, wake-up signal 510 includes burst 511a～511f and blank signal 512a～512f.And it is every
One burst can be made up of four alignment (align) signals 520 or four D24.3 characteristic signals 530.Here,
One unit interval represents the length (that is, cycle) of the maximum subsignal of wake-up signal 510 medium frequency.Such as, wake-up signal 510
Peak frequency be 1.5G hertz, therefore each unit interval (unit interval) is 1/1.5G second (such as, unit district
Between 540).The beginning of registration signal 521 can include the subsignal 521 of a length of 5 unit intervals, is next multiple a length of
The subsignal of 1 or 2 unit interval.And D24.3 characteristic signals 530 is made up of the subsignal of a length of 2 unit intervals entirely
(such as, subsignal 531).In this exemplary embodiment, the operation frequency of squelch detector 420 is 1.5G hertz, the most permissible
Complete subsignal random length being detected；The operation frequency of burst detector 410 is 750M hertz, can detect length and be more than
Subsignal (that is, frequency is less than the subsignal of 750M hertz) equal to 2 unit intervals.
In this exemplary embodiment, when the mode of operation of adapter 102 is at partial status or sleep state, noise elimination
Detector 420 can be closed and burst detector 410 can be activated.Significantly, since the second operation frequency is less than the
One operation frequency, the power that therefore burst detector 410 is consumed when operating is consumed when can operate less than squelch detector 420
Power.When burst detector 410 receives first train of signal 401, can first judge whether this first train of signal includes
One burst.Such as, whether burst detector 410 includes in judging this first train of signal 401 that length is more than or equal to n
The subsignal of unit interval, wherein n is the positive integer more than or equal to 2.Such as, n is positive integer 2, and therefore burst detector 410 can
Subsignal 521 and 531 to be detected.If the first train of signal includes that length is more than or equal to the subsignal of n unit interval, burst
Detector 410 will judge that the first train of signal includes a burst and starts squelch detector 420.
After squelch detector 420 is waken up, squelch detector 420 may proceed to receive a secondary signal string, and sentences
Whether disconnected secondary signal string is wake-up signal.This secondary signal string be connected at the first train of signal after send adapter 102 to
Signal.Such as, the first train of signal includes burst 511a, and secondary signal string includes burst 511b～511f.?
In one exemplary embodiment, if squelch detector 420 judges that secondary signal string includes m burst, squelch detector 420 meeting
Judging that secondary signal string is wake-up signal, wherein m is positive integer (such as, m is 4).In other words, examine when burst detector 410
Squelch detector 420 can be started after measuring first burst 511a, and detected by squelch detector 420 ensuing prominent
Signalling 511b～511f.Significantly, since wake-up signal 510 can include 6 burst 511a～511f and 6
Blank signal 512a～512f, and burst detector 410 have received burst 511a, therefore in an exemplary embodiment
M can be set less than 6.
If squelch detector 420 judges that secondary signal string is wake-up signal, squelch detector 420 can transmit a message to
State controller 430.State controller 430 can be starting state according to the mode of operation of this message alteration adapter 102.
In other exemplary embodiment, the blank signal of transmission and burst letter between adapter 102 and host computer system 1000
Number peak frequency can also be for 3.0G hertz (now a unit interval is the 1/3G second) or other numerical value, the present invention is not
Limit at this.In an exemplary embodiment, when the peak frequency of blank signal Yu burst is 3.0G hertz, the first operation frequency
Rate is 1.5G hertz, and the second operation frequency is 3.0G hertz.But, the first operation frequency and the second operation frequency can also be by
Being set as other numerical value, the present invention is the most not subject to the limits.
In an exemplary embodiment, if the wake-up signal received by adapter 102 is only made up of registration signal, then dash forward
Send out detector 410 and n can be set as 5.That is, when the first train of signal including length more than or equal to 5 unit intervals
During subsignal (such as, subsignal 521), burst detector 410 just can judge that the first train of signal includes burst.Such one
Come, lower (such as, 300M hertz) that the operation frequency of burst detector 410 can set, thereby reduce burst inspection further
Survey the power consumed when device 410 operates.But, in other exemplary embodiment, n can be set as by burst detector 410
3,4 or other numerical value, the present invention is the most not subject to the limits.
In an exemplary embodiment, connect if burst detector 410 can detect within the time of a burst
Whether the signal received includes a burst, and m can also be set as 5 by squelch detector 420.Or, squelch detector 420
M can also be set as 3 or other numerical value, and the present invention is the most not subject to the limits.
Fig. 6 is the flow chart of the control method illustrating adapter according to an exemplary embodiment.
Refer to Fig. 6, in step S602, in the case of squelch detector is pent, burst detector 410 can receive
One the first train of signal.In step s 604, whether burst detector 410 can judge the first train of signal under the first operation frequency
Including a burst.If the first train of signal does not include burst, then return to step S602.If the first train of signal includes dashing forward
Signaling, in step S606, burst detector 410 can start squelch detector 420.In step S608, squelch detector
420 judge under the second operation frequency whether secondary signal string is wake-up signal, and wherein the second operation frequency is more than the first operation
Frequency.If secondary signal string is wake-up signal, in step S610, state controller 430 can change the mode of operation of adapter
For starting state.But, in Fig. 6, each step it is stated that as above, just repeats no more at this.
[the second exemplary embodiment]
Second embodiment is similar with first embodiment part, only describes difference at this.
Fig. 7 is the circuit block diagram illustrating adapter according to the second exemplary embodiment.
Refer to Fig. 7, in the second exemplary embodiment, burst detector 410 includes low-power squelch detecting circuit 411
With squelch detector control circuit 412.Squelch detector 420 includes squelch detecting circuit 421 and frequency external signal decision circuitry
422.Low-power squelch detecting circuit 411 is in order to detect a burst under the first operation frequency.Squelch detector control
Circuit 412 processed is to control (such as, start or close) squelch detecting circuit 421.Squelch detecting circuit 421 is in order to
Detect the burst in a signal under two operation frequencies, and frequency external signal decision circuitry 422 is to judge a signal
Whether it is wake-up signal.
Specifically, when adapter 102 is part/sleep state, squelch detecting circuit 421 can be closed.At noise elimination
In the case of testing circuit 421 is pent, low-power squelch detecting circuit 411 can receive train of signal 401, and judges train of signal
Whether 401 include that length is more than or equal to the subsignal of n unit interval.If it is single more than or equal to n that train of signal 401 includes length
The subsignal that position is interval, squelch detector control circuit 412 can start squelch detecting circuit 421.Squelch detecting circuit 421 can continue
Secondary signal string is received in continued access, and detects the burst in secondary signal string and blank signal.Frequently external signal decision circuitry 422
Can judge whether secondary signal string is wake-up signal according to the burst in secondary signal string and blank signal.Such as, if
Secondary signal string includes m burst, then frequency external signal decision circuitry 422 can judge that secondary signal string is wake-up signal.Separately
On the one hand, if frequency external signal decision circuitry 422 judges that secondary signal string is not wake-up signal, squelch detector control circuit 412
Squelch detector 421 can be closed, only received next signal (the also known as the 3rd signal) by low-power squelch detecting circuit 411, and
And judged whether this 3rd signal includes a burst by low-power squelch detecting circuit 411.
Fig. 8 illustrates adapter according to the second exemplary embodiment and switches between starting state and part/sleep state
Flow chart.
Refer to Fig. 8, in step S802, adapter 102 enters starting state.
In step S804, state controller 430 determines whether to want entering part/sleep state.Such as, state controls
Device 430 can according to the instruction of the instruction of host computer system 1000 or Memory Controller 104 decide whether to entering part/
Sleep state.Or, state controller 430 can also be determined whether to enter by the information (such as, stand-by time) of itself
Partly/sleep state.
To entering part/sleep state, in step S806, state controller 430 can set adapter 102 inlet portion
Point/sleep state.Now, squelch detector control circuit 412 can close squelch detecting circuit 421.
In step S808, low-power squelch detecting circuit 411 determines whether to detect burst.
If low-power squelch detecting circuit 411 detects burst, in step S810, squelch detector controls electricity
Road 412 can start squelch detecting circuit 421.
In step S812, squelch detector 420 determines whether wake-up signal to be detected.Specifically, squelch detection
Circuit 421 can detect the burst in secondary signal string, and frequency external signal decision circuitry 422 can judge this secondary signal string
Whether it is wake-up signal.
If squelch detector 420 judges that this secondary signal string is wake-up signal, can return to step S802, wherein state controls
Device 430 control connector 102 can enter starting state.If squelch detector 420 does not detect wake-up signal, in step
In S814, squelch detector control circuit 412 can close squelch detecting circuit 421, and returns to step S808.But, in Fig. 8
Each step has described in detail as above, just repeats no more at this.
[the 3rd exemplary embodiment]
Fig. 9 is the circuit block diagram according to the adapter depicted in the 3rd exemplary embodiment.
Refer to Fig. 9, adapter 900 includes that low frequency signal detector 911, signal detector control circuit 912, high frequency are believed
Number detector 921, high-frequency signal decision circuitry 922 and state controller 930.Adapter 900 is to meet serial advanced technology
Attachments standards, and train of signal 901 can meet the definition of frequency external signal.Adapter 900 can be installed in a host computer system, hard
On dish, portable disk, solid state hard disc, personal computer or server, the present invention is the most not subject to the limits.
When adapter 900 is when partial status is with sleep state, and high-frequency signal detector 921 can be closed and low frequency signal
Detector 911 can be activated.Low frequency signal detector 911 is in order to connect in the case of high-frequency signal detector 921 is pent
Receive train of signal 901 (the also known as first train of signal), and under the first operation frequency, judge whether the first train of signal includes one the
One signal model.Such as, low frequency signal detector 911 judges whether the first train of signal has a certain amount of burst
(the referred to as first burst), if then judging that the first train of signal includes the first signal model.This first burst symbol
The pulse signal of unification characteristic frequency, its frequency is e.g. not more than 750M hertz (Hz).If the first train of signal includes that first dashes forward
Signal, then signal detector control circuit 912 can start high-frequency signal detector 921.After being actuated to, high-frequency signal is examined
Survey device 921 and may proceed to receive a secondary signal string, and under the second operation frequency, whether detection secondary signal string includes
One secondary signal model, wherein this first signal model is different from secondary signal model.Secondary signal model is e.g. by counting
Individual blank signal is formed with several second bursts.Second burst meets the pulse signal of a characteristic frequency,
The frequency of this second burst can be identical or be different from the first burst.Such as, high-frequency signal decision circuitry 922 can basis
The second burst that high-frequency signal detector 921 is detected and blank signal judge that whether secondary signal string is one to wake up letter up
Number.For example, the wake-up signal in external signal can be at least being made up of with 6 the second bursts 6 blank signals frequently.
Specifically, the first operation frequency can be less than the second operation frequency.Such as, the first operation frequency is not more than the second operation frequency
Half, but the present invention not subject to the limits.If secondary signal string includes a secondary signal model (such as, wake-up signal), then shape
It is starting state that state controller 930 can change the mode of operation of adapter 900.
In sum, the control method of the adapter proposed in the embodiment of the present invention, memorizer memory devices be connected
In device, owing to burst detector is detection burst under the first operation frequency, and just open when burst being detected
Kinetic power consumes bigger squelch detector, therefore can reduce adapter power consumption under non-started state.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any art
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when making a little change and retouching, therefore the present invention
Protection domain when being as the criterion depending on the defined person of scope of the appended claims.
Claims (19)
1. a control method for adapter, wherein this adapter includes a squelch detector, it is characterised in that this control method
Including:
One first train of signal is received in the case of this squelch detector is pent；
Under one first operation frequency, judge whether this first train of signal includes a burst；
If this first train of signal includes this burst, start this squelch detector, and by this squelch detector one second behaviour
Working frequency judges whether a secondary signal string is a wake-up signal, and wherein this secondary signal string is to be received in this first signal
After string, and this second operation frequency is more than this first operation frequency；And
If this secondary signal string is this wake-up signal, change a mode of operation of this adapter to a starting state.
Control method the most according to claim 1, also includes:
If this secondary signal string is not this wake-up signal, close this squelch detector, receive one the 3rd signal, and judge the 3rd
Whether signal includes this burst.
Whether control method the most according to claim 1, wherein judge this first train of signal under this first operation frequency
Step including this burst includes:
Under this first operation frequency, judge whether this first train of signal includes that length is more than or equal to a son letter of n unit interval
Number, wherein n is the positive integer more than or equal to 2；And
If this first train of signal includes this subsignal, it is judged that this first train of signal includes this burst.
Control method the most according to claim 3, wherein this positive integer n is 5.
Control method the most according to claim 1, wherein being judged under this second operation frequency by this squelch detector should
Whether secondary signal string is that the step of this wake-up signal includes:
Being judged whether this secondary signal string includes m burst by this squelch detector, wherein m is positive integer；
If this secondary signal string includes this m burst, this squelch detector judge that this secondary signal string is that this wakes up letter up
Number.
6. a memorizer memory devices, it is characterised in that this memorizer memory devices includes:
A connector, in order to be coupled to a host computer system；
One reproducible nonvolatile memorizer module, including multiple physics erased cell；And
One Memory Controller, is coupled to this adapter and this reproducible nonvolatile memorizer module,
Wherein this adapter includes:
One state controller；
One squelch detector, is coupled to this state controller；And
One burst detector, is coupled to this squelch detector, in order to receive one the in the case of this squelch detector is pent
One train of signal, and under one first operation frequency, judge whether this first train of signal includes a burst,
Wherein, if this first train of signal includes this burst, this burst detector in order to start this squelch detector,
After this squelch detector is actuated to, this squelch detector is in order to judge a secondary signal under one second operation frequency
String whether be a wake-up signal, wherein this secondary signal string be received in this first train of signal after, and this second operation
Frequency is more than this first operation frequency,
If this secondary signal string is this wake-up signal, this state controller opens to one in order to the mode of operation changing this adapter
Dynamic state.
Memorizer memory devices the most according to claim 6, if wherein this secondary signal string is not this wake-up signal, this is dashed forward
Send out detector also in order to close this squelch detector, receive one the 3rd signal, and judge whether the 3rd signal includes this burst
Signal.
Memorizer memory devices the most according to claim 6, wherein this burst detector is sentenced under this first operation frequency
Whether this first train of signal disconnected includes that the operation of this burst includes:
This burst detector judges whether this first train of signal includes that length is more than or equal to n unit under this first operation frequency
An interval subsignal, wherein n is the positive integer more than or equal to 2；
If this first train of signal includes this subsignal, this squelch detector judges that this first train of signal includes this burst.
Memorizer memory devices the most according to claim 8, wherein this positive integer n is 5.
In this squelch detector, memorizer memory devices the most according to claim 6, wherein judges that this secondary signal string is
The no operation for this wake-up signal includes:
This squelch detector judges whether this secondary signal string includes m burst, and wherein m is positive integer；
If this secondary signal string includes m burst, this squelch detector judges that this secondary signal string is this wake-up signal.
11. memorizer memory devices according to claim 6, wherein this burst detector includes:
One low-power squelch detector；And
One squelch detector control circuit, is coupled to this low-power squelch detector,
This squelch detector includes；
One squelch detecting circuit, is coupled to this squelch detector control circuit；And
One frequency external signal decision circuitry, is coupled to this squelch detecting circuit and this state controller,
Wherein, this low-power squelch detector is in order to receive this first signal in the case of this squelch detecting circuit is pent
String, and under this first operation frequency, judge whether this first train of signal includes this burst,
If this first train of signal includes this burst, this squelch detector control circuit in order to start this squelch detecting circuit,
After this squelch detecting circuit is actuated to, this squelch detecting circuit in order to detect under this second operation frequency this second
One second burst in train of signal and a blank signal, and this frequency external signal decision circuitry is in order to according to this second burst
Signal and this blank signal judge whether this secondary signal string is this wake-up signal.
12. 1 kinds of adapters, it is characterised in that this adapter includes:
One state controller；
One squelch detector, is coupled to this state controller；And
One burst detector, is coupled to this squelch detector, in order to receive one the in the case of this squelch detector is pent
One train of signal, and under one first operation frequency, judge whether this first train of signal includes a burst,
Wherein, if this first train of signal includes this burst, this burst detector starts this squelch detector,
After this squelch detector is actuated to, this squelch detector is in order to judge a secondary signal under one second operation frequency
String whether be a wake-up signal, wherein this secondary signal string be received in this first train of signal after, and this second operation
Frequency is more than this first operation frequency,
If this secondary signal string is this wake-up signal, this state controller is to open in order to change a mode of operation of this adapter
Dynamic state.
13. adapters according to claim 12, if wherein this secondary signal string is not this wake-up signal, this burst detects
Device, also in order to cut out this squelch detector, receives one the 3rd signal, and judges whether the 3rd signal includes this burst.
14. adapters according to claim 12, wherein this burst detector judge under this first operation frequency this
Whether one train of signal includes that the operation of this burst includes:
This burst detector judges whether this first train of signal includes that length is more than or equal to n unit under this first operation frequency
An interval subsignal, wherein n is the positive integer more than or equal to 2；
If this first train of signal includes this subsignal, this squelch detector judges that this first train of signal includes this burst.
15. adapters according to claim 14, wherein this positive integer n is 5.
In this squelch detector, 16. adapters according to claim 12, wherein judge whether this secondary signal string is this
The operation of wake-up signal includes:
This squelch detector judges whether this secondary signal string includes m burst, and wherein m is positive integer；
If this secondary signal string includes m burst, this squelch detector judges that this secondary signal string is this wake-up signal.
17. adapters according to claim 12, wherein this burst detector includes:
One low-power squelch detector；And
One squelch detector control circuit, is coupled to this low-power squelch detector,
This squelch detector includes:
One squelch detecting circuit, is coupled to this squelch detector control circuit；And
One frequency external signal decision circuitry, is coupled to this squelch detecting circuit and this state controller,
Wherein, this low-power squelch detector is in order to receive this first signal in the case of this squelch detecting circuit is pent
String, and under this first operation frequency, judge whether this first train of signal includes this burst,
If this first train of signal includes this burst, this squelch detector control circuit in order to start this squelch detecting circuit,
After this squelch detecting circuit is actuated to, this squelch detecting circuit in order to detect under this second operation frequency this second
One second burst in train of signal and a blank signal, and this frequency external signal decision circuitry is in order to according to this second burst
Signal and this blank signal judge whether this secondary signal string is this wake-up signal.
18. 1 kinds of adapters, meet a Serial Advanced Technology Attachment standard, it is characterised in that this adapter includes:
One low frequency signal detector；
One signal detector control circuit, is coupled to this low frequency signal detector；
One high-frequency detector, is coupled to this signal detector control circuit；
One high-frequency signal decision circuitry, is coupled to this high-frequency detector；
One state controller, is coupled to this signal detector control circuit and this high-frequency signal decision circuitry,
Wherein, this low frequency signal detector in order in the case of this high-frequency detector is pent receive one first train of signal, and
And under one first operation frequency, judge whether this first train of signal includes one first signal model,
If this first train of signal includes this first signal model, this signal detector control circuit is in order to start this high-frequency detection
Device,
After this high-frequency detector is actuated to, this high-frequency detector is in order to detect a secondary signal under one second operation frequency
Whether string includes a secondary signal model, wherein this secondary signal string be received in this first train of signal after, and this
Two operation frequencies are more than this first operation frequency, and this first signal model is different from this secondary signal model,
If this secondary signal string includes this secondary signal model, this state controller is in order to change a mode of operation of this adapter
It it is a starting state.
19. adapters according to claim 18, wherein this first operation frequency is not more than the one of this second operation frequency
Half.
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| CN201210405185.5A CN103777732B (en) | 2012-10-22 | 2012-10-22 | The control method of adapter, adapter and memorizer memory devices |
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| CN201210405185.5A CN103777732B (en) | 2012-10-22 | 2012-10-22 | The control method of adapter, adapter and memorizer memory devices |
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Cited By (1)
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| CN108702704A (en) * | 2017-03-02 | 2018-10-23 | 华为技术有限公司 | A kind of method and apparatus of wake on wireless equipment |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105227404B (en) * | 2015-10-13 | 2019-04-09 | 英特格灵芯片(天津)有限公司 | A kind of method and device thereof of detection data transmission |
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| US5881101A (en) * | 1994-09-01 | 1999-03-09 | Harris Corporation | Burst serial tone waveform signaling method and device for squelch/wake-up control of an HF transceiver |
| CN1653406A (en) * | 2002-03-14 | 2005-08-10 | 英特尔公司 | Methods and apparatus for reducing power usage of a transmitter and receiver coupled via a differential serial data link |
| CN102124454A (en) * | 2008-08-21 | 2011-07-13 | 高通股份有限公司 | Universal serial bus (usb) remote wakeup |
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