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Publication numberCN103701307 A
Publication typeApplication
Application numberCN 201310751101
Publication date2 Apr 2014
Filing date31 Dec 2013
Priority date31 Dec 2013
Also published asCN103701307B, US9312771, US20150188434
Publication number201310751101.8, CN 103701307 A, CN 103701307A, CN 201310751101, CN-A-103701307, CN103701307 A, CN103701307A, CN201310751101, CN201310751101.8
Inventors欧阳茜
Applicant成都芯源系统有限公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Single inductance multi-output buck converter as well as control circuit and control method of single inductance multi-output buck converter
CN 103701307 A
Abstract
The invention discloses a single inductance multi-output buck converter as well as a control circuit and a control method of the single inductance multi-output buck converter. The control method comprises the steps of comparing a first feedback signal with a first reference signal and generating a first comparing signal; comparing a second feedback signal with a second reference signal and generating a second comparing signal; if the appearance of the first comparing signal is earlier than that of the second comparing signal, conducting a first switch tube, disconnecting a second switch tube, conducting a third switch tube, disconnecting a fourth switch tube, and disconnecting the first switch tube and conducting the second switch tube when the conducting time of the first switch tube achieves a first time threshold value; if the appearance of the second comparing signal is earlier than the first comparing signal, conducting the first switch tube, disconnecting the second switch tube, disconnecting the third switch tube, conducting the fourth switch tube and disconnecting the first switch tube and conducting the second switch tube when the conducting time of the first switch tube achieves a second time threshold value.
Claims(16)  translated from Chinese
1.一种单电感多输出降压变换器的控制方法,该单电感多输出降压变换器包括具有第一端和第二端的电感器、耦接在输入电压与电感器第一端之间的第一开关管、耦接在电感器第一端与参考地之间的第二开关管、耦接在电感器第二端与第一输出电压之间的第三开关管、耦接在电感器第二端与第二输出电压之间的第四开关管、耦接在第一输出电压与参考地之间的第一电容器、以及耦接在第二输出电压与参考地之间的第二电容器,该控制方法包括: 基于第一输出电压,产生第一反馈信号; 基于第二输出电压,产生第二反馈信号; 将第一反馈信号与第一参考信号进行比较,产生第一比较信号; 将第二反馈信号与第二参考信号进行比较,产生第二比较信号; 判断第一比较信号和第二比较信号中何者较先出现; 若第一比较信号的出现早于第二比较信号,将第一开关管导通,第二开关管关断,第三开关管导通,第四开关管关断,并在第一开关管的导通时间达到第一时间阈值时,将第一开关管关断,第二开关管导通; 若第二比较信号的出现早于第一比较信号,将第一开关管导通,第二开关管关断,第三开关管关断,第四开关管导通,并在第一开关管的导通时间达到第二时间阈值时,将第一开关管关断,第二开关管导通。 1. A method for controlling a single multi-output inductor buck converter, the single multiple-output buck converter comprises an inductor having a first end and a second end of the inductor, coupled between the input voltage and a first end of the inductor a first switch, a second switch coupled at a first end of the inductor and the reference ground, the third switch coupled to the second end of the inductor and the first output voltage between the coupled inductor The second end of the tube with the fourth switch between the second output voltage, is coupled between the first output voltage to a reference ground of the first capacitor, and coupled between the second output voltage and a second reference ground capacitor, the control method comprising: based on a first output voltage to generate a first feedback signal; based on a second output voltage to generate a second feedback signal; the first feedback signal is compared with a first reference signal to generate a first comparison signal; The second feedback signal is compared with a second reference signal to generate a second comparison signal; determining a first comparison signal and the second comparison signal in whichever first occurs; occurs when the first comparison signal is earlier than the second comparison signal, The first switch is turned on, the second switch is turned off, the switch turns on the third and fourth switch off, and the first time to reach the threshold of the first switch conduction time, the first switch off, the second switch is turned on; if the second comparison signal occurs earlier than the first comparison signal, the first switch is turned on, the second switch off, switch off the third, and the fourth switch tube conduction, and a second time to reach the threshold of the first switch conduction time, the first switch off, the second switch is turned on.
2.如权利要求1所述的控制方法,其中在第一开关管关断时,方对第一比较信号和第二比较信号中何者较先出现进行判断。 2. The control method according to claim 1, wherein when the first switch off, side of the first comparison signal and the second comparison signal in whichever first occurs is judged.
3.如权利要求1所述`的控制方法,还包括: 对第一开关管的关断时间进行计时,在第一开关管的关断时间达到最小关断时间阈值后方可将第一开关管导通。 3. The method of controlling a `claim, further comprising: a first switch off-time tube for a time, during the off-time of the first switch off-time to a minimum threshold value before the first switch tube conduction.
4.如权利要求1所述的控制方法,还包括: 将流过电感器的电流与电流限值进行比较,在流过电感器的电流小于电流限值时方可将第一开关管导通。 The control method according to claim 1, further comprising: a current flowing through the inductor and the current limit by comparing the current flowing through the inductor is less than the current limit value before the first switch is turned on .
5.如权利要求1所述的控制方法,其中单电感多输出降压变换器中的第二开关管被二极管代替。 The control method according to claim 1, wherein the single inductor multiple output buck converter in a second switch is a diode instead.
6.一种单电感多输出降压变换器的控制电路,该单电感多输出降压变换器包括具有第一端和第二端的电感器、耦接在输入电压与电感器第一端之间的第一开关管、耦接在电感器第一端与参考地之间的第二开关管、耦接在电感器第二端与第一输出电压之间的第三开关管、耦接在电感器第二端与第二输出电压之间的第四开关管、耦接在第一输出电压与参考地之间的第一电容器、以及耦接在第二输出电压与参考地之间的第二电容器,该控制电路包括: 第一比较电路,具有第一输入端、第二输入端和输出端,其中第一输入端接收代表第一输出电压的第一反馈信号,第二输入端接收第一参考信号,第一比较电路将第一反馈信号与第一参考信号进行比较,在输出端产生第一比较信号; 第二比较电路,具有第一输入端、第二输入端和输出端,其中第一输入端接收代表第二输出电压的第一反馈信号,第二输入端接收第二参考信号,第二比较电路将第二反馈信号与第二参考信号进行比较,在输出端产生第二比较信号;逻辑电路,耦接至第一比较电路和第二比较电路的输出端,基于第一比较信号和第二比较信号产生第一驱动信号、第二驱动信号、第三驱动信号和第四驱动信号以分别控制第一开关管、第二开关管、第三开关管和第四开关管; 其中逻辑电路判断第一比较信号和第二比较信号中何者较先出现,若第一比较信号的出现早于第二比较信号,则逻辑电路将第一开关管导通,第二开关管关断,第三开关管导通,第四开关管关断,并在第一开关管的导通时间达到第一时间阈值时,将第一开关管关断,第二开关管导通;若第二比较信号的出现早于第一比较信号,则逻辑电路将第一开关管导通,第二开关管关断,第三开关管关断,第四开关管导通,并在第一开关管的导通时间达到第二时间阈值时,将第一开关管关断,第二开关管导通。 A single inductor multiple output buck converter control circuit, the single multiple-output buck converter comprises an inductor having a first end and a second end of the inductor, coupled between the input voltage and a first end of the inductor a first switch, a second switch coupled at a first end of the inductor and the reference ground, the third switch coupled to the second end of the inductor and the first output voltage between the coupled inductor The second end of the tube with the fourth switch between the second output voltage, is coupled between the first output voltage to a reference ground of the first capacitor, and coupled between the second output voltage and a second reference ground capacitor, the control circuit comprising: a first comparator circuit having a first input, a second input terminal and an output terminal, wherein a first input for receiving a first feedback signal representative of a first output voltage, a second input terminal for receiving a first reference signal, a first comparator circuit of the first feedback signal is compared with a first reference signal to generate a first comparison signal at an output terminal; a second comparator circuit having a first input, a second input terminal and an output terminal, wherein the first a first input for receiving a feedback signal representing a second output voltage, a second input terminal receiving a second reference signal, the second comparison circuit a second feedback signal is compared with a second reference signal to generate a second comparison signal at the output ; logic circuit, coupled to the output terminal of the first comparator circuit and the second comparison circuit, generating a first drive signal based on the first comparison signal and the second comparison signal, a second driving signal, the third driving signal and a fourth driving signal to control the first switch, the second switch, the third switch and the fourth switch tube; wherein the logic circuit judge of the first comparison signal and the second signal in comparison whichever first occurs, if there is a first comparison signal early in the second comparison signal, the logic circuit of the first switch is turned on, the second switch is turned off, the third switch turns on, and the fourth switch off and reach first at the first switch on-time When a time threshold, the first switch off, the second switch is turned on; if the second comparison signal occurs earlier than the first comparison signal, the logic circuit of the first switch is turned on, the second switch off off, switch off the third and fourth switch turns on, and the second time to reach the threshold at the time of the first switch is turned on when the first switch is turned off, the second switch is turned on.
7.如权利要求6所述的控制电路,其中所述逻辑电路包括: 判断电路,具有第一输入端、第二输入端和输出端,其中第一输入端稱接至第一比较电路的输出端以接收第一比较信号,第二输入端耦接至第二比较电路的输出端以接收第二比较信号,判断电路检测第一比较信号和第二比较信号中何者较先出现,在输出端产生判断信号; 选择电路,具有第一输入端、第二输入端、第三输入端和输出端,其中第一输入端接收第一时间阈值,第二输入端接收第二时间阈值,第三输入端耦接至判断电路的输出端以接收判断信号,选择电路基于判断信号,将第一时间阈值或者第二时间阈值作为导通时间阈值提供至输出端; 导通时间控制电路,具有输入端和输出端,其中输入端耦接至选择电路的输出端以接收导通时间阈值,导通时间控制电路基于导通时间阈值,在输出端产生导通时间控制信号; 逻辑门电路,具有第一输入端、第二输入端和输出端,其中第一输入端I禹接至第一比较电路的输出端以接收第一比较信号,第二输入端耦接至第二比较电路的输出端以接收第二比较信号,逻辑门电路基于第一比较信号和第二比较信号,在输出端产生门输出信号; 触发电路,具有第一输入端、第二输入端和输出端,其中第一输入端耦接至导通时间控制电路的输出端以接收导通时间控制信号,第二输入端耦接至逻辑门电路的输出端以接收门输出信号,触发电路基于导通时间控制信号和门输出信号,在输出端产生开关控制信号; 第一驱动电路,具有输入端、第一输出端和第二输出端,其中输入端I禹接至触发电路的输出端以接收开关控制信号,第一驱动电路基于开关控制信号,在第一输出端和第二输出端分别产生第一驱动信号和第二驱动信号; 第二驱动电路,具有输入端、第一输出端和第二输出端,其中输入端耦接至判断电路的输出端以接收判断信号,第二驱动电路基于判断信号,在第一输出端和第二输出端分别产生第三驱动信号和第四驱动信号。 The control circuit of claim 6, wherein said logic circuit comprises: judging circuit having a first input, a second input terminal and an output terminal, wherein said first input coupled to the output of the first comparator circuit terminal for receiving a first comparison signal, a second input terminal coupled to the second output terminal of the comparator circuit to receive the second comparison signal, the detection circuit determines the first comparison signal and the second comparison signal in whichever first occurs at the output generates a judgment signal; selecting circuit having a first input, a second input terminal, a third input terminal and an output terminal, wherein a first input for receiving a first time threshold, a second input terminal for receiving a second time threshold value, a third input terminal coupled to the decision circuit output terminal to receive the discrimination signal, the selection circuit based on the determination signal, the first time threshold or the second time threshold as the turn-on time threshold value is supplied to an output terminal; on-time control circuit, having an input and output terminal, wherein the input terminal is coupled to the selection circuit output terminal to receive the on-time thresholds, on-time control circuit is based on turn-on time threshold value, at the output on-time control signal; logic gate circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal connected to the first I Yu comparator circuit output terminal for receiving a first comparison signal, a second input terminal coupled to the second output terminal of the comparator circuit to receive the first two comparison signal, a logic gate circuit based on the first comparison signal and the second comparison signal, generated at the output of the gate output signal; trigger circuit having a first input, a second input terminal and an output terminal, wherein the first input is coupled to the on-time control circuit to receive the output of on-time control signal, a second input terminal coupled to the output terminal of the logic gate to receive the gate output signal, the control signal and the gate trigger circuit output signal based on on-time, in generating a switch control signal output terminal; a first driving circuit having an input terminal, a first output terminal and a second output, wherein the input terminal I Yu connected to the output of flip-flop circuit for receiving the switch control signal, the first driving circuit based on a switching control signals, respectively generated at the first output terminal and a second output terminal of the first driving signal and a second driving signal; a second driving circuit, having an input terminal, a first output terminal and a second output, wherein the input terminal is coupled to determination circuit for receiving the output of the determination signal, the second driving circuit based on the determination signal, respectively, to generate a third driving signal and a fourth driving signal at a first output terminal and a second output.
8.如权利要求7所述的控制电路,其中判断电路还耦接至触发电路的输出端以接收开关控制信号,并基于开关控制信号,在第一开关管关断时,方对第一比较信号和第二比较信号中何者较先出现进行判断。 The control circuit 7 and the switch control signal based on when the first switch is off, the first side of the comparison claim, wherein the decision circuit is also coupled to the output terminal of the flip-flop to receive the switch control signal, signal and the second signal in comparison whichever first occurs judge.
9.如权利要求6所述的控制电路,还包括: 最小关断时间控制电路,产生控制第一开关管最小关断时间的最小关断时间控制信号; 其中触发电路还耦接至最小关断时间控制电路以接收最小关断时间控制信号,并基于门输出信号、最小关断时间控制信号和导通时长控制信号产生开关控制信号。 9. The control circuit of claim 6, further comprising: minimum off-time control circuit for generating a first switch controlling the minimum turn-off time of the minimum off-time control signal; wherein the trigger circuit is also coupled to the minimum off time control circuit to receive the minimum off-time control signal, and an output signal based on the gate length control signal when the switching control signal generating minimum off-time control signal and turned on.
10.如权利要求6所述的控制电路,还包括: 限流电路,具有第一输入端,第二输入端和输出端,其中第一输入端接收流过电感器的电流,第二输入端接收电流限值,限流电路将流过电感器的电流与电流限值进行比较,在输出端产生限流信号; 其中触发电路还耦接至限流电路以接收限流信号,并基于门输出信号、限流信号和导通时长控制信号产生开关控制信号。 10. The control circuit of claim 6, further comprising: a current limiting circuit having a first input, a second input terminal and an output terminal, wherein the first input terminal for receiving current flowing through the inductor, a second input terminal receiving current limit circuit will limit the current flowing through the inductor and the current limit by comparing the signal generated at the output of the current limiting; wherein the trigger circuit is also coupled to a current limiting circuit to limit the reception signal, based on the gate output signal, limiting long-control signal and switch control signal conduction signal generation.
11.如权利要求6所述的控制电路,其中单电感多输出降压变换器中的第二开关管被二极管代替。 11. The control circuit of claim 6, wherein the single inductor multiple output buck converter in a second switch is a diode instead.
12.一种单电感多输出降压变换器,包括: 电感器,具有第一端和第二端; 第一开关管,稱接在输入电压与电感器第一端之间; 第二开关管,耦接在电感器第一端与参考地之间; 第三开关管,耦接在电感器第二端与第一输出电压之间; 第四开关管,耦接在电感器第二端与第二输出电压之间; 第一电容器,稱接在第一输出电压与参考地之间; 第二电容器,稱接在第二输出电压与参考地之间; 第一反馈电路,具有输入端和输出端,其中输入端接收第一输出电压,第一反馈电路基于第一输出电压,在输出端产生代表第一输出电压的第一反馈信号; 第二反馈电路,具有输入端和输出端,其中输入端接收第二输出电压,第二反馈电路基于第二输出电压,在输出端产生代表第二输出电压的第二反馈信号;以及如权利要求6至11中任一项所述的控制电路。 12. A single inductor multiple output buck converter, comprising: an inductor having a first end and a second end; a first switch, connected to said input voltage between the first end of the inductor; second switch tube , coupled between a first end of the inductor and the reference ground; third switch coupled between the second end of the inductor and the first output voltage; fourth switch tube, coupled between the second end of the inductor and between the second output voltage; a first capacitor connected between said first output voltage to a reference ground; second capacitor, connected between said second output voltage to a reference ground; a first feedback circuit, having an input and output terminal, wherein the input for receiving the first output voltage, a first feedback circuit based on a first output voltage at the output terminal to produce a first output representative of a first voltage feedback signal; a second feedback circuit having an input terminal and an output terminal, wherein a second input terminal receiving the output voltage, a second feedback circuit based on a second output voltage at the output of the second output voltage representative of a second feedback signal; and a control circuit 6 to 11 in any one of claims.
13.如权利要求12所述的单电感多输出降压变换器,还包括: 第三电容器,耦接电感器的第二端与参考地之间。 Single inductor 13. The multiple output buck converter according to claim 12, further comprising: between the third capacitor, coupled to the second end of the inductor and the reference ground.
14.一种单电感多输出降压变换器的控制电路,该单电感多输出降压变换器包括具有第一端和第二端的电感器、耦接在输入电压与电感器第一端之间的第一开关管、耦接在电感器第一端与参考地之间的第二开关管、分别耦接在电感器第二端与多个输出电压之间的多个输出开关管、以及分别I禹接在多个输出电压与参考地之间的多个电容器,该控制电路包括: 多个比较电路,产生多个比较信号,其中每个比较电路将代表相应输出电压的反馈信号与相应参考信号进行比较,以产生相应比较信号; 逻辑电路,耦接至多个比较电路,基于多个比较信号控制第一开关管、第二开关管和多个输出开关管; 其中逻辑电路判断多个比较信号中何者较先出现,若某个比较信号的出现早于其余比较信号,则逻辑电路将与该较早出现的比较信号对应的输出开关管导通,将其余输出开关管关断,并将第一开关管导通,第二开关管关断,在第一开关管的导通时间达到相应时间阈值时,逻辑电路将第一开关管关断,第二开关管导通。 14. A single inductor multiple output buck converter control circuit, the single multiple-output buck converter comprises an inductor having a first end and a second end of the inductor, coupled between the input voltage and a first end of the inductor a first switch coupled between the first end of the inductor and the reference ground of the second switch, respectively, coupled between the second end of the inductor and the plurality of output voltages of a plurality of output switch, respectively, and I Yu plurality of outputs connected to the plurality of capacitors between the voltage and the reference ground, the control circuit comprising: a plurality of comparator circuit which generates a plurality of comparison signals, each of which represents the corresponding comparison circuit compares the output voltage feedback signal and the corresponding reference signals are compared to generate a corresponding comparison signal; logic circuit, coupled to a plurality of comparator circuits, a plurality of comparison signals based on a first control switch, the second switch and a plurality of output switch; wherein the logic circuit determines a plurality of comparison signals in whichever first occurs, if there is a comparison signal earlier than the rest of the comparison signal, the logic circuit and the earlier onset of the comparison signal corresponding output switch turns on, the rest of the output switch off, and the first A switch turns on, the second switch is turned off, the time to reach the corresponding threshold conduction time of the first switch tube, the logic circuit of the first switch off, the second switch is turned on.
15.如权利要求14所述的控制电路,其中单电感多输出降压变换器中的第二开关管被二极管代替。 15. The control circuit of claim 14, wherein the single inductor multiple output buck converter in a second switch is a diode instead.
16.—种单电感多输出降压变换器,包括: 电感器,具有第一端和第二端; 第一开关管,稱接在输入电压与电感器第一端之间; 第二开关管,耦接在电感器第一端与参考地之间; 多个输出开关管,分别耦接在电感器第二端与多个输出电压之间; 多个电容器,分别稱接在多个输出电压与参考地之间; 多个反馈电路,分别基于多个输出电压,产生多个反馈信号;以及如权利要求14或15所述的控制电路。 16.- kinds single inductor multiple output buck converter, comprising: an inductor having a first end and a second end; a first switch, connected between said input voltage and a first end of the inductor; second switch tube , coupled between a first end of the inductor and the reference ground; a plurality of output switch, respectively, coupled between the second end of the inductor and the plurality of output voltages; a plurality of capacitors, respectively, said plurality of output voltages connected between the reference ground and; a plurality of feedback circuits, respectively, based on a plurality of output voltage to generate a plurality of feedback signals; and a control circuit 14 or 15 according to claim.
Description  translated from Chinese

单电感多输出降压变换器及其控制电路和控制方法 Single inductor multiple-output buck converter and its control circuit and control method

技术领域 FIELD

[0001 ] 本发明的实施例涉及电子电路,尤其涉及单电感多输出降压变换器及其控制电路和控制方法。 EXAMPLES [0001] The present invention relates to electronic circuits, and more particularly relates to a single inductor and the buck converter output control circuit and control method.

背景技术 BACKGROUND

[0002] 许多系统,例如电脑主板,需要多个母线电压,譬如3.3V和2V。 [0002] Many systems, such as computer motherboards, requiring multiple bus voltage, such as 3.3V and 2V. 传统的做法是对每个母线电压均使用单独的降压变换器,每个降压变换器均包括集成控制电路、两个开关管、电感器、输出电容器和其他辅助元器件。 The traditional approach is to use the single buck converter for each bus voltage, each buck converter includes integrated control circuit, two switches, inductor and output capacitor and other auxiliary components. 这些元件,尤其是电感器,需要耗费大量成本。 These components, particularly the inductor, requires a lot of cost. 为此,人们一直在需求一种结构更简单、成本更低廉的多输出解决方案。 For this reason, it has been in demand for a structure more simple, cheaper and more output solutions.

发明内容 SUMMARY

[0003] 本发明要解决的技术问题是提供结构简单、成本低廉的单电感多输出降压变换器及其控制器和控制方法。 [0003] The present invention to solve the technical problem is to provide a simple structure, low cost single-inductor multiple-output buck converter and controller and method.

[0004] 根据本发明实施例的一种单电感多输出降压变换器的控制方法,该单电感多输出降压变换器包括具有第一端和第二端的电感器、耦接在输入电压与电感器第一端之间的第一开关管、耦接在电感器第一端与参考地之间的第二开关管、耦接在电感器第二端与第一输出电压之间的第三开关管、耦接在电感器第二端与第二输出电压之间的第四开关管、耦接在第一输出电压与参考地之间的第一电容器、以及I禹接在第二输出电压与参考地之间的第二电容器,该控制方法包括:基于第一输出电压,产生第一反馈信号;基于第二输出电压,产生第二反馈信号;将第一反馈信号与第一参考信号进行比较,产生第一比较信号;将第二反馈信号与第二参考信号进行比较,产生第二比较信号;判断第一比较信号和第二比较信号中何者较先出现;若第一比较信号的出现早于第二比较信号,将第一开关管导通,第二开关管关断,第三开关管导通,第四开关管关断,并在第一开关管的导通时间达到第一时间阈值时,将第一开关管关断,第二开关管导通;若第二比较信号的出现早于第一比较信号,将第一开关管导通,第二开关管关断,第三开关管关断,第四开关管导通,并在第一开关管的导通时间达到第二时间阈值时,将第一开关管关断,第二开关管导通。 [0004] The control method according to an embodiment of the present invention is a single-inductor multiple output buck converter, the single multiple-output buck converter comprises an inductor having a first end and a second end of the inductor, coupled with the input voltage a first switch between a first end of the inductor, a second switch coupled between the first end of the inductor and the reference ground, and coupled between the second end of the inductor and the first output voltage of the third switch, the fourth switch is coupled a second end of the inductor and the second output voltage is coupled between the first output voltage to a reference ground of the first capacitor, and I connected to the second output voltage Yu and a second capacitor between the ground reference, the method comprising: based on a first output voltage to generate a first feedback signal; based on a second output voltage to generate a second feedback signal; a first feedback signal and the first reference signal comparison, generating a first comparison signal; the second feedback signal is compared with a second reference signal to generate a second comparison signal; determining a first comparison signal and the second comparison signal in whichever first occurs; occurs when the first comparison signal Early in the second comparison signal, the first switch is turned on, the second switch is turned off, the switch turns on the third and fourth switch off, and reached the first time in the on-time of the first switch tube threshold, the first switch off, the second switch MOSFET; If there is a second comparison signal earlier than the first comparison signal, the first switch is turned on, the second switch is turned off, the third switch off, and the fourth switch turns on, and the second time to reach the threshold at the time of the first switch is turned on when the first switch is turned off, the second switch is turned on.

[0005] 根据本发明实施例的一种单电感多输出降压变换器的控制电路,该单电感多输出降压变换器包括具有第一端和第二端的电感器、耦接在输入电压与电感器第一端之间的第一开关管、耦接在电感器第一端与参考地之间的第二开关管、耦接在电感器第二端与第一输出电压之间的第三开关管、耦接在电感器第二端与第二输出电压之间的第四开关管、耦接在第一输出电压与参考地之间的第一电容器、以及I禹接在第二输出电压与参考地之间的第二电容器,该控制电路包括:第一比较电路,具有第一输入端、第二输入端和输出端,其中第一输入端接收代表第一输出电压的第一反馈信号,第二输入端接收第一参考信号,第一比较电路将第一反馈信号与第一参考信号进行比较,在输出端产生第一比较信号;第二比较电路,具有第一输入端、第二输入端和输出端,其中第一输入端接收代表第二输出电压的第一反馈信号,第二输入端接收第二参考信号,第二比较电路将第二反馈信号与第二参考信号进行比较,在输出端产生第二比较信号;逻辑电路,耦接至第一比较电路和第二比较电路的输出端,基于第一比较信号和第二比较信号产生第一驱动信号、第二驱动信号、第三驱动信号和第四驱动信号以分别控制第一开关管、第二开关管、第三开关管和第四开关管;其中逻辑电路判断第一比较信号和第二比较信号中何者较先出现,若第一比较信号的出现早于第二比较信号,则逻辑电路将第一开关管导通,第二开关管关断,第三开关管导通,第四开关管关断,并在第一开关管的导通时间达到第一时间阈值时,将第一开关管关断,第二开关管导通;若第二比较信号的出现早于第一比较信号,则逻辑电路将第一开关管导通,第二开关管关断,第三开关管关断,第四开关管导通,并在第一开关管的导通时间达到第二时间阈值时,将第一开关管关断,第二开关管导通。 [0005] According to one single inductor multiple output buck converter control circuit of the embodiment of the present invention, the single multiple-output buck converter comprises an inductor having a first end and a second end of the inductor, coupled with the input voltage a first switch between a first end of the inductor, a second switch coupled between the first end of the inductor and the reference ground, and coupled between the second end of the inductor and the first output voltage of the third switch, the fourth switch is coupled a second end of the inductor and the second output voltage is coupled between the first output voltage to a reference ground of the first capacitor, and I connected to the second output voltage Yu and a second capacitor between the ground reference, the control circuit comprising: a first comparator circuit having a first input, a second input terminal and an output terminal, wherein a first input for receiving a first feedback signal representative of a first output voltage , a second input terminal for receiving a first reference signal, a first comparator circuit of the first feedback signal is compared with a first reference signal to generate a first comparison signal at an output terminal; a second comparator circuit having a first input, a second input terminal and an output terminal, wherein a first input for receiving a first feedback signal representative of a second output voltage, a second input terminal receiving a second reference signal, the second comparison circuit a second feedback signal is compared with a second reference signal, generating at the output a second comparison signal; logic circuit, coupled to the output terminal of the first comparator circuit and the second comparison circuit, generating a first drive signal based on the first comparison signal and the second comparison signal, a second driving signal, the first three drive signal and the fourth drive signals to control the first switch, the second switch, the third switch and the fourth switch tube; wherein the logic circuit judge of the first comparison signal and the second signal in comparison whichever first occurs, If there is a first comparison signal earlier than the second comparison signal, the logic circuit of the first switch is turned on, the second switch is turned off, the switch turns on the third and fourth switch off, and the first When the switch conduction time to reach the first time threshold, the first switch is turned off, the second switch is turned on; if the second comparison signal occurs earlier than the first comparison signal, the logic circuit of the first switch When turned on, the second switch off, switch off the third and fourth switch turns on, and the second time to reach the threshold of the first switch on-time, the first switch off, the first two switch conduction.

[0006] 根据本发明实施例的一种单电感多输出降压变换器,包括:电感器,具有第一端和第二端;第一开关管,耦接在输入电压与电感器第一端之间;第二开关管,耦接在电感器第一端与参考地之间;第三开关管,耦接在电感器第二端与第一输出电压之间;第四开关管,I禹接在电感器第二端与第二输出电压之间;第一电容器,I禹接在第一输出电压与参考地之间;第二电容器,耦接在第二输出电压与参考地之间;第一反馈电路,具有输入端和输出端,其中输入端接收第一输出电压,第一反馈电路基于第一输出电压,在输出端产生代表第一输出电压的第一反馈信号;第二反馈电路,具有输入端和输出端,其中输入端接收第二输出电压,第二反馈电路基于第二输出电压,在输出端产生代表第二输出电压的第二反馈信号;以及如前所述的控制电路。 [0006] According to one single multi-output buck converter inductor embodiment of the present invention, comprises: an inductor having a first end and a second end; a first switch coupled at a first end of the input voltage and the inductor between; a second switch, coupled between a first end of the inductor and the reference ground; third switch coupled between the second end of the inductor and the first output voltage; fourth switch tube, I Yu connected between the second end of the inductor and the second output voltage; a first capacitor, I Yu connected between the first output voltage to a reference ground; a second capacitor coupled between the second output voltage with a reference ground; a first feedback circuit having an input terminal and an output terminal, wherein the input for receiving the first output voltage, a first feedback circuit based on a first output voltage at the output terminal to produce a first output representative of a first voltage feedback signal; a second feedback circuit having an input end and an output end, wherein the input for receiving the second output voltage, a second feedback circuit based on a second output voltage to generate a second output representative of a second voltage feedback signal at an output terminal; and a control circuit as previously described .

[0007] 根据本发明实施例的一种单电感多输出降压变换器的控制电路,该单电感多输出降压变换器包括具有第一端和第二端的电感器、耦接在输入电压与电感器第一端之间的第一开关管、耦接在电感器第一端与参考地之间的第二开关管、分别耦接在电感器第二端与多个输出电压之间的多个输出开关管、以及分别耦接在多个输出电压与参考地之间的多个电容器,该控制电路包括:多个比较电路,产生多个比较信号,其中每个比较电路将代表相应输出电压的反馈信号与相应参考信号进行比较,以产生相应比较信号;逻辑电路,耦接至多个比较电路,基于多个比较信号控制第一开关管、第二开关管和多个输出开关管;其中逻辑电路判断多个比较信号中何者较先出现,若某个比较信号的出现早于其余比较信号,则逻辑电路将与该较早出现的比较信号对应的输出开关管导通,将其余输出开关管关断,并将第一开关管导通,第二开关管关断,在第一开关管的导通时间达到相应时间阈值时,逻辑电路将第一开关管关断,第二开关管导通。 [0007] According to one single inductor multiple output buck converter control circuit of the embodiment of the present invention, the single multiple-output buck converter comprises an inductor having a first end and a second end of the inductor, coupled with the input voltage a first switch between a first end of the inductor, a second switch coupled between the first end of the inductor and the reference ground, and are coupled between the second end of the inductor and the output voltage of the plurality of multi- an output transistor switch, and are respectively coupled between the plurality of the output voltage to a reference ground of the plurality of capacitors, the control circuit comprising: a plurality of comparator circuit which generates a plurality of comparison signals, each of which represents the corresponding comparison circuit the output voltage The feedback signal is compared with the corresponding reference signal, to generate a corresponding comparison signal; logic circuit, coupled to a plurality of comparator circuits, a plurality of comparison signals based on a first control switch, the second switch and a plurality of output switch; wherein the logic circuit judge multiple comparison signals whichever first occurs, if a comparison signal occurs earlier than the rest of the comparison signal, the logic circuit will appear in the earlier comparison signal corresponding output switch turns on, the rest of the output switch off, and the first switch is turned on, the second switch off, to achieve the appropriate time threshold at the time of the first switch is turned on when the logic circuit of the first switch off, the second switch is turned on .

[0008] 根据本发明的实施例的一种单电感多输出降压变换器,包括:电感器,具有第一端和第二端;第一开关管,耦接在输入电压与电感器第一端之间;第二开关管,耦接在电感器第一端与参考地之间;多个输出开关管,分别I禹接在电感器第二端与多个输出电压之间;多个电容器,分别I禹接在多个输出电压与参考地之间;多个反馈电路,分别基于多个输出电压,产生多个反馈信号;以及如前所述的控制电路。 [0008] According to a one embodiment of the present invention the inductor multiple output buck converter, comprising: an inductor having a first end and a second end; a first switch coupled at a first input voltage and inductor between the ends; a second switch, coupled between a first end of the inductor and the reference ground; a plurality of output switch, respectively, I Yu connected between the second end of the inductor and a plurality of output voltages; a plurality of capacitors , respectively connected between the plurality of I Yu output voltage with a reference ground; a plurality of feedback circuits, respectively, based on the plurality of output voltages to produce a plurality of feedback signals; and a control circuit as previously described.

[0009] 根据本发明的实施例的单电感多输出降压变换器与现有技术相比,仅需一个电感器和一个控制电路,极大地减少了元器件数量,降低了成本。 [0009] Compared with the prior art single-inductor according to an embodiment of the present invention, multiple output buck converter, only an inductor and a control circuit, which greatly reduces the number of components, reduces costs. 此外,直接基于反馈信号与参考信号的比较结果来控制开关管,使得该单电感多输出降压变换器在任一输出电压发生变化时均能给出及时有效的响应。 In addition, a direct comparison of the results based on the feedback signal and the reference signal to control the switch so that the single-inductor multiple-output buck converter can at any given timely and effective response when an output voltage changes. 附图说明 Brief Description

[0010] 图1为根据本发明一实施例的单电感多输出降压变换器100的框图; [0010] Figure 1 is a block diagram of a multiple output buck converter 100 according to an embodiment of the present invention, a single inductor embodiment;

[0011] 图2为根据本发明一实施例的图1所示单电感多输出降压变换器100的工作状态图; [0011] FIG. 2 is a diagram of an embodiment of the invention shown in the single inductor multiple output buck converter 100 of the state diagram;

[0012] 图3为根据本发明一实施例的图1所示逻辑电路113的框图; [0012] FIG. 3 is a block diagram of logic circuit 113 shown in FIG. 1 according to an embodiment of the present invention;

[0013] 图4为根据本发明一实施例的单电感多输出降压变换器400的电路原理图; [0013] Figure 4 is a multi-output inductor according to an embodiment of the present invention, a single embodiment of the buck converter circuit diagram 400;

[0014] 图5为根据本发明一实施例的图4所示逻辑电路413的电路原理图; [0014] FIG. 5 is a logic circuit 413. The circuit schematic shown in Figure 4 according to an embodiment of the present invention;

[0015] 图6为根据本发明一实施例的单电感多输出降压变换器400的工作波形图; [0015] Figure 6 is a multiple-output single-inductor according to an embodiment of the invention a waveform diagram of a buck converter 400;

[0016] 图7为根据本发明一实施例的单电感多输出降压变换器700的框图。 [0016] FIG. 7 is a block diagram 700 in accordance with a single inductor multiple output buck converter of an embodiment of the invention.

具体实施方式 DETAILED DESCRIPTION

[0017] 下面将详细描述本发明的具体实施例,应当注意,这里描述的实施例只用于举例说明,并不用于限制本发明。 [0017] Specific embodiments of the present invention will be described in detail, it should be noted that the embodiments described herein are only illustrative and not intended to limit the present invention. 在以下描述中,为了提供对本发明的透彻理解,阐述了大量特定细节。 In the following description, in order to provide a thorough understanding of the present invention, numerous specific details are set forth. 然而,对于本领域普通技术人员显而易见的是,不必采用这些特定细节来实行本发明。 However, those of ordinary skill in apparent that specific details need not be employed to practice the present invention. 在其他实例中,为了避免混淆本发明,未具体描述公知的电路、材料或方法。 In other instances, in order to avoid obscuring the present invention, not specifically described well-known circuits, materials or methods.

[0018] 在整个说明书中,对“ 一个实施例”、“实施例”、“ 一个示例”或“示例”的提及意味着:结合该实施例或示例描述的特定特征、结构或特性被包含在本发明至少一个实施例中。 [0018] Throughout the specification to "one embodiment", "an embodiment", "one example" or "an example" means that: a particular feature of the embodiment or example described, structure, or characteristic is included In at least one embodiment of the present invention embodiment. 因此,在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。 Therefore, in various places throughout the specification appears the phrase "in one embodiment", "in an embodiment", "an example" or "sample" not necessarily all referring to the same embodiment or example. 此外,可以以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。 Further, in any suitable combinations and / or sub-combination to combine the particular features, structures or characteristics in one or more embodiments or examples. 此外,本领域普通技术人员应当理解,在此提供的附图都是为了说明的目的,并且附图不一定是按比例绘制的。 Furthermore, those of ordinary skill will understand, the drawings are provided herein for purposes of illustration, and drawings are not necessarily drawn to scale. 应当理解,当称“元件” “连接到”或“耦接”到另一元件时,它可以是直接连接或耦接到另一元件或者可以存在中间元件。 It should be understood that when "element", "connected to" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. 相反,当称元件“直接连接到”或“直接耦接到”另一元件时,不存在中间元件。 In contrast, when element "directly connected to" or "directly coupled to" another element, there are no intervening elements. 相同的附图标记指示相同的元件。 The same reference numerals indicate like elements. 这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。 As used herein, the term "and / or" includes any and all combinations of one or more related items listed.

[0019] 图1为根据本发明一实施例的单电感多输出降压变换器100的框图。 [0019] Figure 1 is a block diagram of a multiple output buck converter 100 according to an embodiment of the present invention, a single inductor embodiment. 该单电感多输出降压变换器100包括电感器L1、第一开关管S1、第二开关管S2、第三开关管S3、第四开关管S4、第一电容器Cl、第二电容器C2、控制电路101、第一反馈电路102和第二反馈电路103。 This single inductor multiple output buck converter 100 includes an inductor L1, a first switch S1, the second switch S2, third switch tube S3, the fourth switch tube S4, the first capacitor Cl, a second capacitor C2, the control circuit 101, a first feedback circuit 102 and second feedback circuit 103. 电感器LI具有第一端和第二端。 LI inductor having a first end and a second end. 第一开关管SI f禹接在输入电压Vin与电感器LI的第一端之间。 A first switch SI f Yu coupled between the input voltage Vin and the first end of the inductor LI. 第二开关管S2耦接在电感器LI的第一端与参考地之间。 The second switch S2 is coupled between the inductor LI a first terminal and a reference ground. 第三开关管S3耦接在电感器LI的第二端与第一输出电压Voutl之间。 The third switch S3 is coupled between the second end of the inductor LI and the first output voltage Voutl. 第四开关管S4耦接在电感器LI的第二端与第二输出电压Vout2之间。 The fourth switch S4 is coupled between the second end of the inductor LI and the second output voltage Vout2. 第一电容器Cl f禹接在第一输出电压Voutl和参考地之间,第二电容器C2耦接在第二输出电压Vout2和参考地之间。 Yu first capacitor Cl f connected between the first output voltage Voutl and reference ground, a second capacitor C2 is coupled between the second output voltage Vout2 and reference ground. 根据图1可知,当第三开关管S3导通、第四开关管S4关断时,第一开关管S1、第二开关管S2、第三开关管S3、电感器LI和第一电容器Cl 一起构成第一降压变换器(BUCK1),对第一输出电压Voutl进行调节。 According to Figure 1 shows that, when the third switch S3 is turned on, when the fourth switch S4 is turned off, the first switch S1, the second switch S2, third switch S3, the inductor LI and the first capacitor Cl together constituting the first buck converter (BUCK1), the first output voltage Voutl adjusted. 当第三开关管S3关断、第四开关管S4导通时,第一开关管S1、第二开关管S2、第四开关管S4、电感器LI和第二电容器C2 —起构成第二降压变换器(BUCK2),对第二输出电压Vout2进行调节。 When the third switch S3 is turned off, the fourth switch S4 is turned on, the first switch S1, the second switch S2, the fourth switch S4, the inductor LI and the second capacitor C2 - constituting the second drop from Pressure transducer (BUCK2), the second output voltage Vout2 be adjusted.

[0020] 第一反馈电路102具有输入端和输出端,其中输入端接收第一输出电压Voutl。 [0020] The first feedback circuit 102 having an input end and an output end, wherein a first input for receiving the output voltage Voutl. 第一反馈电路102基于第一输出电压Voutl,在输出端产生代表第一输出电压Voutl的第一反馈信号FBI。 A first feedback circuit 102 based on a first output voltage Voutl, at the output represents a first output voltage Voutl of a first feedback signal FBI. 第二反馈电路103具有输入端和输出端,其中输入端接收第二输出电压Vout2。 The second feedback circuit 103 having an input end and an output end, wherein the input for receiving the second output voltage Vout2. 第二反馈电路103基于第二输出电压Vout2,在输出端产生代表第二输出电压Vout2的第二反馈信号FB2。 The second feedback circuit 103 based on the second output voltage Vout2, at the output represents the second output voltage Vout2 of the second feedback signal FB2. 第一反馈电路102和第二反馈电路103均可以用电阻分压器实现,也可以仅包括用于反馈的导线。 A first feedback circuit 102 and second feedback circuit 103 can be realized with a resistor divider, may also include only wire for feedback. 在后一种情况下,第一反馈信号FBl等于第一输出电压Voutl,第二反馈信号FB2等于第二输出电压Vout2。 In the latter case, the first feedback signal FBl equal to the first output voltage Voutl, a second feedback signal FB2 equal to the second output voltage Vout2.

[0021] 控制电路101包括第一比较电路111、第二比较电路112以及逻辑电路113。 [0021] The control circuit 101 includes a first comparator circuit 111, a second comparator circuit 112 and a logic circuit 113. 第一比较电路111具有第一输入端、第二输入端和输出端,其中第一输入端稱接至第一反馈电路102以接收第一反馈信号FB1,第二输入端接收第一参考信号Refl。 A first comparator circuit 111 having a first input, a second input terminal and an output terminal, wherein said first input terminal connected to the first feedback circuit 102 for receiving a first feedback signal FB1, a second input terminal for receiving a first reference signal Refl . 第一比较电路111将第一反馈信号FB与第一参考信号Refl进行比较,在输出端产生第一比较信号Buckl_Set。 The first comparison circuit 111 of the first feedback signal FB with the first reference signal is compared Refl, at the output of the first comparison signal Buckl_Set. 第二比较电路112具有第一输入端、第二输入端和输出端,其中第一输入端稱接至第二反馈电路103以接收第二反馈信号FB2,第二输入端接收第二参考信号Ref2。 The second comparator circuit 112 having a first input, a second input terminal and an output terminal, wherein said first input terminal connected to the second feedback circuit 103 to receive the second feedback signal FB2, a second input terminal for receiving a second reference signal Ref2 . 第二比较电路112将第二反馈信号FB与第二参考信号Ref2进行比较,在输出端产生第二比较信号Buck2—Set。 The second comparator circuit 112 and the second feedback signal FB comparing the second reference signal Ref2, at the output of the second comparison signal Buck2-Set.

[0022] 逻辑电路113耦接至第一比较电路111和第二比较电路112的输出端,基于第一比较信号Buckl_Set和第二比较信号Buck2_Set产生第一驱动信号DRV1、第二驱动信号DRV2、第三驱动信号DRV3和第四驱动信号DRV4,以分别控制第一开关管S1、第二开关管S2、第三开关管S3和第四开关管S4。 [0022] The logic circuit 113 is coupled to the output terminal of the first comparator circuit 111 and the second comparator circuit 112, to generate a first drive signal DRV1 Buckl_Set based on the first comparison signal and the second comparison signal Buck2_Set, the second drive signal DRV2, the first three drive signal DRV3 and fourth drive signal DRV4, to control the first switch S1, the second switch S2, S3 and the third switch tube fourth switch S4.

[0023] 若第一比较信号Buckl_Set的出现早于第二比较信号Buck2_Set,即第一反馈信号FBl减小至第一参考信号Refl的时刻早于第二反馈信号FB2减小至第二参考信号Ref2的时刻,则第一降压变换器工作而第二降压变换器不工作。 [0023] If a first comparison signal Buckl_Set appears earlier than the second comparison signal Buck2_Set, i.e., the first feedback signal is reduced to a first reference signal FBl timing earlier Refl reduced to the second feedback signal FB2 to the second reference signal Ref2 moment, the first buck converter is operating and the second buck converter is not working. 逻辑电路113将第一开关管SI导通,第二开关管S2关断,第三开关管S3导通,第四开关管S4关断,并在第一开关管SI的导通时间达到第一时间阈值TONl时,将第一开关管S2关断,第二开关管S3导通。 A first logic circuit 113 will switch SI is turned on, the second switch S2 is turned off, the third switch S3 is turned on, the fourth switch S4 is turned off and the first switch tube reaches a first conduction time of SI When the time threshold TONl, the first switch S2 is turned off, the second switch S3 is turned on. 第一时间阈值TONl可被设置为恒定值,也可被设置为与输入电压Vin和/或第一输出电压Voutl有关的可变值。 TONl first time threshold may be set to a constant value, or may be set to a variable value of the input voltage Vin and / or the first output voltage Voutl related.

[0024] 若第二比较信号Buck2_Set的出现早于第一比较信号Buckl_Set,即第二反馈信号FB2减小至第二参考信号Ref2的时刻早于第一反馈信号FBl减小至第一参考信号Refl的时刻,则第一降压变换器不工作而第二降压变换器工作。 [0024] If the second comparison signal Buck2_Set appears earlier than the first comparison signal Buckl_Set, i.e., the second feedback signal FB2 is reduced to a second timing reference signal Ref2 is reduced earlier than the first feedback signal to a first reference signal Refl FBl moment, the first buck converter is not working and the second buck converter is operating. 逻辑电路113将第一开关管SI导通,第二开关管S2关断,第三开关管S3关断,第四开关管S4导通,并在第一开关管SI的导通时间达到第二时间阈值T0N2时,将第一开关管S2关断,第二开关管S3导通。 A first logic circuit 113 will switch SI is turned on, the second switch S2 is turned off, the third switch S3 is turned off, the fourth switch S4 is turned on, and the first switch SI reaches the second conduction time When the time threshold T0N2, the first switch S2 is turned off, the second switch S3 is turned on. 第二时间阈值T0N2可被设置为恒定值,也可被设置为与输入电压Vin和/或第二输出电压Vout2有关的可变值。 T0N2 second time threshold may be set to a constant value, or may be set to the input voltage Vin and / or the second output voltage Vout2 variable value associated.

[0025] 以下结合图2对图1所示单电感多输出降压变换器100的工作过程作进一步说明。 [0025] FIG. 2 below in conjunction with FIG. 1 shows a single inductor multiple output buck converter 100 of the working process is further illustrated. 图2为根据本发明一实施例的图1所示单电感多输出降压变换器100的工作状态图,包括状态S201〜S205。 Figure 2 is a diagram of an embodiment of the invention shown in the single inductor multiple output buck converter operation state diagram 100, including status S201~S205.

[0026] 在状态S201,单电感多输出降压变换器100启动,开关管SI〜S4均关断,第一降压变换器和第二降压变换器均不工作。 [0026] In state S201, single-inductor multiple-output buck converter 100 is started, the switch SI~S4 are turned off, the first and second buck converter buck converter not working. 此时,若检测到第一比较信号Buckl_Set的出现早于第二比较信号Buck2_Set,则进入状态S202。 At this time, if the detection of the first comparison signal Buckl_Set appears earlier than the second comparison signal Buck2_Set, the process proceeds to state S202. 若检测到第二比较信号Buck2_Set的出现早于第一比较信号Buckl_Set,则进入状态S204。 Occurs if the second comparison signal Buck2_Set detected earlier than the first comparison signal Buckl_Set, the process proceeds to state S204. [0027] 在状态S202,第一降压变换器工作而第二降压变换器不工作,第一开关管SI和第三开关管S3被导通,第二开关管S2和第四开关管S4被关断。 [0027] In state S202, the first buck converter is operating and the second buck converter is not working, the first switch SI and the third switch S3 is turned on, the second switch S2 and the fourth switch S4 is turned off. 此外,第一开关管SI的导通时间被计时。 Further, the first switch SI conduction time is clocked. 当第一开关管SI的导通时间达到第一时间阈值TONl时,单电感多输出降压变换器100进入状态S203。 When the first switch SI conduction time to reach the first time threshold TONl, single-inductor multiple-output buck converter 100 into the state S203.

[0028] 在状态S203,第一降压变换器工作而第二降压变换器不工作,第一开关管S2被关断,第二开关管S3被导通,第三开关管S3维持导通,第四开关管S4维持关断。 [0028] In state S203, the first buck converter is operating and the second buck converter is not working, the first switch S2 is turned off, the second switch S3 is turned on, the third switch S3 is maintained in the ON fourth switch S4 maintain off. 在状态S203下,若检测到第一比较信号Buckl_Set的出现早于第二比较信号Buck2_Set,则重新进入状态S202。 In state S203, if the detection of the first comparison signal Buckl_Set appears earlier than the second comparison signal Buck2_Set, then re-enter the state S202. 若检测到第二比较信号Buck2_Set的出现早于第一比较信号Buckl_Set,则进入状态S204。 Occurs if the second comparison signal Buck2_Set detected earlier than the first comparison signal Buckl_Set, the process proceeds to state S204.

[0029] 在状态S204,第一降压变换器不工作而第二降压变换器工作,第一开关管SI和第四开关管S4被导通,第二开关管S2和第三开关管S3被关断。 [0029] In state S204, the first buck converter is not working and the second buck converter is operating, the first switch SI and the fourth switch S4 is turned on, the second switch S2 and the third switch S3 is turned off. 此外,第一开关管SI的导通时间被计时。 Further, the first switch SI conduction time is clocked. 当第一开关管SI的导通时间达到第二时间阈值T0N2时,单电感多输出降压变换器100进入状态S205。 When the first switch SI conduction time reaches the second time threshold T0N2, single inductor multiple output buck converter 100 into the state S205.

[0030] 状态S205,第一降压变换器不工作而第二降压变换器工作,第一开关管SI被关断,第二开关管S2被导通,第三开关管S3维持关断,第四开关管S4维持导通。 [0030] State S205, the first buck converter is not working and the second buck converter is operating, the first switch SI is turned off, the second switch S2 is turned on, the third switch S3 is maintained off, The fourth switch S4 to maintain conduction. 在状态S205下,若检测到第一比较信号Buckl_Set的出现早于第二比较信号Buck2_Set,则进入状态S202。 In state S205, if the detection of the first comparison signal Buckl_Set appears earlier than the second comparison signal Buck2_Set, the process proceeds to state S202. 若检测到第二比较信号Buck2_Set的出现早于第一比较信号Buckl_Set,则重新进入状态S204。 Occurs if the second comparison signal Buck2_Set detected earlier than the first comparison signal Buckl_Set, then re-enter the state S204.

[0031] 在一个实施例中,为了避免噪声干扰导致第一开关管SI刚被关断,立刻又被导通,第一开关管Si的关断时间被计时。 [0031] In one embodiment, in order to avoid noise interference causes the first switch SI has just been turned off, and immediately they are turned on, the first switch off time Si timed. 只有在第一开关管SI的关断时间达到最小关断时间阈值后,第一开关管Si方可被导通。 Only after the minimum off-time threshold in the first SI switch off time, before the first switch is turned on Si. 在一个实施例中,为了防止电感电流过流,流过电感器LI的电流IL被用于与电流限值Ilim进行比较,只有在电流IL小于电流限值Ilim时,第一开关管SI方可被导通。 In one embodiment, in order to prevent over-current inductor current, flowing through the inductor current IL LI is used to compare with the current limit Ilim, only the current IL is less than the current limit Ilim, the first switch SI before is turned on.

[0032] 如图2所不,基于第一比较信号Buckl_Set和第二比较信号Buck2_Set,第一降压变换器和第二降压变换器分时工作,从而实现对第一输出电压Voutl和第二输出电压Vout2的调节。 [0032] FIG. 2 is not based on the first comparison signal and the second comparison signal Buckl_Set Buck2_Set, the first buck converter and the second buck converter time-sharing, in order to achieve a first and a second output voltage Voutl regulation of the output voltage Vout2.

[0033] 图3为根据本发明一实施例的图1所示逻辑电路113的框图。 [0033] FIG. 3 is a block diagram of logic circuit 113 shown in FIG. 1 according to an embodiment of the present invention. 逻辑电路113包括选择电路1131、导通时间控制电路1132、逻辑门电路1133、触发电路1134、第一驱动电路1135、判断电路1136和第二驱动电路1137。 Logic circuit 113 includes a selection circuit 1131, on-time control circuit 1132, a logic gate circuit 1133, the flip-flop 1134, a first driving circuit 1135, judgment circuit 1136 and the second drive circuit 1137.

[0034] 判断电路1136具有第一输入端、第二输入端和输出端,其中第一输入端耦接至第一比较电路的输出端以接收第一比较信号Buckl_Set,第二输入端耦接至第二比较电路的输出端以接收第二比较信号Buck2_Set。 [0034] The judgment circuit 1136 having a first input, a second input terminal and an output terminal, wherein the first input coupled to the output of the first comparator circuit for receiving a first comparison signal Buckl_Set, a second input terminal coupled to output of the second comparison circuit to receive the second comparison signal Buck2_Set. 判断电路1136判断第一比较信号Buckl_Set和第二比较信号Buck2_Set中何者较先出现,在输出端产生判断信号JDG。 Judging circuit 1136 determines the first comparison signal and the second comparison signal Buck2_Set Buckl_Set in whichever first occurs, the signal at the output generates a judgment JDG. 在一个实施例中,判断电路1136还耦接至触发电路1134的输出端以接收开关控制信号PWM,并基于开关控制信号PWM,在第一开关管SI关断时,方对第一比较信号Buckl_Set和第二比较信号Buck2_Set中何者较先出现进行判断。 In one embodiment, the determining circuit 1136 is also coupled to the output of flip-flop circuit 1134 to receive the switch control signal PWM, and the switch control signal PWM, the first switch SI is turned off based on the side of the first comparison signal Buckl_Set and a second comparison signal Buck2_Set whichever first occurs in judgment.

[0035] 选择电路1131具有第一输入端、第二输入端、第三输入端和输出端,其中第一输入端接收第一时间阈值T0N1,第二输入端接收第二时间阈值T0N2,第三输入端耦接至判断电路1136的输出端以接收判断信号JDG。 [0035] The selection circuit 1131 having a first input, a second input terminal, a third input terminal and an output terminal, wherein a first input for receiving a first time threshold T0N1, a second input terminal for receiving a second time threshold T0N2, third an input terminal coupled to the output of the decision circuit 1136 for receiving the determination signal JDG. 选择电路1131基于判断信号JDG,将第一时间阈值TONl或者第二时间阈值T0N2作为导通时间阈值TON提供至输出端。 Selection circuit 1131 based on the determination signal JDG, the first time or the second time threshold TONl threshold T0N2 as a threshold conduction time TON provided to the output.

[0036] 导通时间控制电路1132具有输入端和输出端,其中输入端耦接至选择电路1131的输出端以接收导通时间阈值TON。 [0036] on-time control circuit 1132 having an input and an output, wherein the input terminal is coupled to the output of the selection circuit 1131 to receive the on-time threshold TON. 导通时间控制电路1132基于导通时间阈值Τ0Ν,在输出端产生导通时间控制信号C0T。 On-time control circuit 1132 based on on-time threshold Τ0Ν, at the output control signal conduction time C0T.

[0037] 逻辑门电路1133具有第一输入端、第二输入端和输出端,其中第一输入端耦接至第一比较电路的输出端以接收第一比较信号Buckl_Set,第二输入端耦接至第二比较电路的输出端以接收第二比较信号Buck2_Set。 [0037] The logic gate circuit 1133 has a first input, a second input terminal and an output terminal, wherein the first input coupled to the output of the first comparator circuit for receiving a first comparison signal Buckl_Set, a second input terminal coupled to to the second output terminal of the comparator circuit to receive the second comparison signal Buck2_Set. 逻辑门电路1133基于第一比较信号Buckl_Set和第二比较信号Buck2_Set,在输出端产生门输出信号SET。 The logic gate circuit 1133 based on the first comparison signal and the second comparison signal Buckl_Set Buck2_Set, at the output gate output signal SET.

[0038] 触发电路1134具有第一输入端、第二输入端和输出端,其中第一输入端稱接至导通时间控制电路1132的输出端以接收导通时间控制信号C0T,第二输入端耦接至逻辑门电路1133的输出端以接收门输出信号SET。 [0038] trigger circuit 1134 having a first input, a second input terminal and an output terminal, wherein said first input terminal connected to the on-time control circuit 1132. The output of on-time to receive the control signal C0T, a second input terminal coupled to the logic gate output terminal 1133 to receive the gate output signal SET. 触发电路1134基于导通时间控制信号COT和门输出信号SET,在输出端产生开关控制信号PWM。 Trigger circuit 1134 based on-time control signal and the gate output signal COT SET, at the output switch control signal PWM.

[0039] 第一驱动电路1135具有输入端、第一输出端和第二输出端,其中输入端耦接至触发电路1134的输出端以接收开关控制信号PWM。 [0039] The first driving circuit 1135 has an input terminal, a first output terminal and a second output, wherein the input terminal is coupled to the output terminal of the flip-flop 1134 to receive the switch control signal PWM. 第一驱动电路1135基于开关控制信号PWM,在第一输出端和第二输出端分别产生第一驱动信号DRVl和第二驱动信号DRV2。 A first drive circuit 1135 based on the switch control signal PWM, to generate a first drive signal and second drive signals DRV2 DRVl at a first output terminal and a second output.

[0040] 第二驱动电路1137具有输入端、第一输出端和第二输出端,其中输入端耦接至判断电路1136的输出端以接收判断信号JDG。 [0040] The second driver circuit 1137 has an input terminal, a first output terminal and a second output, wherein the input terminal is coupled to the output terminal of the judgment circuit 1136 for receiving the determination signal JDG. 第二驱动电路1137基于判断信号JDG,在第一输出端和第二输出端分别产生第三驱动信号DRV3和第四驱动信号DRV4。 Second drive circuit 1137 based on the determination signal JDG, at a first output and a second output terminal, respectively, for generating a third driving signal and the fourth driving signal DRV3 DRV4.

[0041 ] 当判断电路1136检测到第一比较信号Buckl_Set的出现早于第二比较信号Buck2_Set时,在判断信号JDG的作用下,选择电路1131选择第一时间阈值TONl作为导通时间阈值Τ0Ν,第二驱动电路1137将第三开关管S3导通,第四开关管S4关断。 [0041] When judging circuit 1136 appears first comparison signal Buckl_Set detected earlier than the second comparison signal Buck2_Set when it is determined that the role of the signal JDG, the selection circuit 1131 selects the first time as a turn-on threshold TONl time threshold Τ0Ν, first two drive circuit 1137 and the third switch S3 is turned on, and the fourth switch S4 is turned off. 同时,触发电路1134被触发,第一驱动电路1135将第一开关管SI导通,第二开关管S2关断,直至第一开关管SI的导通时间达到第一时间阈值TONl。 Meanwhile, the trigger circuit 1134 is triggered, the first driving circuit 1135 of the first switch SI is turned on, the second switch S2 is turned off, until the first switch SI conduction time reaches a first time threshold TONl.

[0042] 当判断电路1136检测到第二比较信号Buck2_Set的出现早于第一比较信号Buckl_Set时,在判断信号JDG的作用下,选择电路1131选择第二时间阈值T0N2作为导通时间阈值Τ0Ν,第二驱动电路1137将第三开关管S3关断,第四开关管S4导通。 [0042] When judging circuit 1136 appears Buck2_Set the second comparison signal is detected earlier than the first comparison signal Buckl_Set when it is determined under the effect of the signal JDG, the selection circuit 1131 selects the second time as the turn-on threshold T0N2 time threshold Τ0Ν, first two drive circuit 1137 and the third switch S3 is turned off, and the fourth switch S4 is turned on. 同时,触发电路1134被触发,第一驱动电路1135将第一开关管SI导通,第二开关管S2关断,直至第一开关管SI的导通时间达到第二时间阈值T0N2。 Meanwhile, the trigger circuit 1134 is triggered, the first driving circuit 1135 of the first switch SI is turned on, the second switch S2 is turned off, until the first switch SI conduction time reaches the second time threshold T0N2.

[0043] 在一个实施例中,逻辑电路113还包括最小关断时间控制电路1139,最小关断时间控制电路1139产生控制第一开关管SI最小关断时间的最小关断时间控制信号Μ0Τ。 [0043] In one embodiment, the logic circuit 113 also includes a minimum off-time control circuit 1139, the minimum off-time control circuit 1139 generates the control of the first switch SI minimum off-time of the minimum off-time control signal Μ0Τ. 触发电路1134接收最小关断时间控制信号Μ0Τ,并基于门输出信号SET、导通时长控制信号COT和最小关断时间控制信号MOT产生开关控制信号PWM。 Trigger circuit 1134 receives the minimum off-time control signal Μ0Τ, and generate PWM switching control signal based on the gate output signal SET, length control signal conduction COT and minimum off-time control signal MOT.

[0044] 在一个实施例中,逻辑电路113还包括限流电路1138,以限制流过电感器LI的电流。 [0044] In one embodiment, the logic circuit 113 also includes a current limiting circuit 1138, to limit the flow of current through the inductor LI. 限流电路1138具有第一输入端,第二输入端和输出端,其中第一输入端接收流过电感器的电流IL,第二输入端接收电流限值Ilim。 Current limiting circuit 1138 has a first input, a second input terminal and an output terminal, wherein the first input terminal for receiving a current IL flowing through the inductor, and a second input terminal for receiving current limit Ilim. 限流电路1138将电流IL与电流限值Ilim进行比较,在输出端产生限流信号LMT。 The current limiting circuit 1138 and the current limit Ilim IL compare at the output current limiting signal LMT. 触发电路1134接收限流信号LMT,并基于门输出信号SET、导通时长控制信号C0T、最小关断时间控制信号MOT和限流信号LMT产生开关控制信号PWM。 Trigger circuit 1134 receives the limiting signal LMT, and the gate output signal based on SET, length control signal is turned on C0T, minimum off-time control signal MOT and the current-limit signal LMT switching control signal generating PWM.

[0045] 图4为根据本发明一实施例的单电感多输出降压变换器400的电路原理图。 [0045] Figure 4 is a circuit diagram 400 in accordance with a single inductor multiple output buck converter of an embodiment of the invention. 与图I所示变换器100相比,单电感多输出降压变换器400还包括耦接在电感器LI的第二端与参考地之间的第三电容器C3。 I converter 100 shown in FIG compared single inductor multiple output buck converter 400 further comprises coupled between the second end of the inductor LI and the reference ground of the third capacitor C3. 在图4所示的实施例中,开关管SI〜S4为N型MOSFET,第一比较电路411和第二比较电路412分别包括比较器COMl和COM2,第一反馈电路402和第二反馈电路403均包括电阻分压器。 In the embodiment shown in Figure 4, the switch SI~S4 N-type MOSFET, the first comparison circuit 411 and the second comparator circuit 412 includes a comparator COMl respectively and COM2, the first feedback circuit 402 and second feedback circuit 403 comprises a resistor divider. 为了防止两输出电压短路,开关管S3和S4均包括与其体二极管串联反向串联的二极管。 In order to prevent short-circuit between the output voltage, the switch S3 and S4 are connected in series including a reverse diode connected in series with its body diode.

[0046] 图5为根据本发明一实施例的图4所示逻辑电路413的电路原理图。 [0046] FIG. 5 is a logic circuit in Figure 4 an embodiment of the invention of the circuit diagram 413. 其中选择电路4131包括开关管S6和S7。 Wherein the selection circuit 4131 includes switches S6 and S7. 开关管S6和S7均具有第一端、第二端和控制端。 S6 and S7 switch having a first end, a second end and a control terminal. 开关管S6第一端耦接至第一输出电压Voutl,开关管S7的第一端耦接至第二输出电压Vout2。 Switch S6 is coupled to a first end of a first output voltage Voutl, switch S7 is coupled to a first end connected to the second output voltage Vout2. 开关管S6和S7的控制端接收判断信号JDG。 Switch S6 and S7 control terminal receives the judgment signal JDG. 导通时间控制电路4132包括电流源IS1、开关管S5、电容器C4和比较器COM3。 On-time control circuit 4132 includes a current source IS1, switch S5, capacitor C4 and a comparator COM3. 电流源ISl具有输入端和输出端,其中输入端耦接至输入电压Vin。 ISl current source having an input and an output, wherein the input terminal is coupled to the input voltage Vin. 开关管S5具有第一端、第二端和控制端,其中第一端耦接至电流源ISl的输出端,第二端耦接至参考地,控制端接收开关控制信号PWM。 Switch S5 has a first end, a second end and a control terminal, wherein the first end is coupled to the output terminal of the current source ISl a second end coupled to ground reference, control terminal for receiving the switch control signal PWM. 电容器C4具有第一端和第二端,其中第一端耦接至电流源ISl的输出端,第二端耦接至参考地。 Capacitor C4 having a first end and a second end, wherein the first end is coupled to the output terminal of the current source ISl a second end coupled to ground reference. 比较器COM3具有同相输入端、反相输入端和输出端,其中同相输入端耦接至电容器C4的第一端,反相输入端耦接至开关管S6和S7的第二端,输出端提供导通时间控制信号C0T。 The comparator COM3 has a non-inverting input, an inverting input terminal and an output terminal, wherein the noninverting input terminal coupled to the first end of capacitor C4, and an inverting input terminal coupled to the second end of the switch S6 and S7, the output providing on-time control signal C0T.

[0047] 判断电路4136包括与门AND2、AND3、非门NOTl以及触发器FF2。 [0047] judging circuit 4136 includes an AND gate AND2, AND3, and NAND gate NOTl triggers FF2. 非门NOTl具有输入端和输出端,其中输入端接收开关控制信号PWM。 NOTl having an input NAND gate and an output, wherein the input terminal for receiving the switch control signal PWM. 与门AND2具有第一输入端、第二输入端和输出端,其中第一输入端接收第一比较信号Buckl_Set,第二输入端I禹接至非门NOTl的输出端。 The AND gate AND2 having a first input, a second input terminal and an output terminal, wherein the first input terminal for receiving a first comparison signal Buckl_Set, a second input terminal connected to the output terminal I Yu NOTl of the NAND gate. 与门AND3具有第一输入端、第二输入端和输出端,其中第一输入端I禹接至非门NOTl的输出端,第二输入端接收第二比较信号Buck2_Set。 The AND gate AND3 having a first input, a second input terminal and an output terminal, wherein the first input terminal connected to the output terminal I Yu NOTl of the NAND gate, a second input terminal receiving a second comparison signal Buck2_Set. 触发器FF2具有置位端、复位端和输出端,其中置位端耦接至与门AND2的输出端,复位端耦接至与门AND3的输出端,输出端提供判断信号JDG。 Flip-flop FF2 has a set terminal, a reset terminal and an output terminal, wherein the set terminal coupled to the output of AND gate AND2, and a reset terminal coupled to the output terminal, the output of AND gate AND3 provider determination signal JDG. 逻辑门电路4133包括或门0R1。 4133 includes a logic gate or door 0R1. 或门ORl具有第一输入端、第二输入端和输出端,其中第一输入端I禹接至与门AND2的输出端,第二输入端I禹接至与门AND3的输出端,输出端提供门输出信号SET。 OR gate ORl having a first input, a second input terminal and an output terminal, wherein the first input terminal connected to the I Yu output of AND gate AND2, and a second input terminal connected to the I Yu output of AND gate AND3 and the output terminal provide gate output signal SET.

[0048] 限流电路4138包括比较器COM4。 [0048] The current limiting circuit 4138 includes a comparator COM4. 比较器COM4具有同相输入端、反相输入端和输出端,其中同相输入端接收阈值电压Vth,反相输入端接收代表流过电感器电流IL的电流采样信号Isense,输出端提供限流信号LMT。 The comparator COM4 has a non-inverting input, an inverting input terminal and an output terminal, wherein the noninverting input receives a threshold voltage Vth, the inverting input receiving represents the current sampling signal Isense, the output of the inductor current IL provides current limiting signal LMT . 触发电路4134包括触发器FFl以及与门AND1。 4134 includes a flip-flop circuit FFl and AND gate AND1. 与门ANDl具有第一输入端、第二输入端、第三输入端和输出端,其中第一输入端I禹接至限流电路4138以接收限流信号LMT,第二输入端耦接至逻辑门电路4133以接收门输出信号SET,第三输入端耦接至最小关断时间控制电路4139以接收最小关断时间控制信号Μ0Τ。 ANDl AND gate having a first input, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal connected to the I Yu current limiting circuit 4138 to receive a current limiting signal LMT, a second input terminal coupled to the logic gate circuit 4133 to receive the gate output signal SET, a third input terminal coupled to the minimum off-time control circuit 4139 to receive a minimum off-time control signal Μ0Τ. 触发器FFl具有置位端、复位端和输出端,其中置位端耦接至与门ANDl的输出端,复位端耦接至导通时间控制电路4132以接收导通时间控制信号C0T,输出端提供开关控制信号PWM。 Flip-flop FFl having a set terminal, a reset terminal and an output terminal, wherein the set terminal coupled to the output of AND gate ANDl, the reset terminal coupled to the on-time control circuit 4132 to receive the on-time control signal C0T, an output terminal provides a switching control signal PWM.

[0049] 第一驱动电路4135具有输入端、第一输出端和第二输出端,其中输入端耦接至触发电路4134的输出端以接收开关控制信号PWM。 [0049] The first driving circuit 4135 has an input terminal, a first output terminal and a second output, wherein the input terminal is coupled to the output terminal of the flip-flop 4134 to receive the switch control signal PWM. 第一驱动电路4135基于开关控制信号PWM,在第一输出端和第二输出端分别产生第一驱动信号DRVl和第二驱动信号DRV2。 A first drive circuit 4135 based on the switch control signal PWM, to generate a first drive signal and second drive signals DRV2 DRVl at a first output terminal and a second output.

[0050] 第二驱动电路4137具有输入端、第一输出端和第二输出端,其中输入端耦接至判断电路4136的输出端以接收判断信号JDG。 [0050] The second driver circuit 4137 has an input terminal, a first output terminal and a second output, wherein the input terminal is coupled to the output terminal of the judgment circuit 4136 for receiving the determination signal JDG. 第二驱动电路4137基于判断信号JDG,在第一输出端和第二输出端分别产生第三驱动信号DRV3和第四驱动信号DRV4。 Second drive circuit 4137 based on the determination signal JDG, at a first output and a second output terminal, respectively, for generating a third driving signal and the fourth driving signal DRV3 DRV4.

[0051 ] 当判断电路4136检测到第一比较信号Buckl_Set的出现早于第二比较信号Buck2_Set时,触发器FF2被置位,判断信号JDG为高电平。 [0051] When judging circuit 4136 detects the first comparison signal Buckl_Set appears earlier than the second comparison signal Buck2_Set, the flip-flop FF2 is set, the determination signal JDG is high. 第二驱动电路4137将第三开关管S3导通,第四开关管S4关断。 The second driver circuit 4137 and the third switch S3 is turned on, and the fourth switch S4 is turned off. 同时,开关管S6被导通,开关管S7被关断,第一输出电压Voutl被送入比较器COM3的反相输入端。 At the same time, the switch S6 is turned on, and the switch S7 is turned off, the first output voltage Voutl is fed into the inverting input terminal of the comparator COM3. 导通时间控制电路4132基于输入电压Vin和第一输出电压Voutl产生具有第一时间阈值TONl的导通时间控制信号COT。 On-time control circuit 4132 based on the input voltage Vin and the output voltage Voutl generating a first on-time with a first time threshold TONl control signal COT. 此外,触发器FFl被置位,开关控制信号PWM为高电平,第一驱动电路4135将第一开关管SI导通,第二开关管S2关断,直至第一开关管SI的导通时间达到第一时间阈值TONl。 In addition, the flip-flop FFl is controlled to set the switching signal PWM is high, the first driving circuit 4135 of the first switch SI is turned on, the second switch S2 is turned off, until the first switch SI conduction time reaches a first time threshold TONl.

[0052] 当判断电路4136检测到第二比较信号Buck2_Set的出现早于第一比较信号Buckl_Set时,触发器FF2被复位,判断信号JDG为低电平。 [0052] When judging circuit 4136 detects the second comparison signal Buck2_Set appears earlier than the first comparison signal Buckl_Set, the flip-flop FF2 is reset, the determination signal JDG low. 第二驱动电路4137将第三开关管S3关断,第四开关管S4导通。 The second driver circuit 4137 and the third switch S3 is turned off, and the fourth switch S4 is turned on. 同时,开关管S6被关断,开关管S7被导通,第二输出电压Vout2被送入比较器COM3的反相输入端。 At the same time, the switch S6 is turned off, and the switch S7 is turned on, the second output voltage Vout2 is fed into the inverting input terminal of the comparator COM3. 导通时间控制电路4132基于输入电压Vin和第二输出电压Vout2产生具有第二时间阈值T0N2的导通时间控制信号COT。 On-time control circuit 4132 based on the input voltage Vin and the second output voltage Vout2 COT generating a signal having a second time threshold T0N2 on-time control. 此外,触发器FFl被置位,开关控制信号PWM为高电平,第一驱动电路4135将第一开关管SI导通,第二开关管S2关断,直至第一开关管SI的导通时间达到第二时间阈值T0N2。 In addition, the flip-flop FFl is controlled to set the switching signal PWM is high, the first driving circuit 4135 of the first switch SI is turned on, the second switch S2 is turned off, until the first switch SI conduction time reaches the second time threshold T0N2.

[0053] 图6为根据本发明一实施例的单电感多输出降压变换器400的工作波形图,其中Vsw表示电感器LI第一端的电压。 [0053] FIG. 6 is a waveform diagram 400 in accordance with the work of a single inductor multiple output buck converter of an embodiment of the invention, wherein the voltage Vsw represents a first end of the inductor LI. 如图6所示,第一降压变换器和第二降压变换器分时工作,从而实现对第一输出电压Voutl和第二输出电压Vout2的调节。 As shown in Figure 6, the first buck converter and the second buck converter time-sharing, in order to achieve a first output voltage Voutl and Vout2 of the second output voltage regulation.

[0054] 图7为根据本发明一实施例的单电感多输出降压变换器700的框图,其中二极管Dl被用于代替第二开关管S2。 [0054] FIG. 7 is a block diagram 700 in accordance with a single inductor multiple output buck converter of an embodiment of the invention, in which the diode Dl is used instead of the second switch S2.

[0055] 前述实施例中均以双输出为例,然而,通过在电感器的第二端耦接更多的开关管和电容器,可提供更多的输出。 [0055] The foregoing embodiments are dual-output as an example, however, by the second end of the inductor is coupled more switches and capacitors, may provide more output. 在一个实施例中,单电感多输出降压变换器包括具有第一端和第二端的电感器、耦接在输入电压与电感器第一端之间的第一开关管、耦接在电感器第一端与参考地之间的第二开关管、分别耦接在电感器第二端与多个输出电压之间的多个输出开关管、分别耦接在多个输出电压与参考地之间的多个电容器以及控制电路。 In one embodiment, a single multi-output buck converter comprises an inductor having a first end and a second end of the inductor, a first switch coupled between the input voltage and the inductor between the first end, coupled inductor a first end and a second switch between the ground reference, respectively, coupled to a plurality of output switch in a second end of the inductor and the plurality of output voltage, respectively coupled between the plurality of the output voltage with a reference ground a plurality of capacitors and a control circuit. 控制电路包括多个比较电路和逻辑电路。 The control circuit includes a plurality of comparator circuits and logic circuits. 多个比较电路产生多个比较信号,其中每个比较电路将代表相应输出电压的反馈信号与相应参考信号进行比较,以产生相应比较信号。 A plurality of comparator circuit generates a plurality of comparison signals, each of which represents the corresponding comparison circuit compares the output voltage feedback signal is compared with the corresponding reference signal to generate a respective comparison signals. 逻辑电路耦接至多个比较电路,基于多个比较信号控制第一开关管、第二开关管和多个输出开关管。 A logic circuit coupled to the plurality of comparator circuits, a plurality of comparison signals based on a first control switch, the second switch and a plurality of output switch. 若某个比较信号的出现早于其余比较信号,则逻辑电路将与该较早出现的比较信号对应的输出开关管导通,将其余输出开关管关断,并将第一开关管导通,第二开关管关断,在第一开关管的导通时间达到相应时间阈值时,逻辑电路将第一开关管关断,第二开关管导通。 If there is a comparison signal earlier than the rest of the comparison signal, the logic circuit will appear in the earlier comparison signal corresponding output switch turns on, the rest of the output switch off, and the first switch is turned on, The second switch is turned off, the time to reach the corresponding threshold conduction time of the first switch tube, the logic of the first switch off, the second switch is turned on. 本实施例中的第二开关管也可用二极管代替。 According to the second switch diode can also be used in place of the present embodiment.

[0056] 在一些实施例中,为了消除次谐波振荡,斜坡补偿信号被叠加至反馈信号或从参考信号中被减去,比较电路将反馈信号与斜坡补偿信号之和与参考信号进行比较,以产生比较信号。 [0056] In some embodiments, in order to eliminate subharmonic oscillation, the slope compensation signal is superimposed to the feedback signal or subtracted from the reference signal, the feedback circuit comparing the ramp signal with the sum of the compensation signal is compared with a reference signal, to produce a comparison signal. 本领域技术人员应当理解,这样的解决方案也未脱离本发明的保护范围。 Those skilled in the art should appreciate that such solutions are not departing from the scope of the present invention.

[0057] 虽然已参照几个典型实施例描述了本发明,但应当理解,所用的术语是说明和示例性、而非限制性的术语。 [0057] Although described with reference to several exemplary embodiments of the present invention, it is to be understood that the terminology used and the description is illustrative and not restrictive terms. 由于本发明能够以多种形式具体实施而不脱离发明的精神或实质,所以应当理解,上述实施例不限于任何前述的细节,而应在随附权利要求所限定的精神和范围内广泛地解释,因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。 Since the present invention can be implemented in several forms without departing from the spirit or the specific substance of the invention, it should be understood that the above-described embodiments are not limited to any of the foregoing details, but should be construed broadly within the appended claims as defined by the spirit and scope of the , thus within the claims or all changes and modifications within the equivalent scope of the appended claims should be covered.

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Classifications
International ClassificationH02M1/00, H02M1/08
Cooperative ClassificationH02M2001/009, H02M3/158
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