CN103681859A - A silicon carbide semiconductor device and a manufacturing method thereof - Google Patents

A silicon carbide semiconductor device and a manufacturing method thereof Download PDF

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CN103681859A
CN103681859A CN201310377797.2A CN201310377797A CN103681859A CN 103681859 A CN103681859 A CN 103681859A CN 201310377797 A CN201310377797 A CN 201310377797A CN 103681859 A CN103681859 A CN 103681859A
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silicon dioxide
semiconductor device
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gate dielectric
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黄国华
冯明宪
门洪达
张伟
王坤池
周月
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XIAMEN TIANRUI ELECTRONICS Co Ltd
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XIAMEN TIANRUI ELECTRONICS Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
    • H01L21/0425—Making electrodes
    • H01L21/044—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The invention discloses a silicon carbide semiconductor device comprising a semiconductor substrate, a buffer layer and a conductive epitaxial layer. A gate electrode and a source electrode are arranged on the conductive epitaxial layer. The gate electrode comprises a gate medium layer and a polysilicon layer. A well region is arranged inside the conductive epitaxial layer. A source regions is arranged inside the well region. The silicon carbide semiconductor device and the manufacturing method thereof are characterized in that: the gate medium layer comprises a lower layer silicon dioxide layer, a silicon nitride layer arranged on the lower layer silicon dioxide layer and an upper level silicon dioxide layer positioned on the upper end of the silicon nitride layer. The silicon carbide semiconductor device brought forward by the invention can guarantee overpressure resistance of the device grid source satisfies product standards and application requirements, and at the same time, a relatively low interface state concentration and a stable threshold-voltage can be obtained.

Description

A kind of sic semiconductor device and preparation method thereof
Technical field
The present invention relates to semiconductor power device technology field, relate in particular to a kind of sic semiconductor device and preparation method thereof.
Background technology
Most of power semiconductors are all to be formed by silicon (Si), but various other semi-conducting material is also used, and carborundum (SiC) is exactly one of these candidate materials.In order to realize semiconductor device, there is higher withstand voltage and lower drain performance, and can under hot environment, can use it, conventionally adopt carborundum as the material that is used to form semiconductor device.Compare with the material silicon of using traditionally, carborundum is a kind of for the ideal semiconductor material under high voltage, high frequency and high temperature.Due to the large critical electric field of carborundum (be silicon ten times), large band gap (be silicon three times), high thermal conductivity (be silicon four times) and large electronics saturation (be silicon two times), this becomes carborundum to manufacture such as MOSFET(mos field effect transistor), IGBT(insulated gate bipolar transistor) the more desirable material of device.The semiconductor device being formed by carborundum can have higher temperature, with high power density, with higher speed, with higher power level and the ability that operates under high radiation density.
Therefore,, by adopting carborundum as the material that forms semiconductor device, can realize semiconductor device and there is higher withstand voltage and lower on-resistance properties.In addition, adopt carborundum to be also as the benefit of the semiconductor device of material, compare as the semiconductor device of material with adopting silicon, the possibility that when it uses under hot environment, characteristic reduces is less.
On carborundum, make MOSFET and IGBT device, need to form one deck gate dielectric layer in silicon carbide substrates, this gate dielectric layer is generally oxide skin(coating).Yet utilize traditional thermal oxidation technology on carbofrax material, to produce MOSFET, IGBT(insulated gate bipolar transistor) etc. the gate dielectric layer of device, it exists, and speed of production is slow, interface state density is high, the unsettled shortcoming of interface state density, and the epitaxial loayer of growing on carbon face commercially cannot obtain at present, therefore it is desirable to form gate oxide on silicon face, interface between gate oxide and silicon carbide substrates has a large amount of interface traps, and these interface traps exert an influence to the electron transfer of channel region in every way.
This has a great difference with the gate medium technique on silicon substrate, owing to being difficult to grow at silicon carbide and the equally high-quality silicon dioxide layer of Si-gate oxygen technique, and the quality of gate dielectric layer is just directly to have affected many main device parameters, and these problems have hindered further developing of silicon carbide power device, such as the higher interfacial state concentration of gate dielectric layer has directly affected the stability of threshold voltage, its lower breakdown strength requires gate oxide layer thickness large, can meet so the withstand voltage requirement in device grid source, common product application conditions is 15 volts of +/-, and product specification is 30 volts of +/-.But on the other hand,, the raising of gate dielectric layer thickness, can produce again more interfacial state trap, causes the unsettled problem of device threshold voltage.
In order to guarantee the stability of device parameters threshold voltage vt h, need to reduce the direct interfacial state concentration of gate dielectric layer and silicon carbide substrates material, a kind of direct method is exactly to optimize the process heat process of gate dielectric layer, reduce the thermal process time, increase annealing process, yet can produce gate dielectric layer thin thickness like this, the problem that grid source puncture voltage reduces.
Chinese patent application publication No.: CN101933146A, Shen Qing Publication day: on December 29th, 2010, a kind of sic semiconductor device is disclosed, it comprises the silicon carbide substrates of the first conduction type or the second conduction type, the SiC layer of the first conduction type, it is formed on the first first type surface of SiC substrate; The Yi SiC district of the second conduction type, it is formed on the surface of SiC layer; The Er SiC district of the first conduction type, it is formed in the surface in Yi SiC district; Gate-dielectric, it is formed on SiC floor, Er SiC district and continuously on the surface in the Yi SiC district between SiC floor and Er SiC district.A kind of sic semiconductor device that this patent proposes, it has the following disadvantages: owing to being difficult to grow at silicon carbide and the equally high-quality silicon dioxide layer of Si-gate oxygen technique, therefore the gate dielectric layer on this sic semiconductor device is of low quality, and it directly has influence on the stability of device threshold voltage.
Summary of the invention
The present invention is in order to overcome the deficiencies in the prior art part, a kind of sic semiconductor device and preparation method thereof is provided, its sic semiconductor device of producing can guarantee that device grid source is withstand voltage and meet product specification and application requirements, can access lower interfacial state concentration and stable threshold voltage simultaneously.
To achieve these goals, the present invention is by the following technical solutions:
A manufacture method for sic semiconductor device, comprises the following steps:
(1) provide a semiconductor, described semiconductor comprises Semiconductor substrate and the resilient coating of the layer that forms in semiconductor substrate surface deposit and be positioned at the conduction epitaxial loayer on resilient coating;
(2) at described semi-conductive upper surface, apply photoresist, photoetching, etching, inject first kind foreign ion and form well region;
(3) remove the photoresist of above-mentioned upper semiconductor, more again apply photoresist, photoetching, etching, injecting Equations of The Second Kind foreign ion formation Equations of The Second Kind impurity ion region is source region;
(4) remove the photoresist of upper semiconductor in the 3rd step, inject first kind foreign ion, form first kind impurity ion region;
(5) at described upper semiconductor growth layer of silicon dioxide layer, the ground floor that this silicon dioxide layer is gate dielectric layer;
(6) one deck silicon nitride layer of growing on described silicon dioxide layer, the second layer that this silicon nitride layer is gate dielectric layer;
(7) the layer of silicon dioxide layer of growing on described silicon nitride layer, this silicon oxide layer is gate dielectric layer the 3rd layer;
(8) at described semi-conductive upper surface deposit one deck polysilicon layer, described polysilicon layer covers above-mentioned gate dielectric layer;
(9) utilize photoresist to make masking layer, the optionally above-mentioned polysilicon layer of etching and gate dielectric layer, thus form gate electrode;
(10) at upper semiconductor deposit one deck insulating medium layer, on above-mentioned insulating medium layer, carry out photoetching and the etching of contact hole, obtain source lead hole;
(12) in upper semiconductor deposited metal, described metal level covers described insulating medium layer, by metal level being carried out to photoetching and etching obtains source metal.
The manufacture method of a kind of sic semiconductor device proposed by the invention, its gate medium in making manufacturing silicon carbide semiconductor technical process is comprised of trilaminate material, and it can guarantee that device grid source is withstand voltage and meet product specification and application requirements.
As preferably, described ground floor silicon dioxide layer, its growing environment is high warm and humid fosterization, and thickness is 10 ~ 30nm, and temperature during its growth is controlled between 950 ~ 1050 degrees Celsius.In this preferred version, because the thickness of bottom ground floor silicon dioxide is arranged between 10 ~ 30nm, its thin thickness, can reduce growth temperature, speed and growth time, thereby reduce the interface state density of itself and semiconductor substrate materials, the scope of its growth temperature is 950 ℃ ~ 1050 ℃, and its speed of growth is 0.1 ~ 0.2nm per minute, and growth time shortens to 100 ~ 200 minutes.
As preferably, described second layer silicon nitride layer, it adopts the technique growth pattern of LPCVD, and its thickness is 10 ~ 30nm.
As preferably, described the 3rd layer of silicon dioxide layer, its growth technique condition is high-temperature oxydation, its thickness is less than 10nm, its temperature is controlled between 1100 ~ 1200 degrees Celsius, and in the second half section of three layers of silicon dioxide layer of growth regulation, its temperature improves 20 ~ 50 degrees Celsius, reduce the flow of oxygen, improve the flow of nitrogen simultaneously.In this preferred version, in the second half section of high-temperature oxidation process, temperature is carried out the raising of 20 ℃ ~ 50 ℃, reduce the flow that oxygen flow improves nitrogen simultaneously, can carry out annealing in process for grown silicon dioxide layer for the first time and second layer silicon nitride layer like this, to reduce stress, repair-deficiency, further reduces interface state density.
As preferably, described semiconductor substrate materials is carborundum.In this preferred version, semiconductor substrate materials adopts carbofrax material, and it can allow the semiconductor device of producing have higher withstand voltage properties and have lower conducting resistance.
As preferably, more than the doping content of described Semiconductor substrate is set in E18/cm3.Red in this preferred version, more than the doping content of Semiconductor substrate is set in E18/cm3, can reduce like this series resistance that semiconductor substrate materials forms.
As preferably, when etching gate dielectric layer, in the etching technics of second layer silicon nitride layer, use CF 4as etching gas, increase the content of oxygen and nitrogen; In the etching technics of ground floor silicon dioxide layer, increase the content of oxygen.In this preferred version, the content that increases oxygen and nitrogen in the etching technics of silicon nitride layer is for the second time used for diluting CF 4concentration, to reduce the etch rate to ground floor silicon dioxide layer, and the etch rate that reaches 20:1 is selected ratio; In the etching technics of ground floor silicon dioxide layer, increase the content of oxygen, it can oxide and the selection ratio of semiconductor substrate materials.
A kind of sic semiconductor device, comprise Semiconductor substrate, resilient coating and conduction epitaxial loayer, on described conduction epitaxial loayer, be provided with gate electrode and source electrode, described gate electrode comprises gate dielectric layer and polysilicon layer, in described conduction epitaxial loayer, be provided with well region, in described well region, be provided with source region, described gate dielectric layer comprises lower floor's silicon dioxide layer, be positioned at silicon nitride layer on lower floor's silicon dioxide layer, be positioned at the upper strata silicon dioxide layer of silicon nitride layer upper end.
A kind of sic semiconductor device proposed by the invention, its gate dielectric layer is comprised of trilaminate material: the silicon nitride layer in lower floor's silicon dioxide layer, intermediate layer and upper strata silicon dioxide layer, its thin thickness of lower floor's silicon dioxide layer, can optimize the interface state density that its growth temperature, growth temperature and growth time reduce lower floor's silicon dioxide layer and Semiconductor substrate; Its dielectric constant of silicon nitride layer is large, and therefore under same thickness, it has larger capacitance parameter, and the breakdown strength of silicon nitride layer is large simultaneously, and under same thickness, silicon nitride layer has larger grid source puncture voltage; Upper strata silicon dioxide layer is for strengthening the compactness of silicon nitride layer.The present invention is by changing the material of gate dielectric layer, and the grid leak electricity, device threshold voltage, dynamic power consumption etc. of sic semiconductor device are improved.We can explain above said interface state density and the affect relation of Cge on Vth of showing from the physical equation of Vth.Described in the textbook of relevant semiconductor device aspect, there is following Vth formula, Vth=Φ s+ Φ s/ Cgs
Wherein: Φ s is surface potential, Q is electron charge, is constant herein; Na is surface impurity concentration, and ε 0 is vacuum dielectric coefficient, and ε si is that silicon materials dielectric coefficient is Cgs device grid source electric capacity.
When considering surface potential (being mainly interfacial state) on the affecting of Vth, differentiated in above-mentioned company's equal sign both sides simultaneously, obtain
d(Vth)?=?d（Φs）?+?k?*?d（Φs）/?Cgs
Wherein, K=
Figure 706291DEST_PATH_IMAGE001
/ Φ s,
As preferably, described Semiconductor substrate is N-type carborundum or P type carborundum.In this preferred version, Semiconductor substrate adopts N-type carborundum, and what it made formation is power MOSFET device; Semiconductor substrate adopts P type carborundum, and what it made formation is IGBT(insulated gate bipolar transistor).
Compared with prior art, the present invention has following beneficial effect: (1) reduces gate dielectric layer interface state density, improves the stability of device parameters; (2) guaranteed the impact that the parameters such as grid source is withstand voltage, the electric leakage of grid source are not diminished by grid medium thickness; (3) can improve grid source electric capacity, further reduce the impact of gate dielectric layer interfacial state on device parameters Vth stability; For IGBT device, after improving grid source electric capacity, can also improve Cge and Cce electric capacity ratio, can reduce the grid concussion under short circuit condition, the short circuit safety operation area of improving device; (4) be conducive to reduce gate electrode (doped polycrystalline silicon) in phosphoric diffusion technology process, gate electrode impurity impact on channel region concentration in subsequent technique thermal process simultaneously, improves device parameters as Vth, Rdson, the stability of V cesat.
Accompanying drawing explanation
Fig. 1 is a kind of structural representation of the present invention.
Fig. 2 is the structural representation of gate dielectric layer of the present invention.
In figure, 1-N-type silicon carbide substrates, 2-resilient coating, 3-conduction epitaxial loayer, 4-P well region, 5-N +source region, 6-gate dielectric layer, 7-lower floor silicon dioxide layer, 8-silicon nitride layer, 9-upper strata silicon dioxide layer.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described.
Embodiment:
As shown in Figure 1 and Figure 2: it is example that N-type silicon carbide power MOSFET device is take in the present invention, a kind of method of making N-type silicon carbide power MOSFET device, comprise the following steps: a. provides a N-type carborundum, described N-type carborundum comprises N-type silicon carbide substrates 1 and the resilient coating 2 of the layer that forms at N-type silicon carbide substrates 1 surface deposition and be positioned at the conduction epitaxial loayer 3 on resilient coating 2, more than the doping content of described N-type silicon carbide substrates 1 is set in E18/cm3;
B. at the upper surface of described N-type carborundum, apply photoresist, photoetching, etching, application high energy ion implanter carries out ion implantation technology under high-temperature, and injections element is triad, as element etc., thus formation P well region 4;
C. remove the photoresist of above-mentioned N-type carborundum upper surface, more again apply photoresist, photoetching, etching, application high energy ion implanter carries out ion implantation technology under high-temperature, injects element and is chosen as pentad, as nitrogen element, thereby forms N +source region 5;
D. remove the photoresist of N-type carborundum upper surface in the 3rd step, application high energy ion implanter, at high temperature carries out ion implantation technology, and injection element is triad, as aluminium element, thereby forms P +district;
E. at described upper semiconductor growth lower floor silicon dioxide layer 7, this lower floor's silicon dioxide layer 7 is the ground floor of gate dielectric layer 6, described lower floor silicon dioxide layer 7, and its growing environment is high warm and humid fosterization, thickness is 10 ~ 30nm, and temperature during its growth is controlled between 950 ~ 1050 degrees Celsius;
F. one deck silicon nitride layer 8 of growing on described lower floor silicon dioxide layer 7, this silicon nitride layer 8 is the second layer of gate dielectric layer 6; Described silicon nitride layer adopts the technique growth pattern of LPCVD, and its thickness is 10 ~ 30nm;
G. the upper strata silicon dioxide layer 9 of growing on described silicon nitride layer, this upper strata silicon dioxide layer 9 is the 3rd layer of gate dielectric layer 6, the growth technique condition of described lower floor silicon dioxide layer 9 is high-temperature oxydation, its thickness is less than 10nm, its temperature is controlled between 1100 ~ 1200 degrees Celsius, and in the second half section of growth lower floor silicon dioxide layer, its temperature improves 20 ~ 50 degrees Celsius, reduce the flow of oxygen, improve the flow of nitrogen simultaneously;
H. at upper surface deposit one deck polysilicon layer of described N-type carborundum, described polysilicon layer covers above-mentioned gate dielectric layer 6;
I. utilize photoresist to make masking layer, the optionally above-mentioned polysilicon layer of etching and gate dielectric layer 6, thus form gate electrode; In to the etching technics of polysilicon, for fear of to polysilicon layer be positioned at gate dielectric layer 6 etching process intermediate ions below polysilicon layer and bombard the upper strata silicon dioxide layer 9 below polysilicon layer, and the loss that reduces photoresist above it, the ability of bombarding ion needs enough low; Simultaneously in order to protect the upper strata silicon dioxide layer 9 below polysilicon, the present invention adopts bromine-based gas (as HBr etc.) to carry out etch polysilicon layer, such benefit is that not only anisotropy is good, guarantee polysilicon layer etch topography near normal, can also there is higher etching rate to the upper strata silicon dioxide layer 9 below polysilicon layer and silicon nitride layer 8 and select ratio; Because upper strata silicon dioxide layer 9 is thinner, in this single-step process, apply the etching gas of little energy, low concentration to guarantee the stability of technique; When etching gate dielectric layer, in the etching technics of second layer silicon nitride layer, use CF 4as etching gas, increase the content of oxygen and nitrogen; In the etching technics of ground floor silicon dioxide layer, increase the content of oxygen; The present invention only carries out photoetching process one time, the photoresist that is to say shielding etching figure needs to retain in whole etching process always, can guarantee like this autoregistration and the zero contraposition deviation of Poly and ONO figure, also realized the object of simplifying a photoetching process, simultaneously in order to reach the object of above-mentioned reservation photoresist, plasma energy in whole etching process is controlled at enough low, the etching rate of photoresist is selected enough higher than necessary.
G. at upper semiconductor deposit one deck insulating medium layer, on above-mentioned insulating medium layer, carry out photoetching and the etching of contact hole, obtain source lead hole;
K. in the upper surface deposited metal of N-type carborundum, described metal level covers described insulating medium layer, by metal level being carried out to photoetching and etching obtains source metal.
Above content is only preferred embodiment of the present invention, for those of ordinary skill in the art, according to thought of the present invention, in embodiment and range of application, all will change, and this description should not be construed as limitation of the present invention.

Claims (9)

1. a manufacture method for sic semiconductor device, is characterized in that comprising the following steps:
(1) provide a semiconductor, described semiconductor comprises Semiconductor substrate and the resilient coating of the layer that forms in semiconductor substrate surface deposit and be positioned at the conduction epitaxial loayer on resilient coating;
(2) at described semi-conductive upper surface, apply photoresist, photoetching, etching, inject first kind foreign ion and form well region;
(3) remove the photoresist of above-mentioned upper semiconductor, more again apply photoresist, photoetching, etching, injecting Equations of The Second Kind foreign ion formation Equations of The Second Kind impurity ion region is source region;
(4) remove the photoresist of upper semiconductor in the 3rd step, inject first kind foreign ion, form first kind impurity ion region;
(5) at described upper semiconductor growth layer of silicon dioxide layer, the ground floor that this silicon dioxide layer is gate dielectric layer;
(6) one deck silicon nitride layer of growing on described silicon dioxide layer, the second layer that this silicon nitride layer is gate dielectric layer;
(7) the layer of silicon dioxide layer of growing on described silicon nitride layer, this silicon oxide layer is gate dielectric layer the 3rd layer;
(8) at described semi-conductive upper surface deposit one deck polysilicon layer, described polysilicon layer covers above-mentioned gate dielectric layer;
(9) utilize photoresist to make masking layer, the optionally above-mentioned polysilicon layer of etching and gate dielectric layer, thus form gate electrode;
(10) at upper semiconductor deposit one deck insulating medium layer, on above-mentioned insulating medium layer, carry out photoetching and the etching of contact hole, obtain source lead hole;
(12) in upper semiconductor deposited metal, described metal level covers described insulating medium layer, by metal level being carried out to photoetching and etching obtains source metal.
2. the manufacture method of a kind of sic semiconductor device according to claim 1, it is characterized in that: described ground floor silicon dioxide layer, its growing environment is high warm and humid fosterization, and thickness is 10 ~ 30nm, and temperature during its growth is controlled between 950 ~ 1050 degrees Celsius.
3. the manufacture method of a kind of sic semiconductor device according to claim 1, is characterized in that: described second layer silicon nitride layer, and it adopts the technique growth pattern of LPCVD, and its thickness is 10 ~ 30nm.
4. the manufacture method of a kind of sic semiconductor device according to claim 1, it is characterized in that: described the 3rd layer of silicon dioxide layer, its growth technique condition is high-temperature oxydation, its thickness is less than 10nm, its temperature is controlled between 1100 ~ 1200 degrees Celsius, and in the second half section of three layers of silicon dioxide layer of growth regulation, its temperature improves 20 ~ 50 degrees Celsius, reduce the flow of oxygen, improve the flow of nitrogen simultaneously.
5. the manufacture method of a kind of sic semiconductor device according to claim 1, is characterized in that: described semiconductor substrate materials is carborundum.
6. the manufacture method of a kind of sic semiconductor device according to claim 1, is characterized in that: more than the doping content of described Semiconductor substrate is set in E18/cm3.
7. the manufacture method of a kind of sic semiconductor device according to claim 1, is characterized in that: when etching gate dielectric layer, in the etching technics of second layer silicon nitride layer, use CF 4as etching gas, increase the content of oxygen and nitrogen; In the etching technics of ground floor silicon dioxide layer, increase the content of oxygen.
8. a sic semiconductor device, comprise Semiconductor substrate, resilient coating and conduction epitaxial loayer, on described conduction epitaxial loayer, be provided with gate electrode and source electrode, described gate electrode comprises gate dielectric layer and polysilicon layer, in described conduction epitaxial loayer, be provided with well region, in described well region, be provided with source region, it is characterized in that: described gate dielectric layer comprises lower floor's silicon dioxide layer, be positioned at silicon nitride layer on lower floor's silicon dioxide layer, be positioned at the upper strata silicon dioxide layer of silicon nitride layer upper end.
9. a kind of sic semiconductor device according to claim 8, is characterized in that: described Semiconductor substrate is N-type carborundum or P type carborundum.
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CN104701362A (en) * 2015-03-23 2015-06-10 东南大学 Trench-isolated and lateral insulated-gate bipolar transistor
CN107871781A (en) * 2016-09-27 2018-04-03 西安电子科技大学 A kind of silicon carbide MOSFET and its manufacture method
CN109003879A (en) * 2017-06-06 2018-12-14 中芯国际集成电路制造(上海)有限公司 The forming method of gate dielectric layer
CN115700217A (en) * 2021-07-21 2023-02-07 合肥本源量子计算科技有限责任公司 Preparation method of air bridge and superconducting quantum device

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CN104701362A (en) * 2015-03-23 2015-06-10 东南大学 Trench-isolated and lateral insulated-gate bipolar transistor
CN107871781A (en) * 2016-09-27 2018-04-03 西安电子科技大学 A kind of silicon carbide MOSFET and its manufacture method
CN109003879A (en) * 2017-06-06 2018-12-14 中芯国际集成电路制造(上海)有限公司 The forming method of gate dielectric layer
CN109003879B (en) * 2017-06-06 2021-03-19 中芯国际集成电路制造(上海)有限公司 Forming method of gate dielectric layer
CN115700217A (en) * 2021-07-21 2023-02-07 合肥本源量子计算科技有限责任公司 Preparation method of air bridge and superconducting quantum device

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