CN103681334B - The method that grid polycrystalline silicon exhausts in suppression PMOS device technique - Google Patents
The method that grid polycrystalline silicon exhausts in suppression PMOS device technique Download PDFInfo
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- CN103681334B CN103681334B CN201210337223.8A CN201210337223A CN103681334B CN 103681334 B CN103681334 B CN 103681334B CN 201210337223 A CN201210337223 A CN 201210337223A CN 103681334 B CN103681334 B CN 103681334B
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- polycrystalline silicon
- grid
- pmos device
- grid polycrystalline
- boron
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
Abstract
The invention discloses a kind of method that grid polycrystalline silicon exhausts in suppression PMOS device technique, including step：Boron ion is injected in grid polycrystalline silicon；N~+ implantation is carried out in gate polycrystalline silicon face；Tungsten silicon layer is formed on the surface of grid polycrystalline silicon.The present invention is by after the injection of the grid polycrystalline silicon boron of PMOS device, N~+ implantation is carried out again, one layer of fine and close nitride film can be formed in gate polycrystalline silicon face, nitride film can prevent diffusion into the surface of the boron to grid polycrystalline silicon, can reduce during subsequent thermal, promote boron to penetrate into the risk in tungsten silicon layer, so as to effectively suppress the grid polycrystalline silicon that boron penetration causes in WSI layers in PMOS device technique to exhaust the generation of phenomenon, the threshold voltage stabilization of PMOS device is made.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, in more particularly to a kind of suppression PMOS techniques
Grid polycrystalline silicon exhausts（Poly Depletion Effects）Method.
Background technology
In existing process, integrated in nmos device for convenience, the grid polycrystalline silicon of PMOS device is adopted and nmos device
Grid polycrystalline silicon identical doping condition, i.e., be all n-type doping and require heavy doping, the grid polycrystalline silicon N of PMOS device
After type doping, it is necessary to form a p-type buried channel in channel region（buried channel）Could solve what N-type grid polycrystalline silicon was caused
Threshold voltage（Vt）Higher problem, introducing for p-type buried channel can produce larger leakage problem again.In order to solve existing PMOS
Higher Vt and the problem of larger leakage current that the buried channel of device causes, using p-type boron impurity come to PMOS in prior art
The grid polycrystalline silicon of device carry out p-type adulterate and for heavy doping, i.e. nmos device grid polycrystalline silicon formed n-type doping knot
Structure, the grid polycrystalline silicon of PMOS device form the structure of p-type doping, could so reduce the P-type grid electrode polysilicon of PMOS device
And the contact gesture between the channel region on silicon substrate, the threshold voltage of PMOS device and the effect of electric leakage can be reduced.But
As nmos device and PMOS device will be integrated, therefore the grid of the grid and PMOS device ensured by nmos device can
Good contact is realized, due to there are contact problems between P-type grid electrode polysilicon and N-type grid polycrystalline silicon, so prior art
Middle employing all forms tungsten silicon layer on P-type grid electrode polysilicon and N-type grid polycrystalline silicon respectively（WSI, Tungsten Polycide）
To realize the good contact connection of the grid of nmos device and the grid of PMOS device.
The grid polycrystalline silicon of PMOS device is adulterated and is formed after tungsten silicon layer, as boron is in tungsten silicon layer and polysilicon using boron
Middle solubility substantially 100:1, so easily affected by subsequent heat treatment, cause boron to pass through tungsten silicon layer and grid polycrystalline silicon
Interface, enters in tungsten silicon layer and builds up in tungsten silicon layer, i.e., the grid polycrystalline silicon that can finally produce PMOS device exhausts（Poly
Depletion Effects）, so as to cause the threshold voltage shift of PMOS device.As shown in figure 1, being formed on silicon substrate 101
There are gate oxide 102, and gate polysilicon layer 103 and tungsten silicon layer 104, wherein p-type boron is injected with gate polysilicon layer 103
Impurity, the structure after subsequent heat treatment is carried out, as the solubility in tungsten silicon layer 104 of boron is bigger, therefore can wear by boron impurity
Thoroughly in tungsten silicon layer 104, the boron impurity of gate polysilicon layer 103 can greatly reduce, and can be thus the PMOS devices for eventually forming
The threshold voltage shift of part.
In order to overcome situation of the above-mentioned boron penetration in tungsten silicon layer to occur, as shown in Fig. 2 a kind of existing process be
After gate polysilicon layer 103 carries out boron doping, one layer of titanium and titanium nitride are formed on the surface of gate polysilicon layer 103（Ti/TiN）
Barrier layer 105, then on barrier layer 105 formed tungsten silicon layer 104, wherein the silicon nitride layer 106 on tungsten silicon layer 104 for isolation
Protective layer.I.e. existing method prevents the boron impurity in grid polycrystalline silicon 103 after the heating to tungsten silicon layer using barrier layer 105
Infiltration aggregation in 104.Although said method can suppressor grid depletion of polysilicon occur, the titanium being newly introduced is easy to rear
Continuous grid polycrystalline silicon is reoxidized（Re-oxidation）Technique is oxidized and expands, and eventually causes hemisphere jut
（pilling）, this can affect very big, be unfavorable for the stable performance of device on the pattern of grid structure.Meanwhile, the introducing of titanium,
There is the risk of metal ion pollution to the product in processing line.
The content of the invention
The technical problem to be solved is to provide a kind of grid polycrystalline silicon in suppressing PMOS device technique and exhausts
Method, can suppress the boron penetration in the grid polycrystalline silicon of PMOS device in tungsten silicon layer, make the threshold voltage stabilization of PMOS device.
To solve above-mentioned technical problem, the method that grid polycrystalline silicon exhausts in the suppression PMOS device technique that the present invention is provided
Comprise the steps：
After step one, on a silicon substrate formation grid polycrystalline silicon, boron ion is injected in the grid polycrystalline silicon, make described
Grid polycrystalline silicon is in p-type doped structure.
Step 2, boron ion injection after, carry out N~+ implantation in the gate polycrystalline silicon face, in the grid
Polysilicon surface forms one layer of nitride film.
Step 3, the surface of the grid polycrystalline silicon after N~+ implantation form tungsten silicon layer, by the tungsten silicon layer and
The grid polycrystalline silicon constitutes the grid of the PMOS device.
Further improvement be, the energy of the injection boron ion in step one is 3KeV～8Kev, and implantation dosage is
1E15cm-2～1E16cm-2。
Further improvement be, the energy of the injecting nitrogen ion in step 2 is 5KeV～20KeV, and implantation dosage is
5E14cm-2～4E15cm-2。
The inventive method, can be by, after the injection of the grid polycrystalline silicon boron of PMOS device, then carrying out N~+ implantation
Gate polycrystalline silicon face forms one layer of fine and close nitride film, and the nitride film can prevent diffusion into the surface of the boron to grid polycrystalline silicon,
Can reduce during subsequent thermal, promote boron to penetrate into the risk in tungsten silicon layer, so as to effectively suppress in PMOS device technique
The grid polycrystalline silicon that boron penetration causes in WSI layers exhausts the generation of phenomenon, makes the threshold voltage stabilization of PMOS device.
Description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is grid structure of the existing PMOS device with tungsten silicon layer and polysilicon layer；
Fig. 2 is grid structure of the existing PMOS device with tungsten silicon layer, barrier layer and polysilicon layer；
Fig. 3 is the flow chart of present invention method；
Fig. 4 A- Fig. 4 C are device junction compositions in each step of present invention method.
Specific embodiment
As shown in figure 3, being the flow chart of present invention method；The embodiment of the present invention suppresses grid in PMOS device technique
The method of pole depletion of polysilicon comprises the steps：
Step one, as shown in Figure 4 A, sequentially forms gate dielectric layer 2 and grid polycrystalline silicon 3 on silicon substrate 1, and wherein grid are situated between
Matter layer 1 can be an oxide layer.After grid polycrystalline silicon 3 is formed, note in the grid polycrystalline silicon 3 of PMOS device forming region
Enter boron ion, the energy for injecting boron ion is 3KeV～8Kev, and implantation dosage is 1E15cm-2～1E16cm-2, make the PMOS
The grid polycrystalline silicon 3 of nmosfet formation region is in p-type doped structure.
Step 2, as shown in Figure 4 A is more in the grid of the PMOS device forming region after boron ion injection
3 surface of crystal silicon carries out N~+ implantation, and the energy of injecting nitrogen ion is 5KeV～20KeV, and implantation dosage is 5E14cm-2~
4E15cm-2.As shown in Figure 4 B, after N~+ implantation, one layer of fine and close nitride film is formed on 3 surface of the grid polycrystalline silicon
3a。
Step 3, as shown in Figure 4 C, forms tungsten silicon layer 4 on the surface of the grid polycrystalline silicon 3, to 4 He of the tungsten silicon layer
The grid polycrystalline silicon 3 carries out chemical wet etching, by chemical wet etching after the tungsten silicon positioned at the PMOS device forming region
Layer 4 and the grid polycrystalline silicon 3 build up the grid for constituting the PMOS device.Wherein due to 3 surface of the grid polycrystalline silicon
Nitride film 3a is formed with, nitride film 3a can reduce the diffusion rate of boron dopant atom, prevents table of the boron to grid polycrystalline silicon 3
Face is spread, and can reduce during subsequent thermal, promote boron to penetrate into the risk in tungsten silicon layer, so as to effectively suppress PMOS devices
The generation that grid polycrystalline silicon 3 exhausts in part technique, makes the threshold voltage stabilization of PMOS device.
Side wall, and the shape in the silicon substrate 1 of the grid both sides are formed in the side of the grid of PMOS device afterwards
Into the source-drain area of PMOS device.
PMOS device is general and nmos device integrates to be formed, in the region for forming nmos device, nmos device
Grid polycrystalline silicon adopt n-type doping, tungsten silicon layer is also formed with grid polycrystalline silicon.PMOS device and nmos device are integrated in
When together, the connection of grid device between is realized by tungsten silicon layer.
The present invention is described in detail above by specific embodiment, but these have not constituted the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (3)
1. a kind of method that grid polycrystalline silicon exhausts in suppression PMOS device technique, it is characterised in that comprise the steps：
After step one, on a silicon substrate formation grid polycrystalline silicon, boron ion is injected in the grid polycrystalline silicon, make the grid
Polysilicon is in p-type doped structure；
Step 2, boron ion injection after, carry out N~+ implantation in the gate polycrystalline silicon face, in the gate polycrystalline
Silicon face forms one layer of nitride film；
Step 3, the surface of the grid polycrystalline silicon after N~+ implantation form tungsten silicon layer, to the tungsten silicon layer and described
Grid polycrystalline silicon carries out chemical wet etching, by chemical wet etching after the tungsten silicon layer and the grid positioned at PMOS device forming region
Pole polysilicon builds up the grid for constituting the PMOS device；
The nitride film that the gate polycrystalline silicon face is formed can reduce the diffusion rate of boron dopant atom, prevent boron to institute
The diffusion into the surface of grid polycrystalline silicon is stated, during subsequent thermal, promote boron to penetrate in the tungsten silicon layer risk can be reduced,
So as to effectively suppress the generation that grid polycrystalline silicon exhausts described in the PMOS device technique, the threshold voltage of PMOS device is made
It is stable；
Side wall is formed in the side of the grid of the PMOS device afterwards, and is formed in the silicon substrate of the grid both sides
The source-drain area of PMOS device.
2. the method that grid polycrystalline silicon exhausts in suppression PMOS device technique as claimed in claim 1, it is characterised in that：Step
The energy of the injection boron ion in is 3KeV～8KeV, and implantation dosage is 1E15cm-2～1E16cm-2。
3. the method that grid polycrystalline silicon exhausts in suppression PMOS device technique as claimed in claim 1, it is characterised in that：Step
The energy of the injecting nitrogen ion in two is 5KeV～20KeV, and implantation dosage is 5E14cm-2～4E15cm-2。
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5648673A (en) * | 1994-12-28 | 1997-07-15 | Nippon Steel Corporation | Semiconductor device having metal silicide film on impurity diffused layer or conductive layer |
| US5846871A (en) * | 1997-08-26 | 1998-12-08 | Lucent Technologies Inc. | Integrated circuit fabrication |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070079802A (en) * | 2006-02-03 | 2007-08-08 | 주식회사 하이닉스반도체 | Method for forming transistor of semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5648673A (en) * | 1994-12-28 | 1997-07-15 | Nippon Steel Corporation | Semiconductor device having metal silicide film on impurity diffused layer or conductive layer |
| US5846871A (en) * | 1997-08-26 | 1998-12-08 | Lucent Technologies Inc. | Integrated circuit fabrication |
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