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Publication numberCN103681334 A
Publication typeApplication
Application numberCN 201210337223
Publication date26 Mar 2014
Filing date12 Sep 2012
Priority date12 Sep 2012
Also published asCN103681334B
Publication number201210337223.8, CN 103681334 A, CN 103681334A, CN 201210337223, CN-A-103681334, CN103681334 A, CN103681334A, CN201210337223, CN201210337223.8
Inventors陈瑜, 罗啸, 李喆
Applicant上海华虹宏力半导体制造有限公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Method for inhibiting depletion of grid polysilicon in PMOS device technology
CN 103681334 A
Abstract
The invention discloses a method for inhibiting depletion of a grid polysilicon in a PMOS (p-channel metal oxide semiconductor) device technology. The method comprises the following steps: implanting boron ions into the grid polysilicon; implanting nitrogen ions on the surface of the grid polysilicon; forming a wolfram silicon layer on the surface of the grid polysilicon. Through nitrogen ion implantation after boron ion implantation into the grid polysilicon of a PMOS device, a dense nitride film can be formed on the surface of the grid polysilicon, and the nitride film can prevent boron from diffusing to the surface of the grid polysilicon and can reduce a risk that in the subsequent thermal process, boron is promoted to penetrate into the wolfram silicon layer, so that the depletion of the grid polysilicon caused by boron penetration into a WSI (wolfram silicon layer) in the PMOS device technology can be effectively inhibited, and the threshold voltage of the PMOS device is stable.
Claims(3)  translated from Chinese
1.一种抑制PMOS器件工艺中栅极多晶硅耗尽的方法,其特征在于,包括如下步骤: 步骤一、在硅衬底上形成栅极多晶硅后,在所述栅极多晶硅中注入硼离子,使所述栅极多晶硅呈P型掺杂结构; 步骤二、在硼离子注入之后,在所述栅极多晶硅表面进行氮离子注入,在所述栅极多晶娃表面形成一层氮化膜; 步骤三、在氮离子注入后的所述栅极多晶硅的表面形成钨硅层,由所述钨硅层和所述栅极多晶硅组成所述PMOS器件的栅极。 A PMOS gate polysilicon depletion device process in a method of inhibiting, characterized by comprising the following steps: Step 1, after forming a gate polysilicon on the silicon substrate, boron ions are implanted in the gate polysilicon, so that the gate was a P-doped polysilicon structure; step two, after ion implantation of boron in the gate polysilicon surface nitrogen ion implantation, at the gate of polycrystalline silicon nitride film formed on the surface layer of the baby; Step three, in the nitrogen ion implantation after the gate polysilicon layer formed on the surface tungsten silicon, a gate of the PMOS device by the tungsten silicon layer and the gate polysilicon.
2.如权利要求1所述的抑制PMOS器件工艺中栅极多晶硅耗尽的方法,其特征在于:步骤一中的注入硼离子的能量为3KeV〜8KeV,注入剂量为lE15cm_2〜lE16cm_2。 2. The inhibition of the gate of the PMOS device 1 according to the process of the polysilicon depletion method of claim, wherein: the energy of boron ions implanted in step one is 3KeV~8KeV, an implantation dose of lE15cm_2~lE16cm_2.
3.如权利要求1所述的抑制PMOS器件工艺中栅极多晶硅耗尽的方法,其特征在于:步骤二中的注入氮离子的能量为5KeV〜20KeV,注入剂量为5E14cnT2〜4E15cnT2。 3. The process of suppressing gate PMOS device 1 according to polysilicon depletion method as claimed in claim wherein: in step two nitrogen ion implantation energy is 5KeV~20KeV, an implantation dose of 5E14cnT2~4E15cnT2.
Description  translated from Chinese

抑制PMOS器件工艺中栅极多晶硅耗尽的方法 PMOS devices inhibit gate process polysilicon depletion method

技术领域 FIELD

[0001] 本发明涉及一种半导体集成电路制造工艺方法,特别是涉及一种抑制PMOS工艺中栅极多晶娃耗尽(Poly Depletion Effects)的方法。 [0001] The present invention relates to a process for manufacturing a semiconductor integrated circuit, particularly to a process of inhibiting PMOS gate polycrystalline baby depletion (Poly Depletion Effects) method.

背景技术 BACKGROUND

[0002] 现有工艺中,为了方便于NMOS器件集成,PMOS器件的栅极多晶硅采用和NMOS器件的栅极多晶硅相同的掺杂条件,即都为N型掺杂且都要求重掺杂,PMOS器件的栅极多晶娃N型掺杂后,必须在沟道区形成一P型埋沟(buried channel)才能解决N型栅极多晶娃造成的阈值电压(Vt)较高的问题,P型埋沟的引入又会产生较大的漏电流问题。 [0002] The prior art, in order to facilitate the integration of the NMOS device, the gate of PMOS devices using polysilicon and the polysilicon gate of the NMOS device of the same doping conditions, i.e., are N-type doped and require heavy doping, PMOS baby back gate polycrystalline doped N-type device, must be formed of a P-type buried channel (buried channel) in the channel region in order to solve the threshold voltage (Vt) N-type gate polycrystalline baby problems caused by higher, P the introduction of buried channel type will have a greater leakage current problems. 为了解决现有PMOS器件的埋沟引起的较高的Vt和较大的漏电流的问题,现有技术中采用P型硼杂质来对PMOS器件的栅极多晶硅进行P型掺杂并且为重掺杂,即NMOS器件的栅极多晶硅形成N型掺杂的结构、PMOS器件的栅极多晶硅形成P型掺杂的结构,这样才能降低PMOS器件的P型栅极多晶硅和硅衬底上的沟道区之间的接触势,能达到降低PMOS器件的阈值电压和漏电的作用。 To solve the problems existing buried channel PMOS device caused higher Vt and high leakage currents, the prior art using a P-type impurity of boron to the gate polysilicon PMOS device will be P-type dopant is heavily doped and heteroaryl, i.e., the gate of the NMOS device is formed an N-type doped polysilicon structure, a gate of the PMOS device is formed a P-type doped polysilicon structure, so as to reduce the channel on the P-type silicon substrate and gate polysilicon PMOS device the contact zone between the potential, can achieve lower PMOS device threshold voltage and the drain of the role. 但是由于NMOS器件和PMOS器件要集成在一起,故要保证NMOS器件的栅极和PMOS器件的栅极能够实现良好的接触,由于P型栅极多晶硅和N型栅极多晶硅之间存在接触问题,所以现有技术中采用在P型栅极多晶硅和N型栅极多晶硅上都分别形成钨硅层(WSI,Tungsten Polycide)来实现NMOS器件的栅极和PMOS器件的栅极的良好的接触连接。 However, because the NMOS and PMOS devices to be integrated, so to ensure that the gates of NMOS devices and PMOS devices can achieve good contact, due to contact problems between the P-type and N-type gate polysilicon gate polysilicon, Therefore, the prior art uses the P-type and N-type gate polysilicon gate polysilicon layer are respectively formed of tungsten silicon (WSI, Tungsten Polycide) to achieve good contact and the gate of the PMOS device is connected to the gate of the NMOS device.

[0003] PMOS器件的栅极多晶硅采用硼掺杂以及形成钨硅层后,由于硼在钨硅层与多晶硅中溶解度大致为100:1,这样容易受后续热处理的影响,导致硼穿越钨硅层和栅极多晶硅的界面,进入到钨硅层中并在钨硅层中聚积,即最后会产生PMOS器件的栅极多晶硅耗尽(Poly Depletion Effects),从而造成PMOS器件的阈值电压漂移。 After the gate of [0003] PMOS device using boron-doped polysilicon and tungsten silicon layer is formed, due to the boron in the polysilicon layer and the tungsten silicon solubility is approximately 100: 1, so susceptible of subsequent heat treatment, resulting in a boron through the silicon layer of tungsten and gate polysilicon interface, into the silicon layer and the tungsten in the tungsten accumulated in the silicon layer, i.e. the last gate of the PMOS device will produce polysilicon depletion (Poly Depletion Effects), resulting in the threshold voltage of the PMOS device drift. 如图1所示,在娃衬底101上形成有栅氧化层102,以及栅极多晶硅层103和钨硅层104,其中栅极多晶硅层103中注入有P型硼杂质,该结构在进行后续热处理后,由于硼的在钨硅层104中的溶解度更大,故硼杂质会穿透到钨硅层104中,栅极多晶硅层103的硼杂质会大大减少,这样就会是最后形成的PMOS器件的阈值电压漂移。 1, the substrate 101 is formed on the baby has a gate oxide layer 102, and a gate polysilicon layer 103 and a tungsten silicon layer 104, wherein the gate polysilicon layer 103 is implanted with a P-type impurity of boron, the structure during the subsequent After the heat treatment, due to the greater solubility of boron in the silicon layer 104 is tungsten, it will penetrate into the tungsten boron impurity silicon layer 104, the gate polysilicon layer 103 is a boron impurities greatly reduced, this will be the final form of the PMOS value threshold voltage shift device.

[0004] 为了克服上述硼穿透到钨硅层中的情况发生,如图2所示,现有一种工艺方法是在栅极多晶硅层103进行硼掺杂后,在栅极多晶硅层103的表面形成一层钛和氮化钛(Ti/TiN)的阻挡层105,再在阻挡层105上形成钨硅层104,其中在钨硅层104上的氮化硅层106为隔离保护层。 [0004] In order to overcome the above-mentioned boron penetration into the tungsten silicon layer occurs, shown in Figure 2, the existing method is a process in the gate polysilicon layer 103 is doped with boron, the surface of the gate polysilicon layer 103 forming a layer of the barrier layer is titanium and titanium nitride (Ti / TiN) 105, and then the barrier layer 105 is formed on the silicon layer 104 of tungsten, wherein the tungsten on the silicon layer 104 of silicon nitride layer 106 as a protective layer between. 即现有方法利用阻挡层105来阻止栅极多晶硅103中的硼杂质在加热后向钨硅层104中渗透聚集。 I.e., the conventional method utilizing the barrier layer 105 to prevent the gate polysilicon 103 boron impurities, after heating aggregates to penetrate the silicon layer 104 of tungsten. 虽然上述方法能够抑制栅极多晶硅耗尽发生,但是新引入的钛很容易在后续的栅极多晶娃的再氧化(Re-oxidation)工艺被氧化而发生膨胀,最后造成球形凸起(pilling),这会对栅极结构的形貌影响很大,不利于器件的性能稳定。 While the above method can suppress the gate polysilicon depletion occurs, but it is easy to titanium newly introduced in the subsequent re-oxidation of polycrystalline baby gate (Re-oxidation) process is oxidized to swell, finally resulting spherical projections (pilling) the morphology of the impact this will have a big gate structure is not conducive to stable performance of the device. 同时,钛的引入,也对工艺线上的产品存在金属离子污染的风险。 At the same time, the introduction of titanium, but also on the process line of metal ion contamination of the product risk exists.

发明内容 SUMMARY

[0005] 本发明所要解决的技术问题是提供一种抑制PMOS器件工艺中栅极多晶硅耗尽的方法,能抑制PMOS器件的栅极多晶硅中的硼穿透到钨硅层中,使PMOS器件的阈值电压稳定。 [0005] The technical problem to be solved by the present invention is to provide a PMOS gate polysilicon depletion device process method of inhibiting, to inhibit gate polysilicon PMOS device in boron penetration into the tungsten silicon layer, so that the PMOS device Threshold voltage stability.

[0006] 为解决上述技术问题,本发明提供的抑制PMOS器件工艺中栅极多晶硅耗尽的方法包括如下步骤: [0006] In order to solve the above technical problems, PMOS device, the gate polysilicon depletion method of inhibiting the process of the present invention comprises the steps of:

[0007] 步骤一、在硅衬底上形成栅极多晶硅后,在所述栅极多晶硅中注入硼离子,使所述栅极多晶硅呈P型掺杂结构。 After [0007] Step A, in the gate polysilicon is formed on the silicon substrate, boron ions are implanted in the polysilicon gate electrode, so that the form of the P-type gate polysilicon doping structure.

[0008] 步骤二、在硼离子注入之后,在所述栅极多晶硅表面进行氮离子注入,在所述栅极多晶娃表面形成一层氮化膜。 [0008] Step two, after ion implantation of boron in the gate polysilicon surface nitrogen ion implantation, at the gate of polycrystalline silicon nitride film formed on the surface layer of the baby.

[0009] 步骤三、在氮离子注入后的所述栅极多晶硅的表面形成钨硅层,由所述钨硅层和所述栅极多晶硅组成所述PMOS器件的栅极。 [0009] Step three, nitrogen ion implantation in the gate polysilicon formed on the surface after a tungsten silicon layer, a gate of the PMOS device by the tungsten silicon layer and the gate polysilicon.

[0010] 进一步的改进是,步骤一中的注入硼离子的能量为3KeV〜8Kev,注入剂量为lE15cm2 〜lE16cm2。 [0010] Further improvement is that the energy of boron ions implanted in step one is 3KeV~8Kev, an implantation dose of lE15cm2 ~lE16cm2.

[0011] 进一步的改进是,步骤二中的注入氮离子的能量为5KeV〜20KeV,注入剂量为5E14cm2 〜4E15cm2。 [0011] Further improvement is that the energy of nitrogen ions implanted in step II is 5KeV~20KeV, an implantation dose of 5E14cm2 ~4E15cm2.

[0012] 本发明方法通过在PMOS器件的栅极多晶硅硼注入之后,再进行氮离子注入,能在栅极多晶硅表面形成一层致密的氮化膜,该氮化膜能够阻止硼向栅极多晶硅的表面扩散,能够降低在后续热过程中促使硼渗透到钨硅层中的风险,从而能有效抑制PMOS器件工艺中硼穿透到WSI层中而引起的栅极多晶硅耗尽现象的发生,使PMOS器件的阈值电压稳定。 [0012] The method of the present invention after the gate polysilicon by boron implantation PMOS devices, and then nitrogen ion implantation, can be a dense nitride film is formed on the surface of the polysilicon gate electrode, which prevents the boron nitride film to the gate polysilicon surface diffusion, can be reduced to promote boron penetration into the tungsten silicon layer risk in subsequent thermal process, which can effectively inhibit the PMOS devices in the process of boron penetration into the gate WSI layer polysilicon depletion caused by the occurrence of so the threshold voltage of the PMOS device stability.

附图说明 Brief Description

[0013] 下面结合附图和具体实施方式对本发明作进一步详细的说明: [0013] below with reference to the accompanying drawings and specific embodiments of the present invention will be further described in detail:

[0014] 图1是现有PMOS器件带有钨硅层和多晶硅层的栅极结构; [0014] FIG. 1 is a conventional silicon PMOS device having a tungsten layer and a polysilicon layer gate structure;

[0015] 图2是现有PMOS器件带有钨硅层、阻挡层和多晶硅层的栅极结构; [0015] FIG. 2 is a conventional silicon PMOS device having a tungsten layer, a barrier layer and a polysilicon layer gate structure;

[0016] 图3是本发明实施例方法的流程图; [0016] FIG. 3 is a flowchart of a method embodiment of the invention;

[0017] 图4A-图4C是本发明实施例方法各步骤中器件结构图。 [0017] Figure 4A- 4C is a method, the steps in example device structure of Figure embodiment of the present invention.

具体实施方式 DETAILED DESCRIPTION

[0018] 如图3所示,是本发明实施例方法的流程图;本发明实施例抑制PMOS器件工艺中栅极多晶硅耗尽的方法包括如下步骤: [0018] Figure 3 is a flowchart of a method embodiment of the invention; Example suppressing gate PMOS devices polysilicon depletion process method comprising the steps of the present invention:

[0019] 步骤一、如图4A所示,在硅衬底I上依次形成栅介质层2和栅极多晶硅3,其中栅介质层I能为一氧化层。 [0019] Step one, 4A, I sequentially on a silicon substrate forming a gate dielectric layer 2 and the gate polysilicon 3, wherein the gate dielectric layer is an oxide layer I can. 在形成栅极多晶硅3后,在PMOS器件形成区域的所述栅极多晶硅3中注入硼离子,注入硼离子的能量为3KeV〜8Kev,注入剂量为lE15cm_2〜lE16cm_2,使所述PMOS器件形成区域的所述栅极多晶硅3呈P型掺杂结构。 3 after forming a gate polysilicon PMOS device is formed in the gate polysilicon region 3, the ion implantation of boron, boron ion implantation energy is 3KeV~8Kev, an implantation dose of lE15cm_2~lE16cm_2, so that the formation region of the PMOS device The gate polysilicon structure 3 has a P-type doping.

[0020] 步骤二、如图4A所示,在硼离子注入之后在所述PMOS器件形成区域的所述栅极多晶硅3表面进行氮离子注入,注入氮离子的能量为5KeV〜20KeV,注入剂量为5E14cm_2〜4E15cm_2。 [0020] Step two, shown in Figure 4A, after the ion implantation of boron in the PMOS device is formed of the polysilicon gate region surface 3 nitrogen ion implantation, nitrogen ion implantation energy is 5KeV~20KeV, an implantation dose of 5E14cm_2~4E15cm_2. 如图4B所示,氮离子注入之后,在所述栅极多晶硅3表面形成一层致密的氮化膜 4B, after nitrogen ion implantation, the surface 3 of the gate polysilicon layer of dense silicon nitride film is formed

3a ο 3a ο

[0021] 步骤三、如图4C所示,在所述栅极多晶硅3的表面形成钨硅层4,对所述钨硅层4和所述栅极多晶硅3进行光刻刻蚀,由光刻刻蚀后的位于所述PMOS器件形成区域的所述钨硅层4和所述栅极多晶硅3的叠成组成所述PMOS器件的栅极。 [0021] Step three, shown in Figure 4C, the surface of the gate polysilicon layer 3 is formed of a tungsten silicon 4, a silicon layer of said tungsten and said gate polysilicon 3 4 photolithographic etching, by photolithography 4 and the polysilicon gate of the PMOS device is folded in the composition 3 after etching the gate PMOS device is formed in said region of said tungsten silicon layer. 其中由于所述栅极多晶硅3表面形成有氮化膜3a,该氮化膜3a能够降低硼掺杂原子的扩散速率,阻止硼向栅极多晶硅3的表面扩散,能够降低在后续热过程中促使硼渗透到钨硅层中的风险,从而能有效抑制PMOS器件工艺中栅极多晶硅3耗尽的发生,使PMOS器件的阈值电压稳定。 Due to 3 wherein the surface of said gate polysilicon nitride film formed 3a, 3a of the nitride film can reduce the rate of diffusion of the boron dopant atoms, boron diffusion to the surface of the gate stop 3 of the polysilicon can be reduced in the subsequent thermal process to promote boron penetration into the tungsten silicon layer risk, which can effectively inhibit the process of gate polysilicon PMOS device 3 depletion occurs, the threshold voltage of the PMOS device stability.

[0022] 之后在PMOS器件的栅极的侧面形成侧墙,并在所述栅极两侧的所述硅衬底I中形成PMOS器件的源漏区。 [0022] After the sides of the gate of the PMOS device is formed spacers and forming source and drain regions of the PMOS device I in the silicon substrate on both sides of the gate.

[0023] PMOS器件一般和NMOS器件集成在一起形成,在形成NMOS器件的区域中,NMOS器件的栅极多晶硅采用N型掺杂,在栅极多晶硅上也形成有钨硅层。 [0023] PMOS devices and NMOS devices are generally integrated together to form, in the region forming the NMOS device, the gate of the NMOS device using an N-type doped polysilicon, the gate polysilicon is also formed with a tungsten silicon layer. PMOS器件和NMOS器件集成在一起时,通过钨硅层实现器件之间的栅极的连接。 When the PMOS and NMOS devices integrated together to achieve the connection means between the gate by a tungsten silicon layer.

[0024] 以上通过具体实施例对本发明进行了详细的说明,但这些并非构成对本发明的限制。 [0024] By the above specific embodiments of the present invention has been described in detail, but these are not construed as limiting the present invention. 在不脱离本发明原理的情况下,本领域的技术人员还可做出许多变形和改进,这些也应视为本发明的保护范围。 Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be regarded as the protection scope of the present invention.

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Classifications
International ClassificationH01L21/336, H01L21/28
Cooperative ClassificationH01L21/28044
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