CN103605064A - Method for preventing electric leakage of probe test carrier - Google Patents
Method for preventing electric leakage of probe test carrier Download PDFInfo
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- CN103605064A CN103605064A CN201310505133.XA CN201310505133A CN103605064A CN 103605064 A CN103605064 A CN 103605064A CN 201310505133 A CN201310505133 A CN 201310505133A CN 103605064 A CN103605064 A CN 103605064A
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Abstract
The invention discloses a method for preventing electric leakage of a probe test carrier. The method comprises the following steps: S1, providing a to-be-tested device; S2, placing the to-be-tested device on a probe test carrier in an insulating and isolating manner; S3, carrying out probe scanning on a to-be-tested area of the to-be-tested device to obtain a feature image; S4, respectively point-pressing two probes on any two well contact electrodes of the to-be-tested device according to the feature image and checking and adjusting the two probes to enable the two probes to be in good contact with the two well contact electrodes; and S5, moving one of the probes out of the corresponding well contact electrode, point-pressing the probe on a to-be-tested electrode of the to-be-tested device, setting the bias voltage of the well contact electrode point-pressed by the other probe to zero and testing the to-be-tested electrode of the to-be-tested device. The method of the invention enables test of the to-be-tested device, especially, test of leakage current to be carried out more accurately and greatly improves the reliability of test data.
Description
Technical field
The present invention relates to semiconductor test technical field, relate in particular to the test of atomic force nano-probe, specifically a kind of method that prevents the electric leakage of probe test objective table.
Background technology
Atomic force nano-probe (Atomic Force nano-Probe, AFP) test is when confirming that whether probe contacts well with test electrode, will the electric leakage to objective table based on device under test, when the electric leakage that obtains when probe test is identical with ideal state, judge that probe contact is good, thereby make the data of test there is reliability, repeatability.But the drawback of this principle is, this electric leakage all exists in the overall process of test, when needs judge element leakage failure mechanism, the data of leakage current will be no longer accurate, take field effect transistor as example, the electric current that source, leakage, grid, trap detect and non-vanishing, proves and really has electric current flow to objective table and cannot effectively be collected by probe from the substrate of device under test.Current data is as following table:
| IS | IG | ID | IW |
| 6.58E-10 | 5E-14 | 7.27E-10 | -3.5E-07 |
In upper table, IS, IG, ID, IW are respectively the electric current of source (source), grid (gate), leakage (drain), trap (well) four utmost points, visible four electric current sums are also non-vanishing, and IW trap electric current is large especially, illustrate that trap process silicon substrate is to existing the strong electric leakage of 350nA to leak between objective table, this electric leakage is not accurate enough and reliable by the test data that causes device under test.Therefore, how to prevent that the electric current in the substrate of device under test from leaking by probe test objective table, affecting test data accuracy is problem demanding prompt solution.
Chinese patent (publication number: CN102109569A) disclose a kind of method for dielectric breakdown test on gate oxide adopting, comprised the following steps: choose the test probe for testing in the probe in probe; Described test probe is connected with test machine, and is connected current-limiting resistance on the connecting path between test probe and test machine; By on described test probe engaged test sample with the solder joint of gate oxide conducting; By described test machine, to the gate oxide in described specimen, apply from zero volt and start the linear voltage increasing in time, meanwhile record the current value on gate oxide under each magnitude of voltage, until the current value measuring increases to certain threshold value, represent that gate oxide is breakdown.The damage of the larger leakage current that the probe that this invention provides and method for dielectric breakdown test on gate oxide adopting produce when when test can prevent that gate oxide is breakdown effectively to probe and test machine, and can guarantee to increase and after current-limiting resistance, still can accurately test out the voltage breakdown of gate oxide.
Chinese patent (publication number: CN101424705A) disclose a kind of probe column, for wafer sort, comprised a: circular body, dispose LCD test section and I/O test section, and circular body has lower of a body seat of honour and a body; Most group's probe aperture, are configured in LCD test section and I/O test section, vertically run through lower of the body seat of honour and body simultaneously; And most group's test probes, be configured in etc. in probe aperture, to pass through the test signal of circular body; Most group's ground holes are configured in I/O test section; Most group's grounding pins, are embedded in one of them most group's ground holes of lower of the body seat of honour and body in close-fitting mode, and electrically conduct to circular body, with by noise and the leakage current ground connection of the test probe of vicinity; Most group's spaced rings, make with insulating material, are disposed at the end of probe aperture, with fixing test probe, in circular body, and provide being electrically insulated of test probe and circular body.
Electric current in above-mentioned two patents the unexposed substrate that how to solve device under test in prior art leaks by probe test objective table, affects the problem of test data accuracy.
Summary of the invention
Problem for above-mentioned existence, the present invention discloses a kind of method that prevents the electric leakage of probe test objective table, by the isolation to device under test and probe test objective table, effectively overcome the electric current in the substrate of device under test in prior art and leaked by probe test objective table, affected the problem of test data accuracy; In addition, by trap contact electrode is carried out to zero potential biasing, also effectively overcome due to after device under test and the isolation of probe test objective table, the contact of skin peace electric current (pico current) detector probe is difficult to the problem realizing.
To achieve these goals, the present invention adopts following technical scheme:
Prevent a method for probe test objective table electric leakage, be applied to, in the test of atomic force nano-probe, wherein, adopt following steps:
S1, provides a device under test;
S2, adopts the mode of insulation isolation to be placed on probe test objective table described device under test;
S3, carries out probe scanning to the region to be measured of described device under test, obtains a feature image;
S4, puts two probes respectively on any two the trap contact electrodes that are pressed in described device under test according to described feature image, checks and adjust two probes itself and two trap contact electrodes are all contacted well;
S5, will be wherein a probe from trap contact electrode, remove, and point is pressed on the electrode to be measured of described device under test, the bias voltage of the trap contact electrode that then another root probe presses is set to zero volt spy, then tests the electrode to be measured of described device under test.
The above-mentioned method that prevents the electric leakage of probe test objective table, wherein, in described step S1, the described device under test providing is by going the method for level to be ground to layer to be measured.
The above-mentioned method that prevents the electric leakage of probe test objective table, wherein, in described step S2, adopt the mode of insulation isolation to be specially: the bottom of described device under test to be placed on described probe test objective table after by insulation viscosity material adhesion one chip fragment, the bottom of device under test and the insulation of described probe test objective table are isolated.
The above-mentioned method that prevents the electric leakage of probe test objective table, wherein, in described step S4, the region to be measured of described device under test is provided with N trap contact electrode, and N is natural number; Checking and adjusting two probes all contacts well itself and two trap contact electrodes, concrete grammar is: check the skin peace electric current being pressed in respectively between two probes on two trap contact electrodes, and adjust the dynamics that presses and the position of two probes, when contact is good, obtain short-circuit current curve and skin peace electric current reaches maximal value.
The above-mentioned method that prevents the electric leakage of probe test objective table, wherein, the electrode to be measured of described device under test comprises source, leakage, gate electrode.
The above-mentioned method that prevents the electric leakage of probe test objective table, wherein, described device under test comprises integrated circuit (IC)-components.
The above-mentioned method that prevents the electric leakage of probe test objective table, wherein, described device under test comprises floating hollow structure semiconductor devices.
The above-mentioned method that prevents the electric leakage of probe test objective table, wherein, described floating hollow structure semiconductor devices comprises SOI device, electrically programmable fuse and polysilicon gate.
Tool of the present invention has the following advantages or beneficial effect:
1. the mode of device under test being isolated by insulation is placed on probe test objective table, solved the substrate of device under test to the electric leakage of probe test objective table, thereby the test that the makes device under test especially test of leakage current can be carried out more accurately, has greatly improved the reliability of test data.
2. first probe points is pressed on the trap contact electrode easily pressing, and this trap contact electrode is carried out to zero potential biasing, thereby solved after device under test and the isolation of probe test objective table, thereby cannot detect the problem that skin peace electric current cannot judge probe contact condition.
3. method of the present invention can be applied to SOI(Silicon-On-Insulator, the silicon in dielectric substrate) device, E-fuse(electrically programmable fuse) and Poly Gate(polysilicon gate) etc. floating sky (floating) structure.
4. because the probe Main Function on trap contact electrode is that trap contact electrode arranges bias voltage, therefore do not need the best new probe of situation (Class A), can use the probe of thick (feature image is inaccurate) of surface oxidized (contact resistance is large) or needle point, thereby save testing cost.
Concrete accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, the present invention and feature thereof, profile and advantage will become more apparent.In whole accompanying drawings, identical mark is indicated identical part.Can proportionally not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 is the structural representation of device under test and probe test objective table insulation isolation in first embodiment of the invention;
Fig. 2 is the structural representation of device under test in first embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
The first embodiment of the present invention relates to a kind of method that prevents the electric leakage of probe test objective table, is applied to, in the test of atomic force nano-probe, wherein, adopt following steps:
S1, provides a device under test, and device under test is by going the method for level to be ground to layer to be measured.
S2, adopts the mode of insulation isolation to be placed on probe test objective table device under test, adopt the mode of insulation isolation to be specially: insulation cohesive material is passed through to (as double faced adhesive tape in the bottom of device under test, solid gum, liquid glue etc.) be placed on probe test objective table after adhering to a chip fragment, make bottom and the probe test objective table insulation isolation of device under test, as shown in Figure 1, device under test and chip fragment are fixed together by insulation cohesive material, this chip fragment is selected all smooth fragments of front and back, thus, probe test objective table just can firmly be fixed chip fragment by inhaling the mode of vacuum, thereby fixing device under test, the slip of device under test while preventing probe test, make test result more accurate.
Present embodiment is isolated device under test mode by insulation is placed on probe test objective table, solved the substrate of device under test to the electric leakage of probe test objective table, thereby the test that the makes device under test especially test of leakage current can be carried out more accurately, has greatly improved the reliability of test data.If but substrate and the probe test objective table of isolation device under test cannot detect thereby can produce the problem that skin peace electric current cannot judge probe contact condition, the following steps of present embodiment can address this problem.
S3, carries out probe scanning to the region to be measured of device under test, obtains a feature image.
S4, puts two probes respectively on any two the trap contact electrodes that are pressed in device under test according to feature image, checks and adjust two probes itself and two trap contact electrodes are all contacted well; The region to be measured of device under test is provided with N trap contact electrode 11, N is natural number, and trap contact electrode 11 is all positioned at well region, as shown in Figure 2, also comprise lay respectively at source electrode 2, drain 3, the source of grid 4, leakage, grid three utmost point electrodes (21,31,41), and shallow channel isolation area (STI) 5; Checking and adjusting two probes all contacts well itself and two trap contact electrodes, concrete grammar is: check the skin peace electric current being pressed in respectively between two probes on two trap contact electrodes, and adjust the dynamics that presses and the position of two probes, when contact is good, obtain short-circuit current curve and skin peace electric current reaches maximal value; Wherein, two pins of short-circuit current curve proof have all successfully been pressed on trap contact electrode, and skin peace electric current reaches maximal value and illustrates that contact is good.
S5, will be wherein a probe from trap contact electrode, remove, and point is pressed on the electrode to be measured of device under test, the bias voltage of the trap contact electrode that then another root probe presses is set to zero volt spy, then tests the electrode to be measured of device under test.The electrode to be measured of device under test is tested according to classic method, and other three probes are put on the source that is pressed in, leakage, gate electrode respectively, completes corresponding test.The bias voltage of trap contact electrode is set to after zero volt spy (GND), has played the effect of skin peace level drain current path in original test, so the lower pin leaking for source is identical with original testing process.
Present embodiment is first pressed in probe points on the trap contact electrode easily pressing, and this trap contact electrode is carried out to zero potential biasing, thereby by after device under test and the isolation of probe test objective table, can detect accurately skin peace electric current and judge probe contact condition.
Wherein, the electrode to be measured of device under test comprises source, leakage, gate electrode.Device under test comprises integrated circuit (IC)-components, as CMOS, PN junction; Also comprise floating hollow structure semiconductor devices, as E-fuse, Poly Gate.
The step of the whole bag of tricks is divided above, just in order being described clearly, can to merge into a step or some step is split while realizing, and is decomposed into a plurality of steps, as long as comprise identical logical relation, all in the protection domain of this patent; To adding inessential modification in algorithm or in flow process or introducing inessential design, but the core design that does not change its algorithm and flow process is all in the protection domain of this patent.
The second embodiment of the present invention relates to a kind of method that prevents probe test objective table electric leakage, and present embodiment and the first embodiment are roughly the same, and its difference is, the device under test that present embodiment provides is SOI device.
Thereby, in step S2, adopt the mode of insulation isolation to be placed on probe test objective table device under test, because the substrate of SOI device is dielectric substrate, therefore it is directly placed on probe test objective table, just can makes bottom and the probe test objective table insulation isolation of device under test.
For last two embodiments, for example, adopt the device under test of 55nm technology node, test obtains the electric leakage data as following table:
| IS | IG | ID | IW |
| 3.11E-10 | -1E-14 | 3.82E-10 | -6.9E-10 |
As can be seen here, the current summation of four electrodes is zero, proves that method of the present invention can effectively remove the electric leakage from the substrate of device under test to probe test objective table.Because the probe Main Function on trap contact electrode is that trap contact electrode arranges bias voltage, therefore do not need the best new probe of situation (Class A), can use the probe of thick (feature image is inaccurate) of surface oxidized (contact resistance is large) or needle point, thereby save testing cost.
It should be appreciated by those skilled in the art that those skilled in the art can realize variation example in conjunction with prior art and above-described embodiment, such variation example does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (8)
1. prevent a method for probe test objective table electric leakage, be applied to, in the test of atomic force nano-probe, it is characterized in that, adopt following steps:
S1, provides a device under test;
S2, adopts the mode of insulation isolation to be placed on probe test objective table described device under test;
S3, carries out probe scanning to the region to be measured of described device under test, obtains a feature image;
S4, puts two probes respectively on any two the trap contact electrodes that are pressed in described device under test according to described feature image, checks and adjust two probes itself and two trap contact electrodes are all contacted well;
S5, will be wherein a probe from trap contact electrode, remove, and point is pressed on the electrode to be measured of described device under test, the bias voltage of the trap contact electrode that then another root probe presses is set to zero volt spy, then tests the electrode to be measured of described device under test.
2. the method that prevents the electric leakage of probe test objective table according to claim 1, is characterized in that, in described step S1, the described device under test providing is by going the method for level to be ground to layer to be measured.
3. the method that prevents probe test objective table electric leakage according to claim 1, it is characterized in that, in described step S2, adopt the mode of insulation isolation to be specially: the bottom of described device under test to be placed on described probe test objective table after by insulation viscosity material adhesion one chip fragment, the bottom of device under test and the insulation of described probe test objective table are isolated.
4. the method that prevents the electric leakage of probe test objective table according to claim 1, is characterized in that, in described step S4, the region to be measured of described device under test is provided with N trap contact electrode, and N is natural number; Checking and adjusting two probes all contacts well itself and two trap contact electrodes, concrete grammar is: check the skin peace electric current being pressed in respectively between two probes on two trap contact electrodes, and adjust the dynamics that presses and the position of two probes, when contact is good, obtain short-circuit current curve and skin peace electric current reaches maximal value.
5. the method that prevents the electric leakage of probe test objective table according to claim 1, is characterized in that, the electrode to be measured of described device under test comprises source, leakage, gate electrode.
6. according to the method that prevents the electric leakage of probe test objective table described in claim 1-5 any one, it is characterized in that, described device under test comprises integrated circuit (IC)-components.
7. according to the method that prevents the electric leakage of probe test objective table described in claim 1 any one, it is characterized in that, described device under test comprises floating hollow structure semiconductor devices.
8. the method that prevents the electric leakage of probe test objective table according to claim 7, is characterized in that, described floating hollow structure semiconductor devices comprises SOI device, electrically programmable fuse and polysilicon gate.
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| CN106877945A (en) * | 2015-12-13 | 2017-06-20 | 航天信息股份有限公司 | The method for improving the simulation test percent of pass based on NFC Forum specifications |
| CN107833844A (en) * | 2017-11-21 | 2018-03-23 | 长江存储科技有限责任公司 | A kind of method leaked electricity between differentiation PMOS grids and source-drain electrode or N traps |
| WO2019085101A1 (en) * | 2017-11-06 | 2019-05-09 | 武汉华星光电半导体显示技术有限公司 | Electrical property testing method |
| CN110261753A (en) * | 2019-05-06 | 2019-09-20 | 长江存储科技有限责任公司 | Semiconductor device failure analysis method |
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Cited By (4)
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