CN103531446A - Method for preparing interconnected structure of metal hard mask layer and copper - Google Patents
Method for preparing interconnected structure of metal hard mask layer and copper Download PDFInfo
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- CN103531446A CN103531446A CN201310491825.3A CN201310491825A CN103531446A CN 103531446 A CN103531446 A CN 103531446A CN 201310491825 A CN201310491825 A CN 201310491825A CN 103531446 A CN103531446 A CN 103531446A
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- hard mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
The invention provides a method for preparing an interconnected structure of a metal hard mask layer and copper. A metal nitride with a certain thickness is deposited on a semi-conductor substrate, and thermal annealing nitrogen treatment and thermal reflow treatment are carried out on the metal nitride to form the metal hard mask layer. Sufficient nitrogen reaction and shrinkage can be carried out in the metal nitride through the thermal annealing nitrogen treatment and the thermal reflow treatment to produce trend stretching stress, so that the flatness of the metal hard mask layer can be effectively improved without influencing the electric resistivity evenness of the metal hard mask layer. Meanwhile, the stress of the metal hard mask layer is fully released and reduced, so that the possibility that a film below the metal hard mask layer is deformed due to the high stress of the metal hard mask layer is lowered, and the quality of the film below the metal hard mask layer is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to the preparation method of a kind of metal hard mask layer and copper interconnection structure.
Background technology
At 0.13 μ m and more advanced last part technology, copper-connection is due to lower resistivity and better deelectric transferred performance and by extensively as aluminium, interconnection substitutes.Completing of copper wiring technique can adopt the method (conventionally adopting physical vapour deposition (PVD) PVD method to prepare titanium nitride TiN film) of metal hard mask layer to realize.Adopt this technique can reduce the damage that low-k interlayer dielectric medium causes in dry method moment process, reduced the consumption of photoresistance, and metal hard mask layer is sacrifice layer, can in final product, not retain, thereby this technique is widely used in the copper-connection below 65nm.
But find in actual production process, the stress of metal hard mask layer is generally very high, be about-1.4GPa of the stress of titanium nitride TiN film for example, the metal hard mask layer with higher stress can produce certain effect (as shown by the arrows in Figure 1 to the low dielectric constant films of its below, the effect of low dielectric constant films of TiN film to its below) cause its deform (as shown in Figure 1), thereby affect the yield of product.
The method addressing this problem is at present adjusted plated metal hard mask layer thin film parameter for passing through, and changes the stress of film, and then reduces this film for the effect of its below low dielectric constant films power, improves product yield.Yet, adjustment to metal hard mask layer thin film deposition parameter, although the stress of film is reduced to some extent, but make the resistivity evenness of this film affect to some extent (for example, after deposition parameter is adjusted, the resistivity evenness of TiN film is increased to more than 8% from 2%), and then can have influence on its follow-up processing procedure such as etching.Therefore, need a kind of method can either reduce the stress of this film, can make again other performances of film not be subject to too much influence.
Summary of the invention
The object of the present invention is to provide the preparation method of a kind of metal hard mask layer and copper interconnection structure, can fully reduce the stress of metal hard mask layer, thereby reduce its lower film owing to being subject to the heavily stressed quality that produces the possibility of metaboly generation and improved metal hard mask layer.
For addressing the above problem, the present invention proposes a kind of preparation method of metal hard mask layer, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, deposits certain thickness metal nitride;
Described metal nitride is carried out to thermal annealing nitrogen treatment and hot reflux processing, form the metal hard mask layer of predefine thickness.
Further, described metal hard mask layer is titanium nitride and/or tantalum nitride.
Further, the technique of plated metal hard mask layer is CVD or MOCVD or PVD or ALD.
Further, described metal hard mask layer thickness is
Further, described thermal annealing nitrogen treatment skill is that rapid thermal treatment, boiler tube are processed or laser short annealing.
Further, the carrier gas of described thermal anneal process comprises nitrogen, also comprises argon gas and/or hydrogen.
Further, the technological parameter of described thermal annealing nitrogen treatment comprises: annealing temperature is 200 ℃～400 ℃; Annealing time is 10s～100s; The flow of the nitrogen passing into is 100sccm～10000sccm, and the flow of argon gas or hydrogen is 10sccm～1000sccm.
Further, the technological parameter that described hot reflux is processed comprises: hot reflux temperature is 100 ℃～400 ℃; The hot reflux time is 100s～500s; The flow of the inert gas passing into is 100sccm～1000sccm, and described inert gas comprises argon gas or helium.
The present invention also provides a kind of preparation method of copper interconnection structure, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms successively laying, low K dielectric layer;
Adopt the preparation method of one of above-mentioned metal hard mask layer, on described low K dielectric layer, form the metal hard mask layer of predefine thickness;
On described metal hard mask layer, form cover layer;
Adopt cover layer described in single Damascus etching technics and/or dual damascene etching technics etching, metal hard mask layer, low K dielectric layer and laying, thereby in described low K dielectric layer, form layer of copper interconnection structure.
Further, described laying is nitrogenous carborundum (SiCN); Described low K dielectric layer comprise porous silicon layer (SiOCH) with and the teos layer (TEOS) of top; Described cover layer is silica.
Further, the step of described single Damascus etching technics and/or dual damascene etching technics comprises:
Raceway groove exposure, etching; Via hole exposure, etching; Remove photoresist layer; Raceway groove and via etch; Laying opening; Chemico-mechanical polishing after the inculating crystal layer deposition of raceway groove and via hole, copper are filled and filled.
Compared with prior art, the preparation method of metal hard mask layer provided by the invention and copper interconnection structure, by depositing certain thickness metal nitride and described metal nitride is carried out to thermal annealing nitrogen treatment and hot reflux processes to form metal hard mask layer in semi-conductive substrate, and thermal annealing nitrogen treatment and hot reflux processing can make metal nitride inside carry out sufficient nitridation reaction and contraction, produce the stress that trend stretches, thereby can effectively improve the evenness of metal hard mask layer, do not affect metal hard mask layer resistivity evenness, fully discharge and reduce again the stress of metal hard mask layer simultaneously, thereby reduce its lower film owing to being subject to the heavily stressed possibility that produces metaboly generation of metal hard mask layer, improved the quality of metal hard mask layer lower film.
Accompanying drawing explanation
A kind of electron-microscope scanning figure of copper interconnection structure in Fig. 1 prior art;
Fig. 2 is preparation method's flow chart of the metal hard mask layer of the specific embodiment of the invention;
Fig. 3 is preparation method's flow chart of the concrete copper interconnection structure of implementing of the present invention;
Fig. 4 A to Fig. 4 D is the device architecture schematic diagram of preparation method's flow process of the copper interconnection structure shown in Fig. 3.
Embodiment
Core concept of the present invention is the preparation method who discloses a kind of metal hard mask layer and copper interconnection structure, by depositing certain thickness metal nitride and described metal nitride is carried out to thermal annealing nitrogen treatment and hot reflux processes to form metal hard mask layer in semi-conductive substrate, and thermal annealing nitrogen treatment and hot reflux processing can make metal nitride inside carry out sufficient nitridation reaction and contraction, produce the stress that trend stretches, thereby can effectively improve the evenness of metal hard mask layer, do not affect metal hard mask layer resistivity evenness, fully discharge and reduce again the stress of metal hard mask layer simultaneously, thereby reduce its lower film owing to being subject to the heavily stressed possibility that produces metaboly generation of metal hard mask layer, improved the quality of metal hard mask layer lower film.
For object of the present invention, feature are become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described, yet the present invention can realize by different forms, should not think and just be confined to described embodiment.
Please refer to Fig. 2, the present invention proposes a kind of preparation method of metal hard mask layer, comprising:
S11, provides Semiconductor substrate, adopts CVD or MOCVD or PVD(physical vapour deposition (PVD) in described Semiconductor substrate) or ALD(ald) deposit certain thickness titanium nitride;
S12, carries out thermal annealing nitrogen treatment and hot reflux processing to described titanium nitride, forms metal hard mask layer.
Wherein, in other embodiments of the invention, metal hard mask layer can be also the composite bed that tantalum nitride or titanium nitride and tantalum nitride form.In the deposition process of step S11, a kind of method is chemical vapour deposition (CVD) (CVD) method, and it adopts titanium tetrachloride (TiCl conventionally
4) as titanium source and ammonia (NH
3) as nitrogenous source, form titanium nitride layer; Another kind method is to rely on organic metal CVD (MODCD, metallo-organic CVD) method, uses four (dimethyl ammonification) titanium (TDMAT, Ti[N (CH
3)
2]
4, tetrakis-dimethylamino titanium) form.
In step S12, the metal hard mask layer that first adopts thermal annealing nitrogenation treatment technology to form titanium nitride carries out preliminary treatment, remove impurity, effectively reduce the stress of most of metal hard mask layer, metal hard mask layer after then adopting hot reflux treatment process to thermal annealing nitrogen treatment is processed again, can be effectively and fully remove residual stress in metal hard mask layer, thereby effectively and fully reduce its lower film owing to being subject to the heavily stressed quality that produces the possibility of metaboly generation and improved its lower film of metal hard mask layer through twice processing.
Please refer to Fig. 3, the present invention also provides a kind of preparation method of copper interconnection structure, comprising:
S21, provides Semiconductor substrate, forms successively laying, low K dielectric layer in described Semiconductor substrate;
S22, adopts the preparation method of the metal hard mask layer described in S11 to S12, forms the metal hard mask layer of predefine thickness on described low K dielectric layer;
S23 forms cover layer on described metal hard mask layer;
S24, adopts cover layer described in single Damascus etching technics and/or dual damascene etching technics etching, metal hard mask layer, low K dielectric layer and laying, thereby in described low K dielectric layer, forms layer of copper interconnection structure.
Below in conjunction with accompanying drawing 3 and accompanying drawing 4A to 4D, describe the preparation method of copper interconnection structure of the present invention in detail.
Please refer to Fig. 3 and Fig. 4 A, in step S21, the Semiconductor substrate 400 providing is X-1 layer copper interconnection structure, comprises M
x-1metal level, in described Semiconductor substrate 400, form successively laying 401,
Low K dielectric layer 402; Wherein, described laying 401 is nitrogenous carborundum (SiCN); Described low K dielectric layer 402 comprise porous silicon layer (SiOCH) with and the teos layer (TEOS) of top.
Please refer to Fig. 3 and Fig. 4 A, in step S22, the preparation method of the metal hard mask layer described in employing S11 to S12, on described low K dielectric layer 402, form the metal hard mask layer 403 of predefine thickness, wherein in the preparation method of the metal hard mask layer described in S11 to S12, by CVD or MOCVD or PVD or ALD depositing operation depositing titanium nitride, form metal hard mask layer.The thickness that forms metal hard mask layer is
be for example
thermal annealing nitrogen treatment can be rapid thermal treatment, boiler tube technique or laser short annealing, mixed carrier gas when thermal annealing desalination is processed comprises nitrogen, also comprise argon gas and/or hydrogen, the technological parameter of thermal annealing nitrogen treatment comprises: annealing temperature is 200 ℃～400 ℃; Annealing time is 10s～100s; The flow of the nitrogen passing into is 100sccm～10000sccm, and the flow of argon gas or hydrogen is 10sccm～1000sccm.The technological parameter that hot reflux is processed can be adjusted according to the deposition process parameters of metal hard mask layer, thickness and thermal annealing nitrogenation treatment technology parameter adaptation, and preferably, hot reflux temperature is 100 ℃～400 ℃; The hot reflux time is 100s～500s; The flow of the inert gas passing into is 100sccm～1000sccm, and described inert gas comprises argon gas or helium.
Please refer to Fig. 3 and Fig. 4 A, in step S23, on described metal hard mask layer 403, form cover layer 404, wherein, described cover layer 404 is silica.
Please refer to Fig. 3 and Fig. 4 B to 4D, in step S24, can adopt single Damascus etching technics and/or each rete of dual damascene etching technics etching, to form layer of copper interconnection structure in described low K dielectric layer 402.For example the detailed process of dual damascene etching technics is as follows:
Please refer to Fig. 4 B, on described metal hard mask layer 404, be coated with photoresist layer 405, photoresist layer 405 comprises, photoresist layer 405 comprises bottom anti-reflection layer BARC and photoresist PR layer; Then carry out raceway groove exposure, etching technics, first to photoresist layer 405 expose, the photoetching process such as development, etching, form with M
xthe photoresist layer of the patterning of layer metal pattern, follows etching cover layer 404, metal hard mask layer 403, low K dielectric layer 402 successively, or etching cover layer 404 and over etching metal hard mask layer 403, by the M on photoresist layer 405
xlayer metal pattern transferred on cover layer 404, metal hard mask layer 403, low K dielectric layer 402 successively, M
xlayer metal pattern is channel pattern;
Please refer to Fig. 4 C, remove above-mentioned photoresist layer, comprising M
xthe redeposited photoresist layer 405a of device surface of layer metal pattern, and carries out via hole exposure, etching, to new photoresist layer 405a expose, the photoetching process such as development, etching, form with via hole V
xthe photoresist layer of the patterning of pattern, then etching cover layer 404, metal hard mask layer 403, low K dielectric layer 402 successively, or etching cover layer 404 and over etching metal hard mask layer 403, by the via hole V on photoresist layer 405
xpattern is transferred on cover layer 404, metal hard mask layer 403, low K dielectric layer 402 successively;
Please refer to Fig. 4 D, remove above-mentioned new photoresist layer, and before or after removing cover layer, take metal hard mask layer as mask, according to by the M forming
xlayer metal pattern and via hole V
xpattern continues etching until laying 401 openings carry out raceway groove and via etch and laying 401 openings, thereby form raceway groove in low K dielectric layer 402, (raceway groove is for follow-up formation M
xmetal level, not shown), in low K dielectric layer 402 and laying 401, form via hole; Wherein, the aperture degree of depth of via hole extends to the M in Semiconductor substrate 400
x-1layer on surface of metal, for follow-up M
x-1metal level and M
xthe interconnection of metal level;
Please continue to refer to Fig. 4 D, in via hole and raceway groove, deposit inculating crystal layer, and carry out copper filling and fill after chemico-mechanical polishing (top flattening is to predefine M
xmetal layer thickness, generally can be planarized to the lower floor of low K dielectric layer 402), form and comprise M
xmetal level and via hole V
xnew layer of copper interconnection structure.
In other embodiments, adopting single Damascus etching technics is mainly the operation completely separately of channel etching, filling process and via etch, filling process, and its step also comprises: raceway groove exposure, etching; Via hole exposure, etching; Remove photoresist layer; Raceway groove and via etch; Laying opening; Chemico-mechanical polishing after the inculating crystal layer deposition of raceway groove and via hole, copper are filled and filled.
In sum, the preparation method of metal hard mask layer provided by the invention and copper interconnection structure, by depositing certain thickness metal nitride and described metal nitride is carried out to thermal annealing nitrogen treatment and hot reflux processes to form metal hard mask layer in semi-conductive substrate, and thermal annealing nitrogen treatment and hot reflux processing can make metal nitride inside carry out sufficient nitridation reaction and contraction, produce the stress that trend stretches, thereby can effectively improve the evenness of metal hard mask layer, do not affect metal hard mask layer resistivity evenness, fully discharge and reduce again the stress of metal hard mask layer simultaneously, thereby reduce its lower film owing to being subject to the heavily stressed possibility that produces metaboly generation of metal hard mask layer, improved the quality of metal hard mask layer lower film.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (11)
1. a preparation method for metal hard mask layer, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, deposits certain thickness metal nitride;
Described metal nitride is carried out to thermal annealing nitrogen treatment and hot reflux processing, form the metal hard mask layer of predefine thickness.
2. the preparation method of metal hard mask layer as claimed in claim 1, is characterized in that, described metal hard mask layer is titanium nitride and/or tantalum nitride.
3. the preparation method of metal hard mask layer as claimed in claim 1, is characterized in that, the technique of plated metal hard mask layer is CVD or MOCVD or PVD or ALD.
4. the preparation method of metal hard mask layer as claimed in claim 1, is characterized in that, described metal hard mask layer thickness is
5. the preparation method of metal hard mask layer as claimed in claim 1, is characterized in that, described thermal annealing nitrogen treatment is that rapid thermal treatment, boiler tube are processed or laser short annealing.
6. the preparation method of metal hard mask layer as claimed in claim 1, is characterized in that, the carrier gas of described thermal anneal process comprises nitrogen, also comprises argon gas and/or hydrogen.
7. the preparation method of metal hard mask layer as claimed in claim 1, is characterized in that, the technological parameter of described thermal annealing nitrogen treatment comprises: annealing temperature is 200 ℃～400 ℃; Annealing time is 10s～100s; The flow of the nitrogen passing into is 100sccm～10000sccm, and the flow of argon gas or hydrogen is 10sccm～1000sccm.
8. the preparation method of metal hard mask layer as claimed in claim 1, is characterized in that, the technological parameter that described hot reflux is processed comprises: hot reflux temperature is 100 ℃～400 ℃; The hot reflux time is 100s～500s; The flow of the inert gas passing into is 100sccm～1000sccm, and described inert gas comprises argon gas or helium.
9. a preparation method for copper interconnection structure, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms successively laying, low K dielectric layer;
Adopt the preparation method of the metal hard mask layer described in any one in claim 1 to 8, on described low K dielectric layer, form the metal hard mask layer of predefine thickness;
On described metal hard mask layer, form cover layer;
Adopt cover layer described in single Damascus etching technics and/or dual damascene etching technics etching, metal hard mask layer, low K dielectric layer and laying, thereby in described low K dielectric layer, form layer of copper interconnection structure.
10. the preparation method of copper interconnection structure as claimed in claim 9, is characterized in that, described laying is nitrogenous carborundum; Described low K dielectric layer comprise porous silicon layer with and the teos layer of top; Described cover layer is silica.
The preparation method of 11. copper interconnection structures as claimed in claim 9, is characterized in that, the step of described single Damascus etching technics and/or dual damascene etching technics comprises:
Raceway groove exposure, etching; Via hole exposure, etching; Remove photoresist layer; Raceway groove and via etch; Laying opening; Chemico-mechanical polishing after the inculating crystal layer deposition of raceway groove and via hole, copper are filled and filled.
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| CN201310491825.3A CN103531446A (en) | 2013-10-18 | 2013-10-18 | Method for preparing interconnected structure of metal hard mask layer and copper |
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|---|---|---|---|
| CN201310491825.3A CN103531446A (en) | 2013-10-18 | 2013-10-18 | Method for preparing interconnected structure of metal hard mask layer and copper |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010019891A1 (en) * | 1999-12-15 | 2001-09-06 | Genitech Co., Ltd. | Method of forming copper interconnections and thin films using chemical vapor deposition with catalyst |
| CN102709232A (en) * | 2012-06-21 | 2012-10-03 | 上海华力微电子有限公司 | Preparation method for metal hard mask layer applied to copper interconnection |
| CN102832167A (en) * | 2012-06-21 | 2012-12-19 | 上海华力微电子有限公司 | Preparation method of metal hard mask layer and semiconductor manufacturing method |
-
2013
- 2013-10-18 CN CN201310491825.3A patent/CN103531446A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010019891A1 (en) * | 1999-12-15 | 2001-09-06 | Genitech Co., Ltd. | Method of forming copper interconnections and thin films using chemical vapor deposition with catalyst |
| CN102709232A (en) * | 2012-06-21 | 2012-10-03 | 上海华力微电子有限公司 | Preparation method for metal hard mask layer applied to copper interconnection |
| CN102832167A (en) * | 2012-06-21 | 2012-12-19 | 上海华力微电子有限公司 | Preparation method of metal hard mask layer and semiconductor manufacturing method |
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