CN103489781A - Method for manufacturing semiconductor device by utilizing stress memory technology - Google Patents
Method for manufacturing semiconductor device by utilizing stress memory technology Download PDFInfo
- Publication number
- CN103489781A CN103489781A CN201210195636.7A CN201210195636A CN103489781A CN 103489781 A CN103489781 A CN 103489781A CN 201210195636 A CN201210195636 A CN 201210195636A CN 103489781 A CN103489781 A CN 103489781A
- Authority
- CN
- China
- Prior art keywords
- stress memory
- substrate
- stress
- side wall
- memory layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
Abstract
A method for manufacturing a semiconductor device by utilizing the stress memory technology comprises the step of providing a substrate, the step of forming a grid electrode on the substrate, the step of forming side walls on the two sides of the grid electrode, the step of injecting ions into the area, where a source and drain electrode is formed, in the substrate, the step of partially removing the side walls, the step of forming a stress memory layer covering the substrate, the grid electrode and the side walls and the step of executing thermal annealing. Due to the fact that the exerted stress is close to a channel, good device performance can be obtained; the improved stress memory layer is thicker than a stress memory layer in the prior art, therefore, higher stress can be produced, and a better gap fill effect can be obtained; due to the fact that the obtained silicon is large in non-crystallizing quantity, the stress memory effect can be enhanced, and better device performance can be obtained.
Description
Technical field
The present invention relates to a kind of technical field of manufacturing semiconductors, more precisely, the present invention relates to a kind of method that adopts stress memory technique to manufacture semiconductor device.
Background technology
Along with the development of semiconductor device technology and in proportion size dwindle, stress engineering is playing increasing effect aspect semiconductor technology and device performance.The stress memory effect is a kind of method of stress of introducing in semiconductor fabrication process.
In utilizing the semi-conductive process of stress technique manufacture PMOS, can obtain higher compression by e-SiGe and compression cover layer.
But in utilizing the semi-conductive process of stress technique manufacture NMOS, thereby be difficult to improve the semi-conductive electric property of NMOS by improve electron mobility by the tensile stress technology.For example, traditional, utilize during stress technique manufactures the semi-conductive process of NMOS, after forming the step that sidewall and source-drain electrode (S/D) inject, cover the stress memory layer and carry out the S/D annealing process on device and make to be positioned at the polysilicon gate recrystallization under it.In follow-up technique, above-mentioned stress memory layer is removed.Such method can only improve the electric property of nmos device 5-15%.But, when dimensions of semiconductor devices diminishes in proportion, the distance between grid diminishes thereupon, thereby has reduced the area of source leakage between grid and non-metallic volume thereof, also affected the gap-fill effect of stress memory layer, so stress memory is weakened the effect of NMOS semiconductor effect.
Summary of the invention
In view of above problem, the invention provides a kind of method that adopts stress memory technique to manufacture semiconductor device, comprise the following steps: a substrate is provided; Form grid on described substrate; Form side wall on described grid both sides; Implantation is carried out in the zone that will form source-drain electrode in described substrate; Part is removed described side wall; Form the stress memory layer that covers described substrate, described grid and described side wall; Carry out thermal annealing.
Further, also be included in described part and remove the ion implantation pre-amorphous step of carrying out after the step of side wall.
Further, also be included in the step that described thermal anneal step forms metal silicified layer afterwards.
Further, also be included in the step that described thermal anneal step is removed described stress memory layer afterwards.
Further, wherein said ion implantation pre-amorphous step is that the pattern that uses described Implantation step to use carries out.
Further, described device is CMOS, wherein for PMOS, adopts selectivity technique, does not carry out the step that described part is removed side wall.
In the present invention, due to the close raceway groove of the stress applied, so can obtain device performance preferably; In addition, the thickness of stress memory layer is thick than the thickness of the stress memory layer of prior art, so can bring out higher stress and obtain better gap-fill (gap fill) effect; In addition, because the decrystallized amount of resulting silicon is larger, so can strengthen the stress memory effect, obtain better device performance.
The accompanying drawing explanation
Figure 1A-1E is that employing stress memory technique of the present invention is manufactured the semiconductor structure schematic diagram.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.In order thoroughly to understand the present invention, detailed step will be proposed in following description, so that explaination the present invention proposes the stress memory technique method.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet, except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.Next, in connection with accompanying drawing, the present invention is more intactly described.
At first, as shown in Figure 1A, provide a substrate 101.Described substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Can be formed with doped region and/or isolation structure in described substrate, described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Can be formed with cmos device in described substrate, cmos device is for example transistor (for example, NMOS and/or PMOS) etc.In addition, the upper surface of described substrate also comprises the insulating barrier (not shown), and insulating barrier can comprise silica, sapphire and/or other applicable insulating material.
Form the step of polysilicon gate 102 on the CMOS zone of then, carrying out at described substrate.The method of described formation can be deposition, it comprises chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD), also can use such as the general similarity method such as sputter and physical vapour deposition (PVD) (PVD).Use in one embodiment of the invention low-pressure chemical vapor phase deposition (LPCVD) technique to form described polysilicon gate, its process conditions comprise: reacting gas is silane (SiH4), the range of flow of described silane can be 100～200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700～750 degrees centigrade; The reaction chamber internal pressure can be 250～350 milli millimetress of mercury (mTorr), as 300mTorr; Also can comprise buffer gas in described reacting gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen can be 5～20 liter/mins (slm), as 8slm, 10slm or 15slm.
Then can also carry out carrying out to described substrate the step that the lightly-doped source drain electrode is injected.
Then, form side wall 103 in described grid both sides.In one embodiment, at first on Semiconductor substrate He on grid, deposit successively the oxide layer of 50-1000 dust and the nitration case of 50-1000 dust.Then described side wall nitride layer is carried out to etching, described etching can be the directed etching perpendicular to the semiconductor substrate surface direction that the side wall nitration case is carried out, and the method for etching can be dry etching.Then described side wall oxide layer is carried out to etching, described etching can be the method with the wet etching that carries out of hydrofluoric acid solution of dilution.So just can form silica-silicon nitride side wall.
The step of Implantation is carried out in the zone 105 of then, carrying out forming source-drain electrode in described substrate 101.Can comprise by ion implantation technology and form source drain region in the Semiconductor substrate around grid.
Then, as shown in Figure 1B, the side wall that part is removed NMOS makes it have thinner shape.The method of described removal can be the method for dry etching, wet etching or its combination, and wherein dry etching comprises the combination in any of reactive ion etching (RIE), ion beam milling, plasma etching, laser cutting or these methods.Wet etching comprises the employing hydrofluoric acid solution, for example buffer oxide etch agent (BOE) or hydrofluoric acid cushioning liquid (BHF).
Wherein side wall can optionally be removed, and according to the shape selective ground of formed source-drain electrode in NMOS, removes and makes the edge near the close raceway groove of formed source-drain electrode by the side wall of the thinning outside.
And adopt selectivity technique for PMOS, do not carry out the step that described part is removed side wall.
Preferably, after described side wall part is optionally removed, carry out the step of selective ion implantation pre-amorphous (PAI).The metal silicide in subsequent step forms grid and source drain region are carried out selective ion implantation pre-amorphous, flow and the selectivity Ions Bombardment is carried out in described zone make its surface decrystallized by high energy ion, to obtain the volume of larger amorphized silicon, thereby strengthen the effect of follow-up stress memory.
Then, as shown in Figure 1 C, form the step of the stress memory layer 104 that covers described substrate and described grid.The method of described formation stress memory layer can be the method for deposition.The material of stress memory layer can be silicon nitride.In one embodiment of the invention, the stress memory layer is 350 to 450 ℃ of temperature by plasma reinforced chemical vapour deposition (PECVD) technique, power 50 is to 150W, reaction chamber pressure 4 is to 10Torr, the SiH4 flow is 50-100sccm, the NH3 flow is 400-700sccm, under the condition of N2 flow 800-1500sccm, forms.The thickness of stress memory layer can be the 200-800 dust, and its stress value is 500 to 800MPa.
Especially, the thickness of the stress memory layer in the present invention can be selected to be greater than stress memory layer thickness of the prior art and brings out higher stress with the channel region in the NMOS Semiconductor substrate.
Because formed side wall in above-mentioned steps has thinner thickness, so the stress memory layer that deposited thereon is nearer apart from groove.Therefore can bring out higher stress by the channel region in the NMOS Semiconductor substrate.
Can also be included in and form the stress memory layer step of formation buffer oxide layer on grid before, described buffer oxide layer can be avoided the stress memory layer to cause unnecessary destruction to grid and can be used as the etching stop layer of stress memory layer afterwards.
Then, carry out the step of thermal annealing.Grid and source-drain electrode area are carried out to thermal anneal process and make the stress that the stress memory layer brings out be remembered to the NMOS semiconductor device, improve the electron mobility of channel region in NMOS, thereby improve the electric property of NMOS element.Described thermal annealing can be used the annealing process that is rapidly heated, use in one embodiment the technique of samming annealing, utilize the high temperature of 900 to 1050 ℃ to activate the doping in regions and source/drain, the amorphous silicon recrystallization formed due to Implantation before making it, and the lattice structure of simultaneously repairing semiconductor substrate surface impaired in each ion implantation technology, the recrystallization of described amorphous silicon makes the substrate partial volume that closes on described stress memory layer expand, and it can significantly improve the effect of stress memory.
Wherein thermal annealing can also be the method for rapid thermal annealing or LASER HEAT annealing.What in the LASER HEAT annealing of one embodiment of the present of invention, use is carbon dioxide laser, in this process, by laser beam arc or linear scan, completes this thermal annealing process.The method of the rapid thermal annealing used in a further embodiment adopts in the admixture of gas atmosphere of NH3 under the condition of 1100 to 1150 ℃ of temperature and Ar carries out.The heating of described atmosphere with per second approximately the speed of 50 ℃ be increased to 1100 to 1150 ℃ from 800 ℃, its temperature-fall period is that the speed of per second 10-70 ℃ is down to 800 ℃.
Then, as shown in Fig. 1 D, remove the stress memory layer 104 on the nmos area territory.Can use dry etching or wet etching etching technique.
Then, as shown in Fig. 1 E, carry out the step of follow-up formation metal silicified layer 106, described metal silicified layer can be to be formed on grid and source-drain electrode.Can comprise the first step of plated metal silicide barrier layer on grid and substrate, this layer can be SiO2; Then blocking layer of metal silicide is carried out to etching and form regional corresponding substrate surface and/or grid structure surface to expose contact hole; The step of then carrying out plated metal and short annealing processing forms metal silicide at the substrate surface exposed and/or grid structure surface.
For the purpose of illustration and description, provided the above description of various aspects of the present invention.It is not intended to exclusive list or limits the invention to disclosed precise forms, and significantly, can carry out numerous modifications and variations.The present invention is intended to it will be apparent to those skilled in the art that these modifications and variations are included in the scope of the present invention be defined by the following claims.
Claims (6)
1. a method that adopts stress memory technique to manufacture semiconductor device, comprising: a substrate is provided;
Form grid on described substrate;
Form side wall on described grid both sides;
Implantation is carried out in the zone that will form source-drain electrode in described substrate;
Part is removed described side wall;
Form the stress memory layer that covers described substrate, described grid and described side wall; Carry out thermal annealing.
2. method according to claim 1, also be included in described part and remove the ion implantation pre-amorphous step of carrying out after the step of side wall.
3. method according to claim 1 and 2, also be included in the step that described thermal anneal step forms metal silicified layer afterwards.
4. method according to claim 1, also be included in the step that described thermal anneal step is removed described stress memory layer afterwards.
5. method according to claim 2, wherein said ion implantation pre-amorphous step is that the pattern that uses described Implantation step to use carries out.
6. method according to claim 1, described device is CMOS, wherein for PMOS, adopts selectivity technique, does not carry out the step that described part is removed side wall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210195636.7A CN103489781A (en) | 2012-06-13 | 2012-06-13 | Method for manufacturing semiconductor device by utilizing stress memory technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210195636.7A CN103489781A (en) | 2012-06-13 | 2012-06-13 | Method for manufacturing semiconductor device by utilizing stress memory technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103489781A true CN103489781A (en) | 2014-01-01 |
Family
ID=49829923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210195636.7A Pending CN103489781A (en) | 2012-06-13 | 2012-06-13 | Method for manufacturing semiconductor device by utilizing stress memory technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103489781A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114023651A (en) * | 2021-10-21 | 2022-02-08 | 上海华力集成电路制造有限公司 | Preparation method of NMOS (N-channel metal oxide semiconductor) transistor |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1845304A (en) * | 2005-04-08 | 2006-10-11 | 联华电子股份有限公司 | Method for making metal-oxide-semiconductor transistor |
| CN1892998A (en) * | 2005-07-06 | 2007-01-10 | 台湾积体电路制造股份有限公司 | Method of forming semiconductor structure |
| CN101197286A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Method of manufacturing metal oxide semiconductor device |
| CN101989574A (en) * | 2009-08-06 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device with strain memory action |
| CN102054695A (en) * | 2009-10-29 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for improving performance of semiconductor components |
| US20110269278A1 (en) * | 2010-04-30 | 2011-11-03 | Globalfoundries Inc. | Stress Memorization with Reduced Fringing Capacitance Based on Silicon Nitride in MOS Semiconductor Devices |
| CN102983075A (en) * | 2011-09-07 | 2013-03-20 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device applying stress approaching technology |
-
2012
- 2012-06-13 CN CN201210195636.7A patent/CN103489781A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1845304A (en) * | 2005-04-08 | 2006-10-11 | 联华电子股份有限公司 | Method for making metal-oxide-semiconductor transistor |
| CN1892998A (en) * | 2005-07-06 | 2007-01-10 | 台湾积体电路制造股份有限公司 | Method of forming semiconductor structure |
| US20070010073A1 (en) * | 2005-07-06 | 2007-01-11 | Chien-Hao Chen | Method of forming a MOS device having a strained channel region |
| CN101197286A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Method of manufacturing metal oxide semiconductor device |
| CN101989574A (en) * | 2009-08-06 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device with strain memory action |
| CN102054695A (en) * | 2009-10-29 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for improving performance of semiconductor components |
| US20110269278A1 (en) * | 2010-04-30 | 2011-11-03 | Globalfoundries Inc. | Stress Memorization with Reduced Fringing Capacitance Based on Silicon Nitride in MOS Semiconductor Devices |
| CN102983075A (en) * | 2011-09-07 | 2013-03-20 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device applying stress approaching technology |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114023651A (en) * | 2021-10-21 | 2022-02-08 | 上海华力集成电路制造有限公司 | Preparation method of NMOS (N-channel metal oxide semiconductor) transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7655987B2 (en) | Method for fabricating ultra-high tensile-stressed film and strained-silicon transistors thereof | |
| CN103545186A (en) | Method for manufacturing metal gate semiconductor device | |
| KR20110135771A (en) | Method of fabricating semiconductor integrated circuit device | |
| CN103545185A (en) | Method of producing semiconductor device by pseudo-gate | |
| JP2009283527A (en) | Semiconductor device and production method thereof | |
| CN104795362B (en) | A kind of method for making semiconductor devices | |
| CN104465486B (en) | The forming method of semiconductor devices | |
| US20120034749A1 (en) | Method for manufacturing a strained semiconductor device | |
| CN105097534B (en) | A method of making semiconductor devices | |
| CN102915971B (en) | Manufacturing method of semiconductor device | |
| CN103151258B (en) | A kind of manufacture method of semiconductor device | |
| CN101383326A (en) | Mos transistor and fabrication method thereof | |
| CN103489781A (en) | Method for manufacturing semiconductor device by utilizing stress memory technology | |
| CN103681333A (en) | Method for manufacturing semiconductor device | |
| CN108615731A (en) | A kind of semiconductor devices and its manufacturing method | |
| CN104051245B (en) | A kind of preparation method of semiconductor devices | |
| CN110098151B (en) | Semiconductor device and method of forming the same | |
| US8642435B2 (en) | Performing treatment on stressors | |
| CN108172547B (en) | Method for manufacturing semiconductor device | |
| US9219151B1 (en) | Method for manufacturing silicon nitride layer and method for manufacturing semiconductor structure applying the same | |
| CN104952725B (en) | A kind of semiconductor devices and its manufacture method | |
| CN104916588A (en) | Semiconductor device and manufacturing method thereof | |
| CN104952798B (en) | A kind of manufacturing method of semiconductor devices | |
| TWI787339B (en) | Method for manufacturing semiconductor device | |
| CN104347506A (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140101 |