CN103456707A - Semiconductor package structure and manufacturing method thereof - Google Patents

Semiconductor package structure and manufacturing method thereof Download PDF

Info

Publication number
CN103456707A
CN103456707A CN2013104003358A CN201310400335A CN103456707A CN 103456707 A CN103456707 A CN 103456707A CN 2013104003358 A CN2013104003358 A CN 2013104003358A CN 201310400335 A CN201310400335 A CN 201310400335A CN 103456707 A CN103456707 A CN 103456707A
Authority
CN
China
Prior art keywords
semiconductor element
filler
protective layer
spatial accommodation
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2013104003358A
Other languages
Chinese (zh)
Other versions
CN103456707B (en
Inventor
高金利
李长祺
赖逸少
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Publication of CN103456707A publication Critical patent/CN103456707A/en
Application granted granted Critical
Publication of CN103456707B publication Critical patent/CN103456707B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16113—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01031—Gallium [Ga]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/07—Polyamine or polyimide
    • H01L2924/07025—Polyimide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15763—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550 C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15798—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Abstract

The invention relates to a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure is provided with a semiconductor element which comprises a body, a plurality of conductive channels and at least one filler. The conductive channels penetrate the body. The filler is located in the body, wherein the coefficient of thermal expansion of the filler is different from the coefficient of thermal expansion of the body and the conductive channels. Thus, the thermal expansion coefficient of the whole semiconductor element can be adjusted, and the warping can be reduced.

Description

Semiconductor package and manufacture method thereof
Technical field
The invention relates to a kind of semiconductor package and semiconductor technology.In detail, the invention relates to a kind of semiconductor element and there is the semiconductor package of this semiconductor element, and the manufacture method of semiconductor element.
Background technology
Known stacking type encapsulating structure (for example: an intermediate plate) and a substrate comprises a chip, semiconductor element usually.This chip configuration is in this semiconductor element and be electrically connected to this semiconductor element.This semiconductor element utilizes several soldered balls to be connected to this substrate.Because the material of this semiconductor element is different from the material of this substrate, so also difference to some extent of its thermal coefficient of expansion (CTE).When this known stacking type encapsulating structure is heated, because the material of this semiconductor element is different from the thermal coefficient of expansion of this substrate, its two warpage degree difference, can cause the easy failure of described soldered ball.Topmost destruction is the interface that these soldered balls and this semiconductor element occur, and these soldered balls can be peeled off from this semiconductor element (Peeling); Less important destruction occurs in these soldered balls itself, i.e. these soldered balls can rupture (Fracture).Once above-mentioned destruction occurs, form and open circuit between this semiconductor element and this substrate, make the life-span of this known stacking type encapsulating structure only come to an end, cause the reliability of this known stacking type encapsulating structure to improve.In addition, along with the size of this semiconductor element is larger, above-mentioned destruction situation can be more obvious, and the reliability of encapsulating structure can be lower.
Summary of the invention
The one side of this exposure is about a kind of semiconductor element.In one embodiment, this semiconductor element comprises a body, at least one spatial accommodation, runs through the several conductive channels of this body (Conductive Via) and at least one filler.These conductive channels run through this body.This filler is to be positioned at this body, and wherein the thermal coefficient of expansion of this filler (CTE) is different from the thermal coefficient of expansion of this body and these conductive channels.
This exposure be about a kind of semiconductor package on the other hand.In one embodiment, this semiconductor package comprises a substrate, semiconductor element, several soldered ball and at least one chip.This semiconductor element is to be positioned at this substrate top, and comprises a body, several conductive channel and at least one filler.These conductive channels run through this body.This filler is to be positioned at this body, and wherein the thermal coefficient of expansion of this filler is different from the thermal coefficient of expansion of this body and these conductive channels.These soldered balls connect this substrate and this semiconductor element, and are electrically connected to these conductive channels.This chip is to be attached to this semiconductor element.
In this semiconductor package, this filler is added into the thermal coefficient of expansion that this semiconductor element can be adjusted this semiconductor element integral body, after making this semiconductor element be engaged to this substrate, can not mate (Mismatch) and produce serious warpage because of thermal coefficient of expansion each other.Moreover this body is divided into several independently blocks by this filler, therefore, when this semiconductor element is heated, these blocks are that warpage occurs individually, and can all not be accumulated in together, and by this, can reduce in a large number the warpage degree of this semiconductor element integral body.In addition, for example, along with the size larger (being greater than 10mm*10mm) of this semiconductor element, the effect of above-mentioned minimizing warpage can be more obvious, and can increase the reliability of this semiconductor package, can increase the number that stacks the chip on this semiconductor element simultaneously.
This exposure be the manufacture method about a kind of semiconductor element on the other hand.In one embodiment, this manufacture method comprises the following steps: (a) from a upper surface of a body, form several holes and at least one spatial accommodation; (b) form a conductive channel in each hole; (c) form at least one filler in this at least one spatial accommodation, wherein the thermal coefficient of expansion of this filler is different from the thermal coefficient of expansion of this body and these conductive channels; (d) form on one on rerouting layer and a protective layer in the upper surface of this body, wherein should be connected to these conductive channels by upper rerouting layer, should cover above rerouting layer by upper protective layer, should there is at least one upper shed to appear above rerouting layer of part by upper protective layer, and forming at least one upper protruding block, upper rerouting layer is somebody's turn to do in the upper shed and the contact that are positioned at protective layer on this; (e) from this body of a lower surface thinning of this body, to appear these conductive channels; And (f) form rerouting layer and a lower protective layer in the lower surface of this body; wherein this time rerouting layer is connected to these conductive channels; this lower protective layer covers the rerouting layer this time; this lower protective layer has at least one under shed to appear this time rerouting layer of part; and form projection at least once, be positioned at the under shed of this lower protective layer and contact the rerouting layer this time.
The accompanying drawing explanation
Fig. 1 shows the partial schematic sectional view of an embodiment of semiconductor element of the present invention.
Fig. 2 shows the schematic top plan view of the semiconductor element of Fig. 1, wherein only shows the relative position of this filler and these soldered balls.
Fig. 3 to Fig. 9 shows the schematic diagram of manufacture method one embodiment of semiconductor element of the present invention.
Figure 10 shows the cross-sectional schematic of another embodiment of semiconductor element of the present invention.
Figure 11 to Figure 14 shows the schematic diagram of another embodiment of the manufacture method of semiconductor element of the present invention.
Figure 15 shows the cross-sectional schematic of another embodiment of semiconductor element of the present invention.
Figure 16 shows the schematic top plan view of another embodiment of semiconductor element of the present invention, wherein only shows the relative position of this filler and these soldered balls.
Figure 17 shows the schematic top plan view of another embodiment of semiconductor element of the present invention, wherein only shows the relative position of this filler and these soldered balls.
Figure 18 shows the schematic top plan view of another embodiment of semiconductor element of the present invention, wherein only shows the relative position of this filler and these soldered balls.
Figure 19 shows the schematic top plan view of another embodiment of semiconductor element of the present invention, wherein only shows the relative position of this filler and these soldered balls.
Figure 20 shows the schematic top plan view of another embodiment of semiconductor element of the present invention, wherein only shows the relative position of this filler and these soldered balls.
Figure 21 shows the cross-sectional schematic of an embodiment of semiconductor package of the present invention.
Embodiment
With reference to figure 1, show the partial schematic sectional view of an embodiment of semiconductor element of the present invention.This semiconductor element 1 comprises rerouting layer 16 on a body 10, several conductive channel (Conductive Via) 12, at least one filler 14,, once protective layer 22, one first lower protective layer 24, one second lower protective layer 26, at least one upper protruding block 28, at least one lower protruding block 30 and several soldered ball 32 on protective layer 20, one second on rerouting layer 18, one first.
The material of this body 10 can be semi-conducting materials such as silicon, germanium, GaAs.This body 10 has a upper surface 101, a lower surface 102, several hole 103 and at least one spatial accommodation 104.In the present embodiment, these holes 103 are cylindric, and its diameter is 5 μ m to 200 μ m; This spatial accommodation 104 is a line style groove (Trench), and its width is 5 μ m to 200 μ m, and has at least one the first opening 1041 in the upper surface 101 of this body 10.This spatial accommodation 104 is between at least two holes 103, and this first opening 1041 is greater than the spacing in two holes 103 in the length of the line segment of these body 10 upper surfaces 101.In the present embodiment, these holes 103 and this spatial accommodation 104 all run through this body 10, yet, in other embodiments, only have these holes 103 to run through this body 10, and this spatial accommodation 104 can not run through this body 10.In addition,
These conductive channels 12 have a lining (Liner) 121 and a conducting metal 122.This lining 121 is insulating material, and it is the sidewall that is positioned at this hole 103, and defines a centre bore.The material of this conducting metal 122 is copper, and it is to fill up this centre bore, and is revealed in upper surface 101 and the lower surface 102 of this body 10, as the use of electric connection.
This filler 14 is polymer (Polymer) or metal, is filled in this spatial accommodation 104 of this body 10.That is this filler 14 is between at least two conductive channels 12.In the present embodiment, this filler 14 is polymer (Polymer), and its thermal coefficient of expansion (CTE) is greater than 10ppm/ ℃; The material of this body 10 is silicon, and its thermal coefficient of expansion (CTE) is about 3ppm/ ℃; The material of this conductive channel 12 is copper, and its thermal coefficient of expansion (CTE) is about 17ppm/ ℃.Therefore, the thermal coefficient of expansion of this filler 14 is different from the thermal coefficient of expansion of this body 10 and these conductive channels 12, and the thermal coefficient of expansion of this filler 14 is the thermal coefficient of expansions that are greater than this body 10.Be noted that this filler 14 can be as the use be electrically connected, it can not connect any circuit, even this filler 14 is metal materials, is also like this.
Should be adjacent to the upper surface 101 of this body 10 by upper rerouting layer 16, and be connected to these conductive channels 12.In the present embodiment, on this, rerouting layer 16 is to be positioned at this on first on protective layer 20 and opening 201, to contact these conductive channels 12.
This time rerouting layer 18 is adjacent to the lower surface 102 of this body 10, and is connected to these conductive channels 12.In the present embodiment, this time rerouting layer 18 is to be positioned on this first lower protective layer 24 and opening 241, to contact these conductive channels 12.
This on first protective layer 20 are the upper surfaces 101 that cover this body 10, and there are several openings 201 to appear these conductive channels 12.Be noted that this on first protective layer 20 be to cover this filler 14.This on first the material of protective layer 20 be benzocyclobutene (Benzocyclobutene, BCB) or polyimides (Polyimide, PI).
This on second protective layer 22 be positioned at this on first on protective layer 20, and cover should upper rerouting layer 16.This on second protective layer 22 there is at least one upper shed 221 should upper rerouting layer 16 to appear part.This on second the material of protective layer 22 be benzocyclobutene (Benzocyclobutene, BCB) or polyimides (Polyimide, PI), and this on protective layer 20 and this second, the material of protective layer 22 can be identical or different on first.This first lower protective layer 24 is the lower surfaces 102 that cover this body 10, and has several openings 241 to appear these conductive channels 12.Be noted that this first lower protective layer 24 is to cover this filler 14.The material of this first lower protective layer 24 is benzocyclobutene (Benzocyclobutene, BCB) or polyimides (Polyimide, PI).
This second lower protective layer 26 is positioned on this first lower protective layer 24, and covers rerouting layer 18 this time.This second lower protective layer 26 has at least one under shed 261 to appear this time rerouting layer 18 of part.The material of this second lower protective layer 26 is benzocyclobutene (Benzocyclobutene, BCB) or polyimides (Polyimide, PI), and the material of this first lower protective layer 24 and this second lower protective layer 26 can be identical or different.
This upper protruding block 28 is positioned at upper shed 221 and the contact of this protective layer 22 on second should upper rerouting layer 16.This lower protruding block 30 is positioned at the under shed 261 of this second lower protective layer 26 and contacts rerouting layer 18 this time.These soldered balls 32 are to be connected to this lower protruding block 30.Be understandable that, this semiconductor element 1 can not comprise these soldered balls 32.
With reference to figure 2, show the schematic top plan view of the semiconductor element of Fig. 1, wherein only show the relative position of this filler 14 and these soldered balls 32.
This spatial accommodation 104 is the spacings that are greater than two soldered balls 32 in the length of this first opening 1041 of these body 10 upper surfaces 101.As shown in the figure, this first opening 1041 forms several line segments on the upper surface 101 of this body 10, and these line segments are arranged in specific pattern, for example: rectangle, L shaped, cross or latticed.In the present embodiment, these line segments are arranged in latticed, and each soldered ball 32 is the relative positions that are positioned at each grid.In addition, the long-pending ratio of all surfaces of the area summation of all these the first openings 1041 and the upper surface 101 of this body 10 is 5% to 50%, is preferably 5% to 20%.Cooperation, with reference to figure 1 and Fig. 2, can find out that this body 10 is divided into several independence block of (not connecting mutually) by this filler 14.
In this semiconductor element 1, the interpolation of this filler 14 can be adjusted the thermal coefficient of expansion of this semiconductor element 1 integral body, make this semiconductor element 1 (for example: printed circuit board (PCB)), can not mate (Mismatch) and produce serious warpage because of thermal coefficient of expansion each other be engaged to other elements.Moreover this body 10 is divided into several independently blocks by this filler 14, therefore, when this semiconductor element 1 is heated, these blocks are that warpage occurs individually, and can all not be accumulated in together, by this, can reduce in a large number the warpage degree of this semiconductor element 1 integral body.In addition, for example, along with the size larger (being greater than 10mm*10mm) of this semiconductor element 1, the effect of above-mentioned minimizing warpage can be more obvious, and can increase the reliability of connected structure.
To Fig. 9, show the schematic diagram of manufacture method one embodiment of semiconductor element of the present invention with reference to figure 3.
With reference to figure 3, provide this body 10.The material of this body 10 can be semi-conducting materials such as silicon, germanium, GaAs, and it has a upper surface 101 and a lower surface 102.Then, form several holes 103 and at least one spatial accommodation 104 from the upper surface 101 of this body 10.In the present embodiment, these holes 103 are cylindric, and its diameter is 5 μ m to 200 μ m; This spatial accommodation 104 is a line style groove (Trench), and its width is 5 μ m to 200 μ m.In this step, these holes 103 and this spatial accommodation 104 all do not run through this body 10.In addition, this spatial accommodation 104 is between at least two holes 103.
This first opening 1041 forms several line segments (as shown in Figure 2) on the upper surface 101 of this body 10, and these line segments are arranged in specific pattern, for example: rectangle, L shaped, cross or latticed.In the present embodiment, these line segments are arranged in latticed.In addition, the long-pending ratio of all surfaces of the area summation of all these the first openings 1041 and the upper surface 101 of this body 10 is 5% to 50%, is preferably 5% to 20%.
With reference to figure 4, form this lining 121 in the sidewall in this hole 103, and define a centre bore 123.In the present embodiment, this lining 121 is insulating material, and it only is positioned at the sidewall in this hole 103, and is not positioned at the sidewall of this spatial accommodation 104.
With reference to figure 5, this conducting metal 122 is filled up to this centre bore 123, to form a conductive channel 12 in each hole 103.In the present embodiment, the material of this conducting metal 122 is copper.
With reference to figure 6, form this filler 14 to this spatial accommodation 104.This filler 14 is polymer (Polymer) or metal, and it fills up this spatial accommodation 104.In the present embodiment, this filler 14 is polymer (Polymer), and its thermal coefficient of expansion (CTE) is greater than 10ppm/ ℃; The material of this body 10 is silicon, and its thermal coefficient of expansion (CTE) is about 3ppm/ ℃; The material of this conductive channel 12 is copper, and its thermal coefficient of expansion (CTE) is about 17ppm/ ℃.Therefore, the thermal coefficient of expansion of this filler 14 is different from the thermal coefficient of expansion of this body 10 and these conductive channels 12, and the thermal coefficient of expansion of this filler 14 is the thermal coefficient of expansions that are greater than this body 10.Be noted that this filler 14 is not as the use of electric connection, it does not connect any circuit, even this filler 14 is metal materials, is like this yet.
With reference to figure 7, form this protective layer 20 on first, rerouting layer 16 on this, this on second protective layer 22 and this upper protruding block 28 in the upper surface 101 of this body 10.This on first protective layer 20 cover the upper surface 101 of these bodies 10, and there are several openings 201 to appear these conductive channels 12.Be noted that this on first protective layer 20 cover these fillers 14.Should be adjacent to the upper surface 101 of this body 10 by upper rerouting layer 16, and be connected to these conductive channels 12.In the present embodiment, on this, rerouting layer 16 is to be positioned at this on first on protective layer 20 and opening 201, to contact these conductive channels 12.This on second protective layer 22 be positioned at this on first on protective layer 20, and cover should upper rerouting layer 16.This on second protective layer 22 there is at least one upper shed 221 should upper rerouting layer 16 to appear part.This on first on protective layer 20 and this second material of protective layer 22 be benzocyclobutene (Benzocyclobutene; BCB) or polyimides (Polyimide; PI), and this on protective layer 20 and this second, the material of protective layer 22 can be identical or different on first.This upper protruding block 28 is positioned at upper shed 221 and the contact of this protective layer 22 on second should upper rerouting layer 16.
With reference to figure 8, from this body 10 of lower surface 102 thinnings of this body 10, to appear these conductive channels 12 and this filler 14.Now, these conductive channels 12 and this filler 14 all run through this body 10.
With reference to figure 9, form this first lower protective layer 24, this time rerouting layer 18, this second lower protective layer 26 and this lower protruding block 30 in the lower surface 102 of this body 10.This first lower protective layer 24 covers the lower surface 102 of this body 10, and has several openings 241 to appear these conductive channels 12.Be noted that this first lower protective layer 24 covers this filler 14.This time rerouting layer 18 is adjacent to the lower surface 102 of this body 10, and is connected to these conductive channels 12.In the present embodiment, this time rerouting layer 18 is to be positioned on this first lower protective layer 24 and opening 241, to contact these conductive channels 12.This second lower protective layer 26 is positioned on this first lower protective layer 24, and covers rerouting layer 18 this time.This second lower protective layer 26 has at least one under shed 261 to appear this time rerouting layer 18 of part.The material of this first lower protective layer 24 and this second lower protective layer 26 is benzocyclobutene (Benzocyclobutene; BCB) or polyimides (Polyimide; PI), and the material of this first lower protective layer 24 and this second lower protective layer 26 can be identical or different.This lower protruding block 30 is positioned at the under shed 261 of this second lower protective layer 26 and contacts rerouting layer 18 this time.Then, form these soldered balls 32 on this lower protruding block 30, to form this semiconductor element 1, as shown in Figure 1.
With reference to Figure 10, show the cross-sectional schematic of another embodiment of semiconductor element of the present invention.The semiconductor element 1a of the present embodiment and the semiconductor element 1 shown in Fig. 1 roughly the same, it does not exist together as described below.In the present embodiment, this semiconductor element 1a more comprises several electrical components (for example electric crystal 105), and it is positioned at the upper surface 101 of this body 10, and by this on first protective layer 20 cover.
With reference to figures 11 to Figure 14, the schematic diagram of another embodiment of the manufacture method of demonstration semiconductor element of the present invention.In the present embodiment, identical in the manufacture method of " first half section " technique and Fig. 3 to Fig. 6.The step of the manufacture method hookup 6 of the present embodiment.
With reference to Figure 11, after forming these conductive channels 12 and this filler 14, more the upper surface 101 in this body 10 forms these electrical components (for example electric crystal 105).
With reference to Figure 12, form this protective layer 20 on first, rerouting layer 16 on this, this on second protective layer 22 and this upper protruding block 28 in the upper surface 101 of this body 10.Be noted that this on first protective layer 20 cover these electrical components.
With reference to Figure 13, from this body 10 of lower surface 102 thinnings of this body 10, to appear these conductive channels 12 and this filler 14.Now, these conductive channels 12 and this filler 14 all run through this body 10.
With reference to Figure 14, form this first lower protective layer 24, this time rerouting layer 18, this second lower protective layer 26 and this lower protruding block 30 in the lower surface 102 of this body 10.Then, form these soldered balls 32 on this lower protruding block 30, to form this semiconductor element 1a, as shown in figure 10.
With reference to Figure 15, show the cross-sectional schematic of another embodiment of semiconductor element of the present invention.The semiconductor element 1b of the present embodiment and the semiconductor element 1 shown in Fig. 1 roughly the same, it does not exist together as described below.In the present embodiment, this semiconductor element 1b more comprises at least one insulating barrier 15, and it is between the sidewall of this filler 14 and this spatial accommodation 104.The material of the material of this insulating barrier 15 and this lining 121 is identical or different.In the present embodiment, the material of this insulating barrier 15 is identical with the material of this lining 121, and is that step at Fig. 4 forms simultaneously.In addition, owing to increasing this insulating barrier 15, therefore, this filler 14 can be metal, and it not only can adjust the thermal coefficient of expansion of this semiconductor element 1b integral body, and can be as heat dissipation path.Be noted that this filler 14 can be as the use of electric connection, it can not connect any circuit.
With reference to Figure 16, show the schematic top plan view of another embodiment of semiconductor element of the present invention, wherein only show the relative position of this filler 14 and these soldered balls 32.The semiconductor element 1c of the present embodiment and the semiconductor element 1 shown in Fig. 2 roughly the same, it does not exist together as described below.In the present embodiment, this first opening 1041 of this semiconductor element 1c is arranged in latticed at the upper surface 101 of this body 10, and single grid is larger than the grid of the semiconductor element 1 shown in Fig. 2, and the single grid in the middle of wherein being positioned at is contained four soldered balls 32.
With reference to Figure 17, show the schematic top plan view of another embodiment of semiconductor element of the present invention, wherein only show that this filler 14 and these weld the relative position of 32 balls.The semiconductor element 1d of the present embodiment and the semiconductor element 1 shown in Fig. 2 roughly the same, it does not exist together as described below.In the present embodiment, this first opening 1041 of this semiconductor element 1d is arranged in latticed at the upper surface 101 of this body 10, and single grid is larger than the grid of the semiconductor element 1 shown in Fig. 2, and the single grid in the middle of wherein being positioned at is contained eight soldered balls 32.
With reference to Figure 18, show the schematic top plan view of another embodiment of semiconductor element of the present invention, wherein only show the relative position of this filler 14 and these soldered balls 32.The semiconductor element 1e of the present embodiment and the semiconductor element 1 shown in Fig. 2 roughly the same, it does not exist together as described below.In the present embodiment, this first opening 1041 of this semiconductor element 1e is arranged in a rectangle and a cross at the upper surface 101 of this body 10, and wherein this cross can be considered two L shaped combinations.
With reference to Figure 19, show the schematic top plan view of another embodiment of semiconductor element of the present invention, wherein only show the relative position of this filler 14 and these soldered balls 32.The semiconductor element 1f of the present embodiment and the semiconductor element 1 shown in Fig. 2 roughly the same, it does not exist together as described below.In the present embodiment, this first opening 1041 of this semiconductor element 1f the upper surface 101 of this body 10 be arranged in a cross or two L shaped.
With reference to Figure 20, show the schematic top plan view of another embodiment of semiconductor element of the present invention, wherein only show the relative position of this filler 14 and these soldered balls 32.The semiconductor element 1g of the present embodiment and the semiconductor element 1 shown in Fig. 2 roughly the same, it does not exist together as described below.In the present embodiment, this first opening 1041 of this semiconductor element 1g is arranged in a rectangle at the upper surface 101 of this body 10.
With reference to Figure 21, show the cross-sectional schematic of an embodiment of semiconductor package of the present invention.This semiconductor package 4 comprises a substrate 41, semiconductor element 1, several soldered ball 32, at least one chip (for example chip 42), a primer 46 and an adhesive material 47.In the present embodiment, this substrate 41 is a printed circuit board (PCB) (PCB) substrate.This semiconductor element 1 is to be positioned at this substrate 41 tops.This semiconductor element 1 is identical with the semiconductor element 1 shown in Fig. 1 and Fig. 2, yet this semiconductor element 1 also can replace to the semiconductor element 1f of semiconductor element 1e, Figure 19 of semiconductor element 1d, Figure 18 of semiconductor element 1c, Figure 17 of semiconductor element 1b, Figure 16 of semiconductor element 1a, Figure 15 of Figure 10 or the semiconductor element 1g of Figure 20.These soldered balls 32 connect this lower protruding block 30 of this substrate 41 and this semiconductor element 1, and are electrically connected to these conductive channels 12.
This at least one chip (for example chip 42) is disposed at this semiconductor element 1, and is electrically connected to this semiconductor element 1.In the present embodiment, this at least one chip for example comprises one first chip 42(: bluetooth (BT) chip), the second chip 43(for example: radio frequency (RF) chip), the 3rd chip 44(for example: power management (PMIC) chip) and four-core sheet 45(is for example: detector (Detector)).This first chip 42 has several the first projections 421, is connected to these upper protruding blocks 28.This second chip 43 has several the second projections 431, is connected to these upper protruding blocks 28.The 3rd chip 44 has several the 3rd projections 441, is connected to these upper protruding blocks 28.This four-core sheet 45 has several the 4th projections 451, is connected to these upper protruding blocks 28.
This primer 46 is to be positioned between these chips 42,43,44,45 and this semiconductor element 1, to protect these first projections 421, these second projections 431, these grade in an imperial examination three projections 441, this grade in an imperial examination four projections 451 and these upper protruding blocks 28.This adhesive material 47 is to be positioned on this substrate 41, to cover a upper surface of these chips 42,43,44,45.In other embodiments, this adhesive material 47 be can not need, only with this primer 46, these projections 421,431,441,451 and these upper protruding blocks 28 coated.Perhaps, can not need this primer 46, only with these adhesive material 47 protection these chips 42,43,44,45, these projections 421,431,441,451 and these upper protruding blocks 28.In addition, this primer 46 is identical or different with the material of this adhesive material 47.
In this semiconductor package 4, this filler 14 is added into the thermal coefficient of expansion that this semiconductor element 1 can be adjusted this semiconductor element 1 integral body, after making this semiconductor element 1 be engaged to this substrate 41, can not mate (Mismatch) and produce serious warpage because of thermal coefficient of expansion each other.Moreover this body 10 is divided into several independently blocks by this filler 14, therefore, when this semiconductor element 1 is heated, warpage occurs individually in these blocks, and can all not be accumulated in together, and by this, can reduce in a large number the warpage degree of this semiconductor element 1 integral body.In addition, for example, along with the size larger (being greater than 10mm*10mm) of this semiconductor element 1, the effect of above-mentioned minimizing warpage can be more obvious, and can increase the reliability of this semiconductor package 4, can increase and stack chip (these chips 42,43 for example simultaneously, 44,45) number.
Reference table 1, show that different types semiconductor element of the present invention utilizes soldered ball 32 to be engaged in the connected structure of a substrate, the analog result comparison sheet of the suffered normal stress of protective layer (Normal Stress), wherein comparative example is known technology, it does not add this filler 14; The semiconductor element 1 that example 1 is Fig. 2, the long-pending ratio of all surfaces of the area summation of its all these the first openings 1041 and the upper surface 101 of this body 10 is 40%; The semiconductor element 1c that example 2 is Figure 16, the long-pending ratio of all surfaces of the area summation of its all these the first openings 1041 and the upper surface 101 of this body 10 is 20%; The semiconductor element 1d that example 3 is Figure 17, the long-pending ratio of all surfaces of the area summation of its all these the first openings 1041 and the upper surface 101 of this body 10 is 10%; The semiconductor element 1e that example 4 is Figure 18, the long-pending ratio of all surfaces of the area summation of its all these the first openings 1041 and the upper surface 101 of this body 10 is 5%; The semiconductor element 1f that example 5 is Figure 19, the long-pending ratio of all surfaces of the area summation of its all these the first openings 1041 and the upper surface 101 of this body 10 is 2.5%; The semiconductor element 1g that example 6 is Figure 20, the long-pending ratio of all surfaces of the area summation of its all these the first openings 1041 and the upper surface 101 of this body 10 is 2.5%.The material of this semiconductor element is silicon, and this filler 14 is polymer (Polymer), and this protective layer refers to this first lower protective layer 24.
Table 1: the analog result of the suffered normal stress of protective layer of different types semiconductor element
Figure BDA0000377789340000101
Figure BDA0000377789340000111
As shown in Table 1, example 1 to the coefficient of safety of example 3 all has obvious lifting, example 4 is similar with comparative example to 6 of examples, from table 1 analog result, the long-pending ratio of all surfaces of the area summation of the first opening 1041 and the upper surface 101 of this body 10 is greater than 5% when above, can there is preferably coefficient of safety, for example be greater than 1.00.
Reference table 2, show that different types semiconductor element of the present invention utilizes soldered ball 32 to be engaged in the connected structure of a substrate, soldered ball destroys the analog result comparison sheet in life-span (Solder Fatigue Life), and wherein comparative example and example 1 are identical with above-mentioned table 1 to the parameter of example 6.
Table 2: the soldered ball of different types semiconductor element destroys the analog result in life-span
Figure BDA0000377789340000112
Figure BDA0000377789340000121
As shown in Table 2, example 1 to the usefulness of example 3 all has obvious lifting, and example 4 to the usefulness of example 6 only a little more than comparative example, from table 2 analog result, the long-pending ratio of all surfaces of the area summation of the first opening 1041 and the upper surface 101 of this body 10 is greater than 5% when above, can have more significant usefulness, for example is greater than 1000%.
Only above-described embodiment is only explanation principle of the present invention and effect thereof, but not in order to limit the present invention.Therefore, practise in the personage of this technology and above-described embodiment is modified and change still not de-spirit of the present invention.Interest field of the present invention should be as listed as claims.

Claims (20)

1. a semiconductor element comprises:
One body;
Several conductive channels, run through this body;
At least one spatial accommodation, run through this body; And
At least one filler, be positioned at this spatial accommodation, and wherein the thermal coefficient of expansion of this filler is different from the thermal coefficient of expansion of this body and described conductive channel.
2. semiconductor element as claimed in claim 1, is characterized in that, this body has several holes, run through this body, each described conductive channel has a lining and a conducting metal, and this lining is the sidewall that is positioned at this hole, and define a centre bore, this conducting metal is to fill up this centre bore.
3. semiconductor element as claimed in claim 1, is characterized in that, this filler is between at least two conductive channels.
4. semiconductor element as claimed in claim 1, is characterized in that, this at least one spatial accommodation has at least one the first opening in a surface of this body.
5. semiconductor element as claimed in claim 1, is characterized in that, this body is semi-conducting material, and this filler is polymer or metal.
6. semiconductor element as claimed in claim 4, is characterized in that, the length of this first opening is greater than the spacing of two conductive channels.
7. semiconductor element as claimed in claim 4, is characterized in that, the long-pending ratio of the area summation of all these at least one the first openings and this surperficial all surfaces of this body is 5% to 50%.
8. semiconductor element as claimed in claim 1, is characterized in that, more comprises at least one insulating barrier, between the sidewall of this filler and this spatial accommodation.
9. semiconductor element as claimed in claim 4, is characterized in that, this at least one first opening forms at least one line segment on this surface of this body, and this at least one line segment is arranged in rectangle, L shaped, cross or netted.
10. semiconductor element as claimed in claim 1, is characterized in that, this body more comprises several electrical components.
11. a semiconductor package comprises:
One substrate;
Semiconductor element, be positioned at this substrate top, and this semiconductor element comprises:
One body;
Several conductive channels, run through this body;
At least one spatial accommodation, run through this body; And
At least one filler, be positioned at this spatial accommodation, and wherein the thermal coefficient of expansion of this filler is different from the thermal coefficient of expansion of this body and described conductive channel;
Several soldered balls, connect this substrate and this semiconductor element, and be electrically connected to described conductive channel; And
At least one chip has at least one projection, is disposed at this semiconductor element top.
12. the semiconductor package as claim 11, is characterized in that, this at least one spatial accommodation has at least one the first opening in a surface of this body.
13. the semiconductor package as claim 12, is characterized in that, the long-pending ratio of the area summation of all these at least one the first openings and this surperficial all surfaces of this body is 5% to 50%.
14. the semiconductor package as claim 11, is characterized in that, more comprises that a primer coats this at least one projection.
15. the semiconductor package as claim 11, is characterized in that, more comprises that an adhesive material covers a upper surface of this at least one chip.
16. the semiconductor package as claim 11, is characterized in that, this body more comprises several electrical components.
17. the manufacture method of a semiconductor element comprises the following steps:
(a) form several holes and at least one spatial accommodation from a upper surface of a body;
(b) form a conductive channel in each hole;
(c) form at least one filler in this at least one spatial accommodation, wherein the thermal coefficient of expansion of this filler is different from the thermal coefficient of expansion of this body and this conductive channel;
(d) form on one on rerouting layer and a protective layer in the upper surface of this body, wherein should be connected to described conductive channel by upper rerouting layer, should cover above rerouting layer by upper protective layer, should upper protective layer have at least one upper shed should upper rerouting layer to appear part, and forms in the upper shed of at least one upper protruding block protective layer in this on and the upper rerouting layer of contact;
(e) from this body of a lower surface thinning of this body, to appear described conductive channel; And
(f) form rerouting layer and a lower protective layer in the lower surface of this body; wherein this time rerouting layer is connected to described conductive channel; this lower protective layer covers the rerouting layer this time; this lower protective layer has at least one under shed to appear this time rerouting layer of part, and formation at least once projection in the under shed of this lower protective layer and contact the rerouting layer this time.
18. the manufacture method as claim 17, it is characterized in that, in step (a), this at least one spatial accommodation is the line style groove, and the upper surface in this body has at least one the first opening, the long-pending ratio of all surfaces of the area summation of all these at least one the first openings and the upper surface of this body is 5% to 50%.
19. the manufacture method as claim 17, is characterized in that, this step (c) more comprises that the several electrical components of a formation are in the step of this body afterwards.
20. the manufacture method as claim 17, is characterized in that, more comprises that step (g) forms a soldered ball and is connected to this lower protruding block.
CN201310400335.8A 2013-05-09 2013-09-05 Semiconductor package structure and manufacturing method thereof Active CN103456707B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW102116464A TWI503934B (en) 2013-05-09 2013-05-09 Semiconductor element and manufacturing method thereof and semiconductor package
TW102116464 2013-05-09

Publications (2)

Publication Number Publication Date
CN103456707A true CN103456707A (en) 2013-12-18
CN103456707B CN103456707B (en) 2016-09-21

Family

ID=49738921

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310400335.8A Active CN103456707B (en) 2013-05-09 2013-09-05 Semiconductor package structure and manufacturing method thereof

Country Status (3)

Country Link
US (2) US9589840B2 (en)
CN (1) CN103456707B (en)
TW (1) TWI503934B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107039235A (en) * 2016-02-03 2017-08-11 奕力科技股份有限公司 Have the driving chip and its manufacture method of low warpage

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI503934B (en) * 2013-05-09 2015-10-11 Advanced Semiconductor Eng Semiconductor element and manufacturing method thereof and semiconductor package
JP2016174101A (en) 2015-03-17 2016-09-29 株式会社東芝 Semiconductor device and manufacturing method of the same
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10510668B1 (en) * 2018-07-16 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating semiconductor device
KR102545168B1 (en) 2019-03-26 2023-06-19 삼성전자주식회사 Interposer and semiconductor package including the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4069498A (en) * 1976-11-03 1978-01-17 International Business Machines Corporation Studded heat exchanger for integrated circuit package
US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
US20020028532A1 (en) * 1997-04-25 2002-03-07 Yoshitaka Tsunashima Method of manufacturing a multi-chip semiconductor device effective to improve alignment
CN1591920A (en) * 2003-09-01 2005-03-09 株式会社东芝 Light semiconductor device and optical signal input and output device
CN102497723A (en) * 2006-05-02 2012-06-13 揖斐电株式会社 Circuit wiring board incorporating heat resistant substrate
CN102610709A (en) * 2011-01-19 2012-07-25 旭德科技股份有限公司 Package carrier and method for manufacturing the same

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2737073C3 (en) 1977-08-17 1981-09-17 Siemens AG, 1000 Berlin und 8000 München Method for producing an insulated gate field effect transistor for a single transistor memory cell
CN1187800C (en) * 1997-04-03 2005-02-02 株式会社山武 Circuit board and detector, and method for manufacturing the same
US6239026B1 (en) 1998-09-28 2001-05-29 Conexant Systems, Inc. Nitride etch stop for poisoned unlanded vias
JP2004128063A (en) 2002-09-30 2004-04-22 Toshiba Corp Semiconductor device and its manufacturing method
JP2004128352A (en) 2002-10-04 2004-04-22 Mitsubishi Electric Corp Semiconductor device and manufacturing method of semiconductor device
TWI228806B (en) * 2003-05-16 2005-03-01 Advanced Semiconductor Eng Flip chip package
CN100485913C (en) * 2004-02-24 2009-05-06 揖斐电株式会社 Substrate for mounting semiconductor
JP4343044B2 (en) * 2004-06-30 2009-10-14 新光電気工業株式会社 Interposer, manufacturing method thereof, and semiconductor device
US20060231960A1 (en) * 2005-04-15 2006-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. Non-cavity semiconductor packages
US7425507B2 (en) 2005-06-28 2008-09-16 Micron Technology, Inc. Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures
JP4609317B2 (en) 2005-12-28 2011-01-12 カシオ計算機株式会社 Circuit board
US7544605B2 (en) 2006-11-21 2009-06-09 Freescale Semiconductor, Inc. Method of making a contact on a backside of a die
US8049310B2 (en) 2008-04-01 2011-11-01 Qimonda Ag Semiconductor device with an interconnect element and method for manufacture
JP5343245B2 (en) * 2008-05-15 2013-11-13 新光電気工業株式会社 Manufacturing method of silicon interposer
US7998860B2 (en) * 2009-03-12 2011-08-16 Micron Technology, Inc. Method for fabricating semiconductor components using maskless back side alignment to conductive vias
TWI380421B (en) 2009-03-13 2012-12-21 Advanced Semiconductor Eng Method for making silicon wafer having through via
TWI419257B (en) * 2009-12-29 2013-12-11 Advanced Semiconductor Eng Semiconductor process, semiconductor element and package having semiconductor element
TWI414044B (en) 2009-12-29 2013-11-01 Advanced Semiconductor Eng Semiconductor process, semiconductor element and package having semiconductor element
US8294261B2 (en) * 2010-01-29 2012-10-23 Texas Instruments Incorporated Protruding TSV tips for enhanced heat dissipation for IC devices
JP2011171567A (en) * 2010-02-19 2011-09-01 Elpida Memory Inc Method of manufacturing substrate structure, and method of manufacturing semiconductor device
US9048233B2 (en) * 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
KR101817159B1 (en) * 2011-02-17 2018-02-22 삼성전자 주식회사 Semiconductor package having TSV interposer and method of manufacturing the same
US8963335B2 (en) * 2012-09-13 2015-02-24 Invensas Corporation Tunable composite interposer
TWI503934B (en) * 2013-05-09 2015-10-11 Advanced Semiconductor Eng Semiconductor element and manufacturing method thereof and semiconductor package

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4069498A (en) * 1976-11-03 1978-01-17 International Business Machines Corporation Studded heat exchanger for integrated circuit package
US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
US20020028532A1 (en) * 1997-04-25 2002-03-07 Yoshitaka Tsunashima Method of manufacturing a multi-chip semiconductor device effective to improve alignment
CN1591920A (en) * 2003-09-01 2005-03-09 株式会社东芝 Light semiconductor device and optical signal input and output device
CN102497723A (en) * 2006-05-02 2012-06-13 揖斐电株式会社 Circuit wiring board incorporating heat resistant substrate
CN102610709A (en) * 2011-01-19 2012-07-25 旭德科技股份有限公司 Package carrier and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107039235A (en) * 2016-02-03 2017-08-11 奕力科技股份有限公司 Have the driving chip and its manufacture method of low warpage

Also Published As

Publication number Publication date
TWI503934B (en) 2015-10-11
CN103456707B (en) 2016-09-21
US20140332957A1 (en) 2014-11-13
US10056325B2 (en) 2018-08-21
TW201444033A (en) 2014-11-16
US20170133311A1 (en) 2017-05-11
US9589840B2 (en) 2017-03-07

Similar Documents

Publication Publication Date Title
EP2978020B1 (en) Package substrate
US10008470B2 (en) Embedded chip packages and methods for manufacturing an embedded chip package
CN103456707A (en) Semiconductor package structure and manufacturing method thereof
US9224681B2 (en) CTE matched interposer and method of making
US8778791B2 (en) Semiconductor structure and method for making the same
US9553076B2 (en) Stackable molded microelectronic packages with area array unit connectors
KR102107037B1 (en) Printed circuit board and method of manufacturing the same
JP5143451B2 (en) Semiconductor device and manufacturing method thereof
EP2936558B1 (en) Method for fabricating base for semiconductor package
KR101060862B1 (en) Interposer and manufacturing method thereof
WO2009017271A2 (en) Metal-based package substrate, three-dimensional multi-layered package module using the same, and manufacturing method thereof
KR101037827B1 (en) Semiconductor package
US20050258536A1 (en) Chip heat sink device and method
US20040256715A1 (en) Wiring board, semiconductor device and process of fabricating wiring board
JP5814272B2 (en) Thermal vias in integrated circuit packages with integrated dies
US6657295B2 (en) Multilayer interconnect board and multilayer semiconductor device
US11329019B2 (en) Semiconductor device
TWI808601B (en) Semiconductor package device and semiconductor package unit
JP2005236072A (en) Laminated semiconductor device
JP2006203110A (en) Semiconductor device and its manufacturing method
JP2010212647A (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant