CN103426865A - Structure and method for testing contact resistance of W-sinks in semiconductor product - Google Patents

Structure and method for testing contact resistance of W-sinks in semiconductor product Download PDF

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Publication number
CN103426865A
CN103426865A CN2012101546589A CN201210154658A CN103426865A CN 103426865 A CN103426865 A CN 103426865A CN 2012101546589 A CN2012101546589 A CN 2012101546589A CN 201210154658 A CN201210154658 A CN 201210154658A CN 103426865 A CN103426865 A CN 103426865A
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tungsten
contact resistance
tungsten groove
groove
metal level
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CN103426865B (en
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黄景丰
刘梅
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Abstract

The invention discloses a structure for testing the contact resistance of W-sinks in a semiconductor product. Three active regions which are adjacent to one another in sequence are formed on a silicon substrate, and the three active regions and the silicon substrate are in an N type or in a P type at the same time; a first W-sink array formed by X W-sinks formed on the first active region is connected with a first metal layer, a second W-sink array formed by Y W-sinks formed on the second active region is connected with a second metal layer, and a third W-sink array formed by Z W-sinks formed on the third active region is connected with a third metal layer; the sizes of the W-sinks in the three W-sink arrays are equal; the distance between the first W-sink array and the second W-sink array is equal to that between the second W-sink array and the third W-sink array; X, Y and Z are positive integers, and X is not equal to Z. The invention further discloses a method for testing the contact resistance of the W-sinks in the semiconductor product by using the structure for testing the contact resistance of the W-sinks in the semiconductor product. The structure and method for testing the contact resistance of the W-sinks in the semiconductor product can accurately measure the contact resistance of the W-sinks.

Description

Semiconductor article tungsten groove contact resistance test structure and method of testing
Technical field
The present invention relates to semiconductor technology, particularly a kind of semiconductor article tungsten groove contact resistance test structure and method of testing.
Background technology
Semiconductor article as shown in Figure 1, usually be formed with a plurality of active areas on silicon substrate 101, between each active area, with field oxygen 103, isolate, during some semiconductor article encapsulation, draw substrate at chip back, draw resistance in order to reduce, usually grooving on silicon substrate 101, recharge tungsten and form tungsten groove (W-Sink) 102, on tungsten groove 102, there is metal level 105 to cover to prevent that tungsten is exposed, between metal level 105 and substrate, by dielectric layer 104 isolation, this dielectric layer 104 can be oxide, nitride, nitrogen oxide etc.If utilize traditional chain to be connected in series the contact resistance that (Chain) measures tungsten groove 102, because tungsten groove 102 directly is connected with substrate 101, any two groups of tungsten grooves 102 on silicon chip can be connected by substrate 101, serial number can only have 2 groups, total resistance value is less, so test error is large; If utilize traditional Kelvin to connect the contact resistance that (Kelvin) measures tungsten groove 102, because of can't be by the quantification of the resistance substrate of the middle introducing of test structure, and can't quantize the contact resistance of tungsten groove.Kelvin connects principle that (or claiming four end test modes) carry out resistance test as shown in Figure 2.Kelvin is connected with two requirements: for each test point, an excitation line F and a detection line S are arranged, the two strictly separates, and forms separately independent loop; Require the S line must receive on a test loop that high input impedance arranged, the electric current that makes to flow through detection line S is minimum, is approximately zero simultaneously.In Fig. 2, r means the contact resistance sum of lead resistance and probe and test point.Because the electric current that flows through test loop is zero, at r3, pressure drop on r4 is also zero, and exciting current I is at r1, pressure drop on r2 does not affect the pressure drop of I on measured resistance, so voltmeter V can accurately measure the magnitude of voltage at measured resistance Rt two ends, thereby accurately measure the resistance of measured resistance R t.Test result and r are irrelevant, have effectively reduced measure error.According to effect and the height of current potential, these four lines are called as respectively that high potential applies line (HF), electronegative potential applies line (LF), high potential detection line (HS) and electronegative potential detection line (LS).
Summary of the invention
The technical problem to be solved in the present invention is accurately to record the contact resistance of tungsten groove.
For solving the problems of the technologies described above, the invention provides a kind of semiconductor article tungsten groove contact resistance test structure, its structure is:
Be formed with three adjacent active areas successively on silicon substrate, three active areas and substrate are all N-type or P type;
Be formed with X tungsten groove on first active area, this X tungsten groove forms the first tungsten groove array with connecing the first metal layer; Be formed with Y tungsten groove on second active area, this Y tungsten groove forms the second tungsten groove array with connecing the second metal level; Be formed with Z tungsten groove on the 3rd active area, this Z tungsten groove forms the 3rd tungsten groove array with connecing the 3rd metal level;
Electric insulation between the first metal layer, the second metal level, the 3rd metal level;
Each tungsten groove in three tungsten groove arrays measure-alike;
Spacing between the first tungsten groove array and the second tungsten groove array, equal the spacing between the second tungsten groove array and the 3rd tungsten groove array;
X, Y, Z is positive integer, X is not equal to Z.
Preferably, three active areas are measure-alike, between three active areas, with field oxygen, isolate.
Preferably, X, Y, Z are unequal mutually.
Preferably, between the first metal layer, the second metal level, the 3rd metal level and silicon substrate, by dielectric layer, isolated.
Preferably, this semiconductor article tungsten groove contact resistance test structure is positioned at scribe line area or the test chip district of silicon chip.
For solving the problems of the technologies described above, the present invention also provides a kind of described semiconductor article tungsten groove contact resistance test structure to carry out the method for tungsten groove contact resistance test, and it comprises the following steps:
One. utilize the first metal layer of the described semiconductor article tungsten of Kelvin's connecting test groove contact resistance test structure, the resistance R between the second metal level aUtilize the second metal level of the described semiconductor article tungsten of Kelvin's connecting test groove contact resistance test structure, the resistance R between the 3rd metal level b, two. and calculate the contact resistance R of single tungsten groove Wsink, R W sin k = ( R a - R b ) * X * Z Z - X .
Semiconductor article tungsten groove contact resistance test structure of the present invention, comprise three tungsten groove arrays, each tungsten groove in three tungsten groove arrays measure-alike, these three tungsten groove arrays lay respectively on three active areas, and three active areas and substrate are all N-type or the doping of P type.The first tungsten groove array is that X tungsten groove composes in parallel, the second tungsten groove array is that Y tungsten groove composes in parallel, the 3rd tungsten groove array is that Z tungsten groove composes in parallel, X, Y, Z is positive integer, and X is not equal to Z, three tungsten groove arrays are drawn by metal level respectively, between metal level and substrate, by dielectric layer, are isolated, spacing between the first tungsten groove array and the second tungsten groove array equals the spacing between the second tungsten groove array and the 3rd tungsten groove array, between these three tungsten groove arrays, with field oxygen, isolates.Utilize this semiconductor article tungsten groove contact resistance test structure, can connect by Kelvin (Kelvin) and test respectively the resistance R obtained between the first tungsten groove array and the second tungsten groove array a, the resistance R between the second tungsten groove array and the 3rd tungsten groove array b, then according to R a, R B, X, Z can calculate the contact resistance of single tungsten groove, changes the size of single tungsten groove, can obtain the contact resistance of the tungsten groove of different size.The contact resistance of the tungsten groove that utilizes the method to obtain, the dead resistance of substrate and line can be fallen in conductively-closed, can try to achieve tungsten groove contact resistance value accurately by measured data, thereby quantizes tungsten groove contact resistance value, for on-line monitoring tungsten groove technique provides feasibility.
The accompanying drawing explanation
In order to be illustrated more clearly in technical scheme of the present invention, below the accompanying drawing that will use required for the present invention is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is semiconductor article tungsten groove structural section figure signal;
Fig. 2 is that Kelvin connects the schematic diagram that carries out resistance test;
Fig. 3 is semiconductor article tungsten groove contact resistance test structure of the present invention one embodiment schematic diagram;
Fig. 4 is the first metal layer that utilizes Kelvin's connecting test semiconductor article tungsten of the present invention groove contact resistance test structure, the equivalent electric circuit of the resistance between the second metal level;
Fig. 5 utilizes the second metal level of Kelvin's connecting test semiconductor article tungsten of the present invention groove contact resistance test structure, the equivalent electric circuit of the resistance between the 3rd metal level.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Should be appreciated that preferred embodiment described herein, only for description and interpretation the present invention, is not intended to limit the present invention.And, in the situation that do not conflict, embodiment and the feature in embodiment in the present invention can combine mutually.Embodiment based in the present invention, the every other embodiment that those of ordinary skills obtain, belong to the scope of protection of the invention.
Embodiment mono-
Semiconductor article tungsten groove contact resistance test structure as shown in Figure 3,
Be formed with three adjacent active areas successively on silicon substrate 101, three active areas and substrate 101 are all N-type or P type, and three active areas are measure-alike, between three active areas with 103 isolation of field oxygen; Be formed with X tungsten groove (W-Sink) 102 on first active area 111, this X tungsten groove (W-Sink) forms the first tungsten groove array with connecing the first metal layer 105; Be formed with Y tungsten groove (W-Sink) 102 on second active area 112, this Y tungsten groove (W-Sink) forms the second tungsten groove array with connecing the second metal level 106; Be formed with Z tungsten groove (W-Sink) 102 on the 3rd active area 113, this Z tungsten groove (W-Sink) forms the 3rd tungsten groove array with connecing the 3rd metal level 107; Electric insulation between the first metal layer 105, the second metal level 106 the 3rd metal level 107,101 of each metal level 105,106,107 and silicon substrates are isolated by dielectric layer 104, this dielectric layer 104 can be oxide, nitride, nitrogen oxide etc., each tungsten groove in three tungsten groove arrays measure-alike, the spacing between the first tungsten groove array and the second tungsten groove array equals the spacing between the second tungsten groove array and the 3rd tungsten groove array, and spacing is A, X, Y, Z is positive integer, X is not equal to Z.
Preferably, X, Y, Z are mutual unequal positive integer.
Preferably, this semiconductor article tungsten groove contact resistance test structure is positioned at scribe line area or the test chip district of silicon chip.
Embodiment bis-
Utilize the semiconductor article tungsten groove contact resistance test structure of embodiment mono-to carry out the method that tungsten groove contact resistance is tested, comprise the following steps:
One. utilize Kelvin's connect (Kelvin) the first metal layer 105 of testing described semiconductor article tungsten groove contact resistance test structure, resistance R between the second metal level 106 aUtilize Kelvin's connect (Kelvin) the second metal level 106 of testing described semiconductor article tungsten groove contact resistance test structure, resistance R between the 3rd metal level 107 b,
Two. calculate the contact resistance R of single tungsten groove Wsink,
R W sin k = ( R a - R b ) * X * Z Z - X , Formula 1;
Utilize Kelvin's connect (Kelvin) the first metal layer 105 of testing described semiconductor article tungsten groove contact resistance test structure, resistance R between the second metal level 106 aEquivalent electric circuit as shown in Figure 4:
R a=R 1+ R 2+ R Substrate parasitism 1, formula 2;
Utilize Kelvin's connect (Kelvin) the second metal level 106 of testing described semiconductor article tungsten groove contact resistance test structure, resistance R between the 3rd metal level 107 bEquivalent electric circuit as shown in Figure 5:
R b=R 2+ R 3+ R Substrate parasitism 2, formula 3;
Total contact resistance after X the tungsten groove parallel connection that R1 is the first tungsten groove array,
R 1 = R W sin k * 1 X , Formula 4;
Total contact resistance after Y the tungsten groove parallel connection that R2 is the second tungsten groove array,
R 2 = R W sin k * 1 Y , Formula 5;
Total contact resistance after Z the tungsten groove parallel connection that R3 is the 3rd tungsten groove array,
R 3 = R W sin k * 1 z , Formula 6;
R WsinkFor the contact resistance of single tungsten groove, measure-alike due to each tungsten groove in three tungsten groove arrays, so can think that the contact resistance of each tungsten groove is identical, be all R Wsink
R Substrate parasitism 1Be the substrate dead resistance between the first tungsten groove array and the second tungsten groove array, R Substrate parasitism 2Be the substrate dead resistance between the second tungsten groove array and the 3rd tungsten groove array, because the spacing between the first tungsten groove array and the second tungsten groove array equals the spacing between the second tungsten groove array and the 3rd tungsten groove array, therefore can think R Substrate parasitism 1Equal R Substrate parasitism 2
Bring formula 4～6 into formula 2,3,:
R a - R b = ( 1 X - 1 Z ) * R W sin k ,
R W sin k = ( R a - R b ) * X * Z Z - X , Formula 1;
Due to R aAnd R bBy test, can be obtained, X and Z are that layout design is known, therefore can try to achieve tungsten groove contact resistance R by formula 1 Wsink.
Semiconductor article tungsten groove contact resistance test structure of the present invention, comprise three tungsten groove arrays, each tungsten groove in three tungsten groove arrays measure-alike, these three tungsten groove arrays lay respectively on three active areas, and three active areas and substrate are all N-type or the doping of P type.The first tungsten groove array is that X tungsten groove composes in parallel, the second tungsten groove array is that Y tungsten groove composes in parallel, the 3rd tungsten groove array is that Z tungsten groove composes in parallel, X, Y, Z is positive integer, and X is not equal to Z, three tungsten groove arrays are drawn by metal level respectively, between metal level and substrate, by dielectric layer, are isolated, spacing between the first tungsten groove array and the second tungsten groove array equals the spacing between the second tungsten groove array and the 3rd tungsten groove array, between these three tungsten groove arrays, with field oxygen, isolates.Utilize this semiconductor article tungsten groove contact resistance test structure, can connect by Kelvin (Kelvin) and test respectively the resistance R obtained between the first tungsten groove array and the second tungsten groove array a, the resistance R between the second tungsten groove array and the 3rd tungsten groove array B, then according to R a, R B, X, Z can calculate the contact resistance of single tungsten groove, changes the size of single tungsten groove, can obtain the contact resistance of the tungsten groove of different size.The contact resistance of the tungsten groove that utilizes the method to obtain, the dead resistance of substrate and line can be fallen in conductively-closed, can try to achieve tungsten groove contact resistance value accurately by measured data, thereby quantizes tungsten groove contact resistance value, for on-line monitoring tungsten groove technique provides feasibility.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.

Claims (7)

1. a semiconductor article tungsten groove contact resistance test structure, is characterized in that,
Be formed with three adjacent active areas successively on silicon substrate, three active areas and substrate are all N-type or P type;
Be formed with X tungsten groove on first active area, this X tungsten groove forms the first tungsten groove array with connecing the first metal layer; Be formed with Y tungsten groove on second active area, this Y tungsten groove forms the second tungsten groove array with connecing the second metal level; Be formed with Z tungsten groove on the 3rd active area, this Z tungsten groove forms the 3rd tungsten groove array with connecing the 3rd metal level;
Electric insulation between the first metal layer, the second metal level, the 3rd metal level;
Each tungsten groove in three tungsten groove arrays measure-alike;
Spacing between the first tungsten groove array and the second tungsten groove array, equal the spacing between the second tungsten groove array and the 3rd tungsten groove array;
X, Y, Z is positive integer, X is not equal to Z.
2. semiconductor article tungsten groove contact resistance test structure according to claim 1, is characterized in that,
Three active areas are measure-alike, between three active areas, with field oxygen, isolate.
3. semiconductor article tungsten groove contact resistance test structure according to claim 2, is characterized in that,
X, Y, Z are unequal mutually.
4. semiconductor article tungsten groove contact resistance test structure according to claim 2, is characterized in that,
Between the first metal layer, the second metal level, the 3rd metal level and silicon substrate, by dielectric layer, isolated.
5. semiconductor article tungsten groove contact resistance test structure according to claim 4, is characterized in that,
Described dielectric layer is oxide, nitride or nitrogen oxide.
6. semiconductor article tungsten groove contact resistance test structure according to claim 1, is characterized in that,
This semiconductor article tungsten groove contact resistance test structure is positioned at scribe line area or the test chip district of silicon chip.
7. utilize the described semiconductor article tungsten of claim 1 to 6 any one groove contact resistance test structure to carry out the method for tungsten groove contact resistance test, it is characterized in that, comprise the following steps:
One. utilize the first metal layer of the described semiconductor article tungsten of Kelvin's connecting test groove contact resistance test structure, the resistance R between the second metal level aUtilize the second metal level of the described semiconductor article tungsten of Kelvin's connecting test groove contact resistance test structure, the resistance R between the 3rd metal level b,
Two. calculate the contact resistance R of single tungsten groove Wsink, R W sin k = ( R a - R b ) * X * Z Z - X .
CN201210154658.9A 2012-05-16 2012-05-16 Semiconductor article tungsten groove contact resistance test structure and method of testing Active CN103426865B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104808126A (en) * 2014-01-28 2015-07-29 中芯国际集成电路制造(上海)有限公司 Test structure and test method of MOS transistor
CN105223420A (en) * 2015-09-28 2016-01-06 深圳市华星光电技术有限公司 For the measuring method of the TFT and contact resistance that measure contact resistance

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5933020A (en) * 1996-10-16 1999-08-03 Vlsi Technology, Inc. Parasitic resistance measuring device
US6362638B1 (en) * 1999-09-01 2002-03-26 Agere Systems Guardian Corp. Stacked via Kelvin resistance test structure for measuring contact anomalies in multi-level metal integrated circuit technologies
US20100207648A1 (en) * 2009-02-17 2010-08-19 International Business Machines Corporation Contact Resistance Test Structure and Method Suitable for Three-Dimensional Integrated Circuits
CN102200554A (en) * 2011-03-30 2011-09-28 上海北京大学微电子研究院 Resistor test structure and method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5933020A (en) * 1996-10-16 1999-08-03 Vlsi Technology, Inc. Parasitic resistance measuring device
US6362638B1 (en) * 1999-09-01 2002-03-26 Agere Systems Guardian Corp. Stacked via Kelvin resistance test structure for measuring contact anomalies in multi-level metal integrated circuit technologies
US20100207648A1 (en) * 2009-02-17 2010-08-19 International Business Machines Corporation Contact Resistance Test Structure and Method Suitable for Three-Dimensional Integrated Circuits
CN102200554A (en) * 2011-03-30 2011-09-28 上海北京大学微电子研究院 Resistor test structure and method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104808126A (en) * 2014-01-28 2015-07-29 中芯国际集成电路制造(上海)有限公司 Test structure and test method of MOS transistor
CN105223420A (en) * 2015-09-28 2016-01-06 深圳市华星光电技术有限公司 For the measuring method of the TFT and contact resistance that measure contact resistance
WO2017054251A1 (en) * 2015-09-28 2017-04-06 深圳市华星光电技术有限公司 Tft for measuring contact resistance and contact resistance measurement method

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