CN103426813B - For carrying out the method etching reprocessing to low dielectric constant material layer - Google Patents
For carrying out the method etching reprocessing to low dielectric constant material layer Download PDFInfo
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Abstract
The invention provides a kind of method for carrying out etching reprocessing to low dielectric constant material layer, comprising: substrate is provided, provide the low dielectric constant material layer through etching with the first groove over the substrate; And use at least one in Ar and He to perform the first etching reprocessing, to make the surface densification of described low dielectric constant material layer as etching gas.The method can be repaired and be reduced the damage (such as C depletion layer) in low k dielectric, to improve the tolerance of low k dielectric to wet environment etc., and then improves the integrated electronic performance of semiconductor device.In addition, the method can also be compatible with traditional cmos manufacturing process, to reduce manufacturing cost.
Description
Technical field
The present invention relates to field of semiconductor manufacture, and in particular to one for low-k, (low k) material layer carries out the method for etching reprocessing (PET, PostEtchTreatment).
Background technology
At present, plasma etch process is widely used in the structure defining silicon integrated circuit as a kind of semiconductor fabrication process.In copper wiring technique, due to the more difficult etching of copper, so usually utilize plasma etch process to etch through hole or groove to be inserted wherein by metal thus to realize conducting interconnections (Damascus method) in interlayer dielectric (ILD) layer.
Along with IC manufactures to sub-45nm and following development, interconnect delay becomes and improves the speed of integrated circuit (IC) and a key constraints of performance.As everyone knows, in semiconductor fabrication process, one of mode minimizing interconnect delay uses low-k materials to reduce interconnection capacitance during making IC.Thus, in recent years, low-k materials (k<3.0) replaces the relatively high insulating material (e.g., silicon dioxide etc.) of dielectric constant gradually and is used as metal interlevel dielectric (IMD) layer of semiconductor device.In addition, in order to reduce the dielectric constant of insulating material further, can use and wherein form porose ultralow-k material film (k < 2.45), such as, black brill (BD) etc.This low-k dielectric layers is formed by the spin-coating method or chemical vapor deposition (CVD) method being similar to coating photoresist (PR) layer, is thus easy to compatible with existing semiconductor fabrication process.
In conventional semiconductor manufactures, usually according to the through hole in the following step making interconnection structure and groove: first, the ILD layer be such as made up of low-k materials forms metal hard mask (MHM) layer; Then, spin coating PR layer on MHM, and make it have predetermined pattern by chemical etching technique; Then, by such as plasma dry etch process by design transfer to ILD layer, to form through hole wherein; Then, PR layer is removed by such as cineration technics; Then, again etched by such as plasma dry etch process, to form groove in ILD layer, so far complete the making of through hole and groove.Here, need illustrate a bit, " interconnection structure " in the application mentioned by context comprises the ILD layer being wherein formed with through hole and/or groove and the interconnecting metal be filled in through hole and/or groove.
But, although low-k materials is widely used in semiconductor fabrication process owing to having above-mentioned plurality of advantages, use this low-k materials still can there is many problems.
First, low-k dielectric layers usually compares to traditional dielectric layer and is easy to occur damage, and such as, it is easily impaired during the etch process for carrying out composition to ILD layer and plasma ash process, and the k value of IMD is lower then more impaired, and this damage is almost inevitable.In addition, if some low-k materials is impaired, especially after patterning processes, then can become and easily absorb water or be easy to react with other processing contaminants and change the electrology characteristic of dielectric layer, thus cause the k value of low-k materials to increase and thus lose the advantage of its low k.
Secondly, in existing technique, after low-k dielectric layers is etched, usually adopt and comprise O
2, O
2/ H
2o or CO
2gas remove etching as fogging agent after residual photoresist layer etc.Owing to containing C and H element in this kind of conventional low-k materials of black brill, and the content of lower then C and H of k value is higher, and the O of these elements easily and in fogging agent reacts and generates gaseous state product, thus can form C depletion layer (i.e. damaged layer) in low-k materials, thus cause the electric property of the final semiconductor device formed to be deteriorated.
In view of the foregoing, need a kind of method for making semiconductor device, expect that the method can be repaired and reduce the damage (such as C depletion layer) in low k dielectric, to improve the tolerance of low k dielectric to wet environment etc., and then improve the integrated electronic performance of semiconductor device.In addition, also expect that the method can be compatible with traditional cmos manufacturing process, to reduce manufacturing cost.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
For solving problem existing in above-mentioned prior art, the invention provides a kind of method for carrying out etching reprocessing to low dielectric constant material layer, comprise: substrate is provided, provide the low dielectric constant material layer through etching with the first groove over the substrate; And use at least one in Ar and He to perform the first etching reprocessing, to make the surface densification of described low dielectric constant material layer as etching gas.
Preferably, described first etching reprocessing is 100 ~ 2000W and gas flow rate carries out under being the condition of 10 ~ 1000sccm at power.
Preferably, also comprise after the described first etching reprocessing of execution: described low dielectric constant material layer is etched, to form the second groove at least partially in the first groove of described low dielectric constant material layer.
Preferably, the step cycle at least partially of described first etching reprocessing and described second groove of formation is carried out, till forming complete described second groove.
Preferably, also comprise after the step at least partially forming described second groove or after forming complete described second groove: use N
2, N
2/ H
2and CH
4in at least one as etching gas perform second etching reprocessing, with repair in described low dielectric constant material layer through etching produce damage.
Preferably, formation described first groove after, perform described first etching reprocessing before also comprise: use N
2, N
2/ H
2and CH
4in at least one as etching gas perform second etching reprocessing, with repair in described low dielectric constant material layer through etching produce damage.
Preferably, described second etching reprocessing carries out at the temperature of 410 DEG C, and continue 30 minutes.
Preferably, described first etching reprocessing, the step at least partially forming described second groove and described second etching reprocessing circulation are carried out, till forming complete described second groove.
Preferably, described etching reprocessing is that original position is carried out.
Preferably, the dielectric constant of described low dielectric constant material layer is less than 3.0.
Preferably, described first groove adopts metal hard mask etched by plasma dry and formed.
Preferably, described metal hard mask is made up of at least one in TiN and BN.
The present invention further provides a kind of integrated circuit comprising the semiconductor device manufactured by method as above, wherein said integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type DRAM and radio circuit.
The present invention further provides a kind of electronic equipment comprising the semiconductor device manufactured by method as above, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
Method tool according to the present invention has the following advantages: first, by adopting the PET based on Ar or He to utilize ion bombardment effects to make low k dielectric surface densification, this compact surfaces sealing low-k materials below thus can be utilized to protect it from infringements such as wet environments; Secondly, because this compacted zone can prevent the such as copper ion of the metal ion in the metal line of filling subsequently to be diffused in low k dielectric, thus the reliability of interconnection can be improved, such as, can improve TDDB characteristic; Moreover, when adopting metal hard mask to carry out sheltering to etch low-k materials, owing to TiN can be made to cave in based on the PET of Ar or He, reducing the thickness of MHM layer, thus can make interconnecting metal such as copper filling vias or groove better.In addition, by adopting based on N
2, N
2/ H
2or CH
4pET to repair damaged layer (such as, C depletion layer), thus low k dielectric can be made to damage obviously reduce.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings:
Figure 1A-1G shows according to an exemplary embodiment of the present invention for carrying out the schematic cross sectional view of the semiconductor structure in each step of the method for PET to low-k dielectric layers; And
Fig. 2 shows the flow chart of method according to an exemplary embodiment of the present invention.
It should be noted that these figure are intended to the general characteristic according to the method used in certain exemplary embodiments of the present invention, structure and/or material is shown, and the written description provided below is supplemented.But, these figure not draw in proportion, thus accurately may can not reflect precision architecture or the performance characteristics of any given embodiment, and these figure should not be interpreted as the scope limiting or limit numerical value or the attribute contained by exemplary embodiment according to the present invention.Such as, for the sake of clarity, can to reduce or amplification molecule, layer, the relative thickness of region and/or structural detail and location.In the accompanying drawings, similar or identical Reference numeral is used to represent similar or identical element or feature.
Embodiment
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
Should be understood that, when element is referred to as " connection " or " combination " to another element, this element directly can connect or be attached to another element, or can there is intermediary element.Unlike, when element is referred to as " directly connection " or " directly combining " to another element, there is not intermediary element.In whole accompanying drawing, identical Reference numeral represents identical element all the time.As used herein, term "and/or" comprises the combination in any of one or more relevant Listed Items and all combinations.Should explain in an identical manner other words for describing the relation between element or layer (such as, " and ... between " and " directly exist ... between ", " with ... adjacent " and " with ... direct neighbor ", " ... on " and " directly to exist ... on " etc.).
In addition, it is to be further understood that, although term " first ", " second " etc. can be used here to describe different elements, assembly, region, layer and/or part, these elements, assembly, region, layer and/or part should by the restrictions of these terms.These terms are only used to an element, assembly, region, layer or part and another element, assembly, region, layer or part to make a distinction.Therefore, when not departing from the instruction according to exemplary embodiment of the present invention, the first element discussed below, assembly, region, layer or part also can be referred to as the second element, assembly, region, layer or part.
For convenience of description, here can usage space relative terms, as " ... under ", " ... on ", " below ", " in ... top ", " above " etc., be used for the spatial relation described as the element of shown in figure or feature and other elements or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except described the in the drawings orientation of device.Such as, will be positioned as after if the device in accompanying drawing is squeezed, being then described as the element of " below other elements or feature " or " under other elements or feature " " above other elements or feature " or " on other elements or feature ".Thus, exemplary term " in ... below " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and make respective explanations to used space relative descriptors here.
Here used term is only to describe specific embodiment, and is not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
At this, the schematic cross sectional view with reference to the exemplarily preferred embodiment (and intermediate structure) of property embodiment describes according to exemplary embodiment of the present invention.Like this, the change that there will be the shape illustrated such as caused by manufacturing technology and/or tolerance is estimated.Therefore, exemplary embodiment should not be interpreted as the concrete shape in the region be only limitted to shown in this, but can also comprise such as by manufacturing the form variations caused.Such as, the injection zone being depicted as rectangle can have the graded of rounding or bending feature and/or implantation concentration at its edge, and is not only the binary change from injection zone to non-implanted region.Equally, can cause also there are some at this buried regions and the region injected between the surface passed through inject by injecting the buried regions formed.Therefore, the region shown by figure is in fact schematic, and their shape is not intended to the true form in each region illustrated in device, and is not intended to limit the scope according to exemplary embodiment of the present invention.
Unless otherwise defined, otherwise whole terms used here (comprising technical term and scientific terminology) all have the meaning equivalent in meaning usually understood with those skilled in the art.It will also be understood that, unless clearly defined here, otherwise this kind of term of the term such as defined in general dictionary should be interpreted as having the consistent meaning of the meaning with them in association area linguistic context, and do not explain them with desirable or too formal implication.
[exemplary embodiment]
Below, describe in detail according to an exemplary embodiment of the present invention for carrying out etching the method for reprocessing to low-k dielectric layers with reference to Figure 1A-1G and Fig. 2.
With reference to Figure 1A-1G, illustrated therein is the schematic cross sectional view of semiconductor structure in each step of method according to the present invention comprising low-k dielectric layers.
First, provide substrate 110, as shown in Figure 1A, provide the low-k dielectric layers 120 through etching with the first groove 121 on a substrate 110.Wherein, the first groove 121 can be through hole or the groove of the formation semiconductor device interconnected structure of definition usually in this area.But in this article, for convenience, the through hole of ordinary meaning or groove are referred to as groove.Should give understanding, because through hole or groove in manufacture only have difference at the most in the degree of depth and internal diameter, without substantive difference, practical significance both thus distinguishing is also little.Therefore, both are referred to as groove, also can not obscure scope of the present invention.In this example, the first groove is the through hole of definition usually.
Exemplarily, substrate 110 can be such as unadulterated monocrystalline silicon, monocrystalline silicon, germanium silicon or silicon-on-insulator (SOI) etc. doped with N-type or p type impurity.The thickness of low-k dielectric layers 120 is about
isolate for making device and metal interconnecting layer in subsequent metal interconnection process.In addition, one deck undoped silicon glass (USG) can also be provided below low-k dielectric layers 120 or mix phosphorosilicate glass (PSG) (not shown), to provide comparatively smooth surface, for forming low-k dielectric layers 120 thereon by spin-coating method or CVD.
Exemplarily, the constituent material of low-k dielectric layers 120 can be BlackDiamond
tMiI(BDII) dielectric.This dielectric substance is the silica (also referred to as silicon oxide carbide) of carbon doping, wherein carbon content is higher than 10%, it is commercially available by applied materials, inc. of California, USA Sheng great Ke Laola city, and it is improved material and comprises and to be hardened by UV and to have the BDIIx dielectric of the porosity of 30% and the BDIIebeam dielectric by electron-beam curing.In addition, the low-k materials of other carbon containings comprises
with
(benzocyclobutene) dielectric material, it is by DowChemical companies market.In these materials, majority is organic or polyelectrolye, easily and oxygen or oxonium ion react and generate gaseous state thing and be consumed.
Here, need be understood, the method forming the first groove in low-k dielectric layers 120 is known in those skilled in the art, therefore repeats no more herein.In addition, due to different mask layers can be adopted according to practical application, even if thus after stripping photoresist (PR) layer, above low-k dielectric layers 120, other materials layer (not shown) may also be left.Such as, when adopting metal hard mask (MHM, MetalHardMask), after stripping PR layer, TiN or the BN layer as MHM can be left above low-k dielectric layers 120.If TiN or the BN layer stayed is blocked up, then can affects follow-up metal filled, thus affect metal interconnected reliability.
Then, perform the first etching reprocessing (PET), to make the surface densification of low-k dielectric layers 120, thus form dense surface layer 122, as shown in Figure 1B.The object of this step is to form compact surfaces for sealing low-k materials below, to protect low-k materials from wet environment or the infringement of other processing contaminants.As an example, Ar can be used to carry out Ions Bombardment as etching gas to the surface of low-k dielectric layers 120, to perform a PET.As another example, He can be used to carry out Ions Bombardment as etching gas to the surface of low-k dielectric layers 120, to perform a PET.Certainly, Ar and He also can be used to carry out Ions Bombardment as etching gas to the surface of low-k dielectric layers 120, to perform a PET simultaneously.Preferably, the process conditions of a PET are as follows: power is 100 ~ 2000W, and gas flow rate is 10 ~ 1000sccm, and wherein, sccm is under standard state, i.e. 1 atmospheric pressure, 1 cubic centimetre of (1cm per minute at 25 DEG C
3/ min) flow.
Here, need be understood, because a PET uses inert gas Ar and He, so less to the chemical damage of low-k dielectric layers generation.
Then, low-k dielectric layers 120 is etched, to form the 126a at least partially of the second groove wherein, as shown in Figure 1 C.Wherein, the second groove has the implication identical with the first groove in this article.In this example, the second groove is the groove of definition usually.From Fig. 1 C, do not have compact surfaces to provide protection due to during etching forming section second groove 126a in the latter half of low-k dielectric layers 120 sidewall, thus can form damaged layer 123 in low-k dielectric layers 120, such as C depletion layer.
Then, performing the 2nd PET, to repair through the damaged layer 123 that etching produces in low-k dielectric layers 120, thus obtaining the damaged layer 123a through repairing as shown in figure ip.Should give understanding, though this PET step is optional, is preferred.As an example, N can be used
2the 2nd PET is performed as etching gas.As another example, N can be used
2/ H
2the 2nd PET is performed as etching gas.As another example, CH can be used
4the 2nd PET is performed as etching gas.Certainly, also N can be used
2, N
2/ H
2and CH
4any combination as etching gas.In addition, exemplarily, the 2nd PET can carry out at the temperature of such as 410 DEG C, and continues 30 minutes.
Here, need be recognized, by based on N
2, N
2/ H
2or CH
4pET can repair damaged layer 123 at least in part, such as, produce in etching process or owing to using containing O or O
2fogging agent peel off PR and the C depletion layer that formed, thus the damage in low-k dielectric layers can be made obviously to reduce, as shown in figure ip.The principle of repairing is conventionally known to one of skill in the art, therefore repeats no more herein.
Then, repeat a PET, as referring to figure 1e, damaged layer 123a place after repair also form dense surface layer 123b, to prevent etching gas such as F ion to be diffused into low-k dielectric layers when subsequent etch, causes damage to it.Then, the method same with forming section second groove 126a is adopted in low-k dielectric layers 120, to form the second complete groove 126, the groove 126 namely in this example.Certainly, damaged layer 124 can be formed too at the sidewall of groove 126.This damaged layer 124 also can be repaired by again performing the 2nd PET as mentioned above, and the damaged layer after reparation as shown in Figure 1 G.
Referring to Fig. 2, illustrated therein is the flow chart of method according to an exemplary embodiment of the present invention.
First, in step s 201, provide substrate, provide the low-k dielectric layers through etching with the first groove over the substrate.
Then, in step S202, at least one in Ar and He is used to perform a PET, to make the surface densification of described low-k dielectric layers as etching gas.
Then, in step S203, described low-k dielectric layers is etched, to form the second groove at least partially in described low-k dielectric layers.
Then, optional and not necessarily, in step S204, use N
2, N
2/ H
2and CH
4in at least one as etching gas perform the 2nd PET, with repair in described low-k dielectric layers through etching produce damage.Preferably, the 2nd PET carries out at the temperature of 410 DEG C, and continues 30 minutes.
Then, in step S205, repeated execution of steps S202 to S204, to form the remainder of the second groove, thus obtains the second complete groove.
Here, what needs were stressed is, although a PET, the second trench etch and the 2nd PET only circulate and have carried out twice in this exemplary embodiment, but those skilled in the art will recognize that, can be according to actual needs, once circulate or circulate three times or more, till forming the second complete groove.Such as, if be divided into by the second groove three step etchings to be formed, then cycle-index can be three times.
In addition, those skilled in the art can know the first groove according to foregoing description and the second groove can exchange, namely, first groove can be groove second groove of definition is usually then the through hole of definition usually, scheme (namely with adopting " first through hole (via-first) " in above-mentioned exemplary embodiment, groove after first through hole) dual damascene process different, it is known in the industry as the dual damascene process of employing " first groove (trench-first) " scheme (that is, through hole after first groove).Certainly, wherein the first groove through hole of not only having comprised definition usually but also the scheme of the groove comprising definition usually also fall within scope of the present invention.
In addition, when those skilled in the art it will also be appreciated that a PET and the 2nd PET is carried out in circulation, the etching gas that a PET is each used with the 2nd PET can be identical, also can be different.Such as, circulation time for the first time, can use Ar to perform a PET and use N
2perform the 2nd PET, and at second time circulation time, He can be used to perform a PET and use CH
4perform the 2nd PET, the rest may be inferred.
Here, need draw attention to, the 2nd PET described above is preferred and nonessential, so the situation not performing the 2nd PET in fact can be there is, in this case, only need circulation execution the one PET and the second trench etch step, till obtaining the second complete groove.Certainly, also there is such situation, namely before forming the second complete groove, do not perform the 2nd PET, and use N after obtaining the second complete groove
2, N
2/ H
2and CH
4in at least one as etching gas perform the 2nd PET, to repair damage.In addition, also may there is such situation, namely after formation first groove, perform before a PET, perform the 2nd PET as mentioned above, with at that time both established damage repair.This several situation equally also all falls within the scope of the present invention.
In addition, also need to draw attention to, a PET and the 2nd PET can be all that original position (in-situ) is carried out, and namely is all carrying out carrying out in the chamber etched.Can the production cycle be shortened like this and reduce manufacturing cost.
About beneficial effect of the present invention, those skilled in the art can both recognize, can utilize the semiconductor device interconnected structure making the reliability with improvement as mentioned above according to method of the present invention.Because the various method and the concrete technology condition thereof that make semiconductor device interconnected structure are all known in the art, the dual damascene process etc. such as adopted at present, therefore repeats no more herein.
Here, it will be appreciated that, because the compacted zone formed on low k dielectric surface can prevent metal ion in metal line (such as, copper ion) be diffused in low k dielectric, thus the reliability of interconnection structure can be improved, such as can improve time dependence dielectric breakdown (TDDB, Time-DependentDielectricBreakdown) characteristic.In addition, when adopting TiN or BN as metal hard mask etching low-k materials, owing to can make metal hard mask such as TiN or BN depression based on the PET of Ar or He, reduce the thickness of MHM layer, thus interconnecting metal can be made to be filled in better in the gap such as through hole or groove, thus also can to reach the object of the reliability improving interconnection structure.
[industrial applicibility of the present invention]
Can be applicable in multiple integrated circuit (IC) according to the semiconductor device that embodiment as above manufactures.Such as memory circuitry according to IC of the present invention, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcies arbitrarily.IC chip according to the present invention can be used for such as consumer electronic products, as in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition, it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (10)
1., for carrying out the method etching reprocessing to low dielectric constant material layer, comprising:
Substrate is provided, provides the low dielectric constant material layer through etching with the first groove over the substrate; And
At least one in Ar and He is used to perform the first etching reprocessing, to make the surface densification of described low dielectric constant material layer as etching gas;
Also comprise after the described first etching reprocessing of execution: described low dielectric constant material layer is etched, to form the second groove at least partially in the first groove of described low dielectric constant material layer;
Wherein, the step cycle at least partially of described first etching reprocessing and described second groove of formation is carried out, till forming complete described second groove.
2. method according to claim 1, wherein, described first etching reprocessing is 100 ~ 2000W and gas flow rate carries out under being the condition of 10 ~ 1000sccm at power.
3. method according to claim 1, also comprises after the step at least partially forming described second groove or after forming complete described second groove: use N
2, N
2/ H
2and CH
4in at least one as etching gas perform second etching reprocessing, with repair in described low dielectric constant material layer through etching produce damage.
4. method according to claim 1, formation described first groove after, perform described first etching reprocessing before also comprise: use N
2, N
2/ H
2and CH
4in at least one as etching gas perform second etching reprocessing, with repair in described low dielectric constant material layer through etching produce damage.
5. the method according to claim 3 or 4, wherein, described second etching reprocessing carries out at the temperature of 410 DEG C, and continue 30 minutes.
6. method according to claim 3, wherein, described first etching reprocessing, the step at least partially forming described second groove and described second etching reprocessing circulation are carried out, till forming complete described second groove.
7. the method according to claim 1,3 or 4, wherein, described first etching reprocessing and/or the second etching reprocessing are that original position is carried out.
8. method according to claim 1, wherein, the dielectric constant of described low dielectric constant material layer is less than 3.0.
9. method according to claim 1, wherein, described first groove adopts metal hard mask etched by plasma dry and formed.
10. want the method described in 9 according to right, wherein, described metal hard mask is made up of at least one in TiN and BN.
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| KR20080074494A (en) * | 2007-02-09 | 2008-08-13 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
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| US6114259A (en) * | 1999-07-27 | 2000-09-05 | Lsi Logic Corporation | Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage |
| US6537896B1 (en) * | 2001-12-04 | 2003-03-25 | Lsi Logic Corporation | Process for treating porous low k dielectric material in damascene structure to form a non-porous dielectric diffusion barrier on etched via and trench surfaces in the porous low k dielectric material |
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|---|---|
| CN103426813A (en) | 2013-12-04 |
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