CN103426813A - Method for carrying out etching post-processing on low-dielectric-constant material layer - Google Patents
Method for carrying out etching post-processing on low-dielectric-constant material layer Download PDFInfo
- Publication number
- CN103426813A CN103426813A CN2012101625400A CN201210162540A CN103426813A CN 103426813 A CN103426813 A CN 103426813A CN 2012101625400 A CN2012101625400 A CN 2012101625400A CN 201210162540 A CN201210162540 A CN 201210162540A CN 103426813 A CN103426813 A CN 103426813A
- Authority
- CN
- China
- Prior art keywords
- etching
- groove
- low
- material layer
- constant material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides a method for carrying out etching post-processing on a low-dielectric-constant material layer. The method for carrying out etching post-processing on the low-dielectric-constant material layer includes the following steps that a substrate is provided and a low-dielectric-constant material layer which undergoes etching and is provided with a first groove is arranged on the substrate; at least one of Ar and He serves as an etching gas for carrying out first etching post-processing, so that the surface of the low-dielectric-constant material layer is densified. The method for carrying out etching post-processing on the low-dielectric-constant material layer can repair and reduce damage to a low k dielectric layer (for example, a C depletion layer) and the capability of the low k dielectric layer for resisting to the humid environment and the like is improved and therefore, the overall electric performances of a semiconductor device are improved. In addition, the method for carrying out etching post-processing on the low-dielectric-constant material layer is also compatible with the traditional CMOS manufacturing technology in order to reduce manufacturing cost.
Description
Technical field
The present invention relates to field of semiconductor manufacture, and in particular to a kind of for low-k (low k) material layer is carried out to the method for etching reprocessing (PET, Post Etch Treatment).
Background technology
At present, plasma etch process is widely used in defining the structure of silicon integrated circuit as a kind of semiconductor fabrication process.In copper wiring technique, due to the more difficult etching of copper, so usually utilize plasma etch process in interlayer dielectric (ILD) thus etching through hole or groove in layer wherein realizes conductivity interconnection (Damascus method) so that metal is inserted.
Along with IC manufactures to inferior 45nm and following development, interconnect delay becomes the speed of raising integrated circuit (IC) and a key constraints of performance.As everyone knows, one of mode that minimizes interconnect delay in semiconductor fabrication process is to reduce interconnection capacitance with low-k materials during making IC.Thereby in recent years, low-k materials (k<3.0) has replaced gradually the insulating material that dielectric constant is relatively high (as, silicon dioxide etc.) and has been used as metal interlevel dielectric (IMD) layer of semiconductor device.In addition, in order further to reduce the dielectric constant of insulating material, can to use, wherein form porose ultralow k material (k<2.45), for example, black brill (BD) etc.This low-k materials layer can form by being similar to the spin-coating method or the chemical vapor deposition (CVD) method that apply photoresist (PR) layer, thereby is easy to and existing semiconductor fabrication process compatibility.
In conventional semiconductor is manufactured, usually according to the following step, make through hole and the groove in interconnection structure: at first, form metal hard mask (MHM) layer on the ILD layer for example formed by low-k materials; Then, spin coating PR layer on MHM, and make it there is predetermined pattern by chemical etching technique; Then, by plasma dry etch process for example by design transfer to the ILD layer, to form therein through hole; Then, remove the PR layer by for example cineration technics; Then, again by for example plasma dry etch process, carry out etching, in the ILD layer, to form groove, so far complete the making of through hole and groove.Here, need explanation a bit, in the application, mentioned " interconnection structure " of context comprises the ILD layer that wherein is formed with through hole and/or groove and is filled in the interconnecting metal in through hole and/or groove.
Yet, although low-k materials is widely used in semiconductor fabrication process owing to having above-mentioned plurality of advantages, use this low-k materials still can have many problems.
At first, the low-k materials layer usually compares to traditional dielectric layer and is easy to damage occur, and for example, it is easily impaired during the etch process for the ILD layer being carried out to composition and plasma ashing technique, and the k value of IMD is lower more impaired, and this damage is almost inevitable.In addition, if some low-k materials is impaired, especially after composition technique, the electrology characteristic that can become and easily absorb water or be easy to change with other technique pollutant reactions dielectric layer, thus cause the k value of low-k materials to increase and thereby lose the advantage of its low k.
Secondly, in existing technique, after the low-k materials layer is carried out to etching, usually adopt and comprise O
2, O
2/ H
2O or CO
2Gas remove photoresist layer residual after etching etc. as fogging agent.Because black boring in this class low-k materials commonly used contained C and H element, and the content of the lower C of k value and H is higher, and these elements easily with fogging agent in the O generation gaseous state product that reacts, thereby can form C depletion layer (being damaged layer) in low-k materials, thereby cause the electric property variation of the semiconductor device of final formation.
In view of the foregoing, need a kind of for making the method for semiconductor device, the damage (for example C depletion layer) in low k dielectric can be repaired and reduce to expectation the method, to improve the tolerance of low k dielectric to wet environment etc., and then improves the integrated electronic performance of semiconductor device.In addition, also expect the method can with traditional cmos manufacturing process compatibility, to reduce manufacturing cost.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
For solving existing problem in above-mentioned prior art, the invention provides a kind of for low dielectric constant material layer being carried out to the method for etching reprocessing, comprise: substrate is provided, provides the low dielectric constant material layer that there is the first groove through etching on described substrate; And use at least one in Ar and He to carry out the first etching reprocessing as etching gas, so that the surface densification of described low dielectric constant material layer.
Preferably, described the first etching reprocessing is to carry out under 100 ~ 2000W and the gas flow rate condition that is 10 ~ 1000sccm at power.
Preferably, after carrying out described the first etching reprocessing, also comprise: described low dielectric constant material layer is carried out to etching, to form at least a portion of the second groove in the first groove of described low dielectric constant material layer.
Preferably, the step cycle of at least a portion of described the first etching reprocessing and described the second groove of formation is carried out, until form complete described the second groove.
Preferably, after the step of at least a portion that forms described the second groove or after forming complete described the second groove, also comprise: use N
2, N
2/ H
2And CH
4In at least one carry out the second etching reprocessing as etching gas, to repair in described low dielectric constant material layer the damage produced through etching.
Preferably, after forming described the first groove, also comprise before carrying out described the first etching reprocessing: use N
2, N
2/ H
2And CH
4In at least one carry out the second etching reprocessing as etching gas, to repair in described low dielectric constant material layer the damage produced through etching.
Preferably, described the second etching reprocessing is to carry out at the temperature of 410 ℃, and continues 30 minutes.
Preferably, described the first etching reprocessing, the step and described the second etching reprocessing that form at least a portion of described the second groove loop, until form complete described the second groove.
Preferably, described etching reprocessing is that original position is carried out.
Preferably, the dielectric constant of described low dielectric constant material layer is less than 3.0.
Preferably, described the first groove adopts metal hard mask to form by the plasma dry etching.
Preferably, described metal hard mask is that at least one in TiN and BN forms.
The present invention further provides a kind of integrated circuit that comprises the semiconductor device of manufacturing by method as above, wherein said integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type DRAM and radio circuit.
The present invention further provides a kind of electronic equipment that comprises the semiconductor device of manufacturing by method as above, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
The method according to this invention has following advantage: at first, by adopting PET based on Ar or He to utilize ion bombardment effects, so that the low k dielectric surface densification, thereby can utilize this compact surfaces to seal following low-k materials to protect it to avoid the infringements such as wet environment; Secondly, the metal ion in the metal line that can prevent from filling subsequently due to this compacted zone for example copper ion is diffused in low k dielectric, thereby can improve the reliability of interconnection, for example can improve the TDDB characteristic; Moreover, in the situation that adopt metal hard mask to be sheltered with the etching low-k materials, because the PET based on Ar or He can make the TiN depression, reduced the thickness of MHM layer, thereby can make for example copper filling vias or groove better of interconnecting metal.In addition, by adopting based on N
2, N
2/ H
2Or CH
4PET for example, to repair damaged layer (, the C depletion layer), thereby can make the low k dielectric damage obviously reduce.
The accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings:
Figure 1A-1G shows according to an exemplary embodiment of the present invention the schematic cross sectional view of semiconductor structure of each step of the method for the low-k materials layer being carried out to PET; And
Fig. 2 shows the flow chart of method according to an exemplary embodiment of the present invention.
It should be noted in the discussion above that these figure are intended to illustrate the general characteristic according to the method for using in certain exemplary embodiments of the present invention, structure and/or material, and the written description provided is below supplemented.Yet, these figure not draw in proportion, thereby may can accurately not reflect precision architecture or the characteristic of property of any given embodiment, and the numerical value that these figure should not be interpreted as limiting or restriction is contained by exemplary embodiment according to the present invention or the scope of attribute.For example, for the sake of clarity, can dwindle or amplify relative thickness and the location of molecule, layer, zone and/or structural detail.In the accompanying drawings, use similar or identical Reference numeral to mean similar or identical element or feature.
Embodiment
Now, describe in more detail according to exemplary embodiment of the present invention with reference to the accompanying drawings.Yet these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skills.In the accompanying drawings, for the sake of clarity, exaggerated layer and regional thickness, and used identical Reference numeral to mean identical element, thereby will omit description of them.
Should be understood that, when element is known as " connection " or " combination " to another element, this element can directly connect or be attached to another element, or can have intermediary element.Different, when element is known as " directly connection " or " directly combination " to another element, there do not is intermediary element.In whole accompanying drawings, identical Reference numeral means identical element all the time.As used herein, term " and/or " comprise combination in any and all combinations of one or more relevant Listed Items.Should explain in an identical manner other words for describing the relation between element or layer (for example, " and ... between " and " directly exist ... between ", " with ... adjacent " and " with ... direct neighbor ", " ... on " and " directly exist ... on " etc.).
In addition, it is to be further understood that, although can use term " first ", " second " etc. to describe different elements, assembly, zone, layer and/or part here, these elements, assembly, zone, layer and/or part should not be subject to the restriction of these terms.These terms are only for an element, assembly, zone, layer or part and another element, assembly, zone, layer or part are made a distinction.Therefore, in the situation that do not break away from the instruction according to exemplary embodiment of the present invention, the first element discussed below, assembly, zone, layer or part also can be known as the second element, assembly, zone, layer or part.
For convenience of description, here can the usage space relative terms, as " ... under ", " ... on ", " following ", " in ... top ", " top " etc., be used for describing the spatial relation as element as shown in figure or feature and other elements or feature.Should be understood that, the space relative terms is intended to comprise the different azimuth in using or operating except the orientation that device described in the drawings.For example, if the device in accompanying drawing is squeezed, be described as being positioned as " above other elements or feature " or " on other elements or feature " after the element of " below other elements or feature " or " under other elements or feature ".Thereby exemplary term " in ... below " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or in other orientation), and the space relative descriptors used is here made to respective explanations.
Here the term that used is only in order to describe specific embodiment, but not the intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative also is intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
At this, with reference to the schematic cross sectional view of the preferred embodiment (and intermediate structure) as exemplary embodiment, describe according to exemplary embodiment of the present invention.Like this, estimate there will be the variation of the shape illustrated for example caused by manufacturing technology and/or tolerance.Therefore, exemplary embodiment should not be interpreted as only limiting to the concrete shape in the zone shown in this, but can also comprise for example by manufacturing the form variations caused.For example, the injection zone that is depicted as rectangle can have rounding or the feature of bending and/or the graded of implantation concentration at its edge, and the binary of being not only from injection zone to the non-injection regions territory changes.Equally, the buried regions formed by injection can cause at this buried regions and also can there be some injections in the zone of injecting between the surface pass through.Therefore, scheming shown zone is in fact that schematically their shape is not intended to illustrate each the regional true form in device, and is not intended to the scope of restriction according to exemplary embodiment of the present invention.
Unless otherwise defined, otherwise whole terms of using here (comprising technical term and scientific terminology) all have the meaning equivalent in meaning of usually understanding with those skilled in the art.It will also be understood that, unless clearly definition here, otherwise should be interpreted as thering is the meaning consistent with they meanings in the association area linguistic context such as this class term of the term defined in general dictionary, and with desirable or too formal implication, not explain them.
[exemplary embodiment]
Below, with reference to Figure 1A-1G and Fig. 2, describe in detail according to an exemplary embodiment of the present invention for the low-k materials layer being carried out to the method for etching reprocessing.
With reference to Figure 1A-1G, wherein show the schematic cross sectional view of semiconductor structure in each step of the method according to this invention that comprises the low-k materials layer.
At first, provide substrate 110, as shown in Figure 1A, provide the low-k materials layer 120 that there is the first groove 121 through etching on substrate 110.Wherein, the first groove 121 can be through hole or the groove of the formation semiconductor device interconnected structure of common definition in this area.But in this article, for convenience, the through hole of ordinary meaning or groove are referred to as to groove.Should give and be understood that, due to through hole in manufacturing or groove at the most only aspect the degree of depth and internal diameter, having difference without substantive difference, thereby distinguish both practical significances little.Therefore, both are referred to as to groove, also can obscure scope of the present invention.In this example, the first groove is usually the through hole of definition.
As example, substrate 110 such as can be unadulterated monocrystalline silicon, monocrystalline silicon, germanium silicon or silicon-on-insulator (SOI) etc. doped with N-type or p type impurity.The thickness of low-k materials layer 120 is about
For make device and metal interconnecting layer isolation in follow-up metal interconnected technique.In addition, one deck undoped silicon glass (USG) can also be provided below low-k materials layer 120 or mix phosphorosilicate glass (PSG) (not shown), in order to comparatively smooth surface is provided, for by spin-coating method or CVD method, forming low-k materials layer 120 thereon.
As example, the constituent material of low-k materials layer 120 can be Black Diamond
TMII(BDII) dielectric.The silica (also referred to as silicon oxide carbide) that this dielectric substance is the carbon doping, wherein carbon content is higher than 10%, it is commercially available by the holy large Ke Laola of California, USA city Applied Materials company, and it improves material and comprises by UV and harden and have the BDIIx dielectric of 30% porosity and pass through the BDIIebeam dielectric of electron-beam curing.In addition, the low-k materials of other carbon containings comprises
With
(benzocyclobutene) dielectric material, it is commercially available by Dow Chemical company.In these materials, majority is organic or polyelectrolye, easily with oxygen or oxonium ion, reacts generation gaseous state thing and is consumed.
Here, need be understood that, the method that forms the first groove in low-k materials layer 120 is known in those skilled in the art, so this paper repeats no more.In addition, owing to according to the practical application meeting, adopting different mask layers, even thereby after stripping photoresist (PR) layer, also may leave other materials layer (not shown) above low-k materials layer 120.For example, in the situation that adopts metal hard mask (MHM, Metal Hard Mask), after peeling off the PR layer, can stay TiN or BN layer as MHM above low-k materials layer 120.If the TiN stayed or BN layer are blocked up, can affect follow-up metal filled, thereby affect metal interconnected reliability.
Then, carry out the first etching reprocessing (PET), so that the surface densification of low-k materials layer 120, thereby form compact surfaces layer 122, as shown in Figure 1B.The purpose of this step is to form compact surfaces for sealing following low-k materials, with the protection low-k materials, avoids wet environment or the infringement of other technique pollutants.As an example, can use Ar, as etching gas, Ions Bombardment is carried out in the surface of low-k materials layer 120, to carry out a PET.As another example, can use He, as etching gas, Ions Bombardment is carried out in the surface of low-k materials layer 120, to carry out a PET.Certainly, also can use Ar and He, as etching gas, Ions Bombardment is carried out in the surface of low-k materials layer 120, to carry out a PET simultaneously.Preferably, the process conditions of a PET are as follows: power is 100 ~ 2000W, and gas flow rate is 10 ~ 1000sccm, and wherein, sccm is under standard state, i.e. 1 cubic centimetre of (1cm per minute under 1 atmospheric pressure, 25 ℃
3/ min) flow.
Here, need be understood, that use due to a PET is inert gas Ar and He, so the chemical damage that the low-k materials layer is produced is less.
Then, low-k materials layer 120 is carried out to etching, to form therein at least a portion 126a of the second groove, as shown in Figure 1 C.Wherein, the second groove has the implication identical with the first groove in this article.In this example, the second groove is usually the groove of definition.From Fig. 1 C, the latter half at low-k materials layer 120 sidewall during due to etching forming section the second groove 126a does not have compact surfaces that protection is provided, thereby can form damaged layer 123, for example C depletion layer in low-k materials layer 120.
Then, carry out the 2nd PET, to repair the damaged layer 123 produced through etching in low-k materials layer 120, thereby obtain the damaged layer 123a through repairing as shown in Fig. 1 D.Should give and be understood that, though this PET step is optional, is preferred.As an example, can use N
2Carry out the 2nd PET as etching gas.As another example, can use N
2/ H
2Carry out the 2nd PET as etching gas.As another example, can use CH
4Carry out the 2nd PET as etching gas.Certainly, also can use N
2, N
2/ H
2And CH
4Arbitrary combination as etching gas.In addition, as example, the 2nd PET can for example carry out at the temperature of 410 ℃, and continues 30 minutes.
Here, need be recognized, by based on N
2, N
2/ H
2Or CH
4PET can repair at least in part damaged layer 123, for example, in etching process, produce or owing to using containing O or O
2Fogging agent peel off PR and the C depletion layer that forms, thereby can make the damage in the low-k materials layer obviously reduce, as shown in Fig. 1 D.The principle of repairing is conventionally known to one of skill in the art, so this paper repeats no more.
Then, repeat a PET, as shown in Fig. 1 E, the damaged layer 123a place after reparation has also formed compact surfaces layer 123b, so as when subsequent etch, to prevent etching gas for example the F ion be diffused into the low-k materials layer, it is caused to damage.Then, adopt the method same with forming section the second groove 126a to form the second complete groove 126, i.e. groove in this example 126 in low-k materials layer 120.Certainly, the sidewall at groove 126 can form damaged layer 124 too.This damaged layer 124 also can be repaired by again carrying out as mentioned above the 2nd PET, and the damaged layer after reparation as shown in Figure 1 G.
Below with reference to Fig. 2, wherein show the flow chart of method according to an exemplary embodiment of the present invention.
At first, in step S201, provide substrate, provide the low-k materials layer that there is the first groove through etching on described substrate.
Then, in step S202, at least one in use Ar and He carried out a PET as etching gas, so that the surface densification of described low-k materials layer.
Then, in step S203, described low-k materials layer is carried out to etching, to form at least a portion of the second groove in described low-k materials layer.
Then, optional and not necessarily, in step S204, use N
2, N
2/ H
2And CH
4In at least one carry out the 2nd PET as etching gas, to repair the damage produced through etching in described low-k materials layer.Preferably, the 2nd PET carries out at the temperature of 410 ℃, and continues 30 minutes.
Then, in step S205, repeated execution of steps S202 to S204, to form the remainder of the second groove, thereby obtain the second complete groove.
Here, what need to stress is, although in this exemplary embodiment, a PET, the second trench etch and the 2nd PET have only looped twice, but those skilled in the art will recognize that, can be according to actual needs, once circulate or three times or more times circulation, until form the second complete groove.For example, if the second groove is divided into to three step etchings, form, cycle-index can be three times.
In addition, those skilled in the art can know the first groove according to foregoing description and the second groove can exchange,, the first groove can be that groove second groove of definition usually is the common through hole defined, with adopting " first through hole (via-first) " in above-mentioned exemplary embodiment, scheme (, groove after first through hole) dual damascene process difference, it is known in the industry as the dual damascene process of employing " first groove (trench-first) " scheme (that is, through hole after first groove).Certainly, within the scheme that wherein the first groove had not only comprised the through hole of common definition but also comprised the groove of common definition also falls into scope of the present invention.
In addition, those skilled in the art it will also be appreciated that while looping a PET and the 2nd PET, and a PET and each the used etching gas of the 2nd PET can be identical, also can be different.For example, circulation time, can be used Ar to carry out a PET and use N for the first time
2Carry out the 2nd PET, and, at circulation time for the second time, can use He to carry out a PET and use CH
4Carry out the 2nd PET, the rest may be inferred.
Here, need draw attention to, the 2nd PET is preferred and nonessential as mentioned above, so in fact can have the situation of not carrying out the 2nd PET, in this case, only need circulation execution the one PET and the second trench etch step to get final product, until obtain the second complete groove.Certainly, also there is such situation, before forming the second complete groove, do not carry out the 2nd PET, and use N after obtaining the second complete groove
2, N
2/ H
2And CH
4In at least one carry out the 2nd PET as etching gas, to repair damage.In addition, also may have such situation, after forming the first groove, carry out a PET before, carry out as mentioned above the 2nd PET, with at that time both established damage repaired.These several situations also all fall within the scope of the present invention equally.
In addition, also need to draw attention to, a PET and the 2nd PET can be all that original position (in-situ) is carried out, and all in carrying out etched chamber, carry out.Can shorten like this production cycle and reduce manufacturing cost.
About beneficial effect of the present invention, those skilled in the art can both recognize, can utilize the method according to this invention as mentioned above to make the semiconductor device interconnected structure of the reliability with improvement.Because the whole bag of tricks and the concrete technology condition thereof of making semiconductor device interconnected structure are all known in the art, such as the dual damascene process of current employing etc., so this paper repeats no more.
Here, it will be appreciated that, metal ion due to the compacted zone formed on low k dielectric surface in can preventing metal line (for example, copper ion) be diffused in low k dielectric, thereby can improve the reliability of interconnection structure, for example can improve time dependence dielectric breakdown (TDDB, Time-Dependent Dielectric Breakdown) characteristic.In addition, in the situation that adopt TiN or BN as metal hard mask etching low-k materials, because the PET based on Ar or He can make metal hard mask for example TiN or BN depression, reduced the thickness of MHM layer, thereby can make interconnecting metal be filled in better in the gaps such as through hole or groove, thereby also can reach the purpose of the reliability of improving interconnection structure.
[industrial applicibility of the present invention]
According to the semiconductor device of embodiment manufacture as above, can be applicable in multiple integrated circuit (IC).According to IC of the present invention, be for example memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.According to IC of the present invention, can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the purpose for giving an example and illustrating just, but not is intended to the present invention is limited in described scope of embodiments.In addition, it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (12)
1. one kind for carrying out the method for etching reprocessing to low dielectric constant material layer, comprising:
Substrate is provided, provides the low dielectric constant material layer that there is the first groove through etching on described substrate; And
At least one in use Ar and He carried out the first etching reprocessing as etching gas, so that the surface densification of described low dielectric constant material layer.
2. method according to claim 1, wherein, described the first etching reprocessing is to carry out under 100 ~ 2000W and the gas flow rate condition that is 10 ~ 1000sccm at power.
3. method according to claim 1 also comprises: described low dielectric constant material layer is carried out to etching, to form at least a portion of the second groove in the first groove of described low dielectric constant material layer after carrying out described the first etching reprocessing.
4. method according to claim 3, wherein, described the first etching reprocessing and the step cycle that forms at least a portion of described the second groove are carried out, until form complete described the second groove.
5. method according to claim 4 also comprises: use N after the step of at least a portion that forms described the second groove or after forming complete described the second groove
2, N
2/ H
2And CH
4In at least one carry out the second etching reprocessing as etching gas, to repair in described low dielectric constant material layer the damage produced through etching.
6. method according to claim 1 also comprises: use N after forming described the first groove, before carrying out described the first etching reprocessing
2, N
2/ H
2And CH
4In at least one carry out the second etching reprocessing as etching gas, to repair in described low dielectric constant material layer the damage produced through etching.
7. according to the described method of claim 5 or 6, wherein, described the second etching reprocessing is to carry out at the temperature of 410 ℃, and continues 30 minutes.
8. method according to claim 5, wherein, described the first etching reprocessing, the step and described the second etching reprocessing that form at least a portion of described the second groove loop, until form complete described the second groove.
9. according to claim 1,5 or 6 described methods, wherein, described etching reprocessing is that original position is carried out.
10. method according to claim 1, wherein, the dielectric constant of described low dielectric constant material layer is less than 3.0.
11. method according to claim 1, wherein, described the first groove adopts metal hard mask to form by the plasma dry etching.
12. want 11 described methods according to right, wherein, described metal hard mask is that at least one in TiN and BN forms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210162540.0A CN103426813B (en) | 2012-05-21 | 2012-05-21 | For carrying out the method etching reprocessing to low dielectric constant material layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210162540.0A CN103426813B (en) | 2012-05-21 | 2012-05-21 | For carrying out the method etching reprocessing to low dielectric constant material layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103426813A true CN103426813A (en) | 2013-12-04 |
| CN103426813B CN103426813B (en) | 2016-02-03 |
Family
ID=49651366
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210162540.0A Active CN103426813B (en) | 2012-05-21 | 2012-05-21 | For carrying out the method etching reprocessing to low dielectric constant material layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103426813B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105336664A (en) * | 2014-06-13 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Etching method |
| CN108493104A (en) * | 2018-04-10 | 2018-09-04 | 睿力集成电路有限公司 | Method for etching plasma and plasma etching post-processing approach |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114259A (en) * | 1999-07-27 | 2000-09-05 | Lsi Logic Corporation | Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage |
| US6537896B1 (en) * | 2001-12-04 | 2003-03-25 | Lsi Logic Corporation | Process for treating porous low k dielectric material in damascene structure to form a non-porous dielectric diffusion barrier on etched via and trench surfaces in the porous low k dielectric material |
| KR20080074494A (en) * | 2007-02-09 | 2008-08-13 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
-
2012
- 2012-05-21 CN CN201210162540.0A patent/CN103426813B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114259A (en) * | 1999-07-27 | 2000-09-05 | Lsi Logic Corporation | Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage |
| US6537896B1 (en) * | 2001-12-04 | 2003-03-25 | Lsi Logic Corporation | Process for treating porous low k dielectric material in damascene structure to form a non-porous dielectric diffusion barrier on etched via and trench surfaces in the porous low k dielectric material |
| KR20080074494A (en) * | 2007-02-09 | 2008-08-13 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105336664A (en) * | 2014-06-13 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Etching method |
| CN105336664B (en) * | 2014-06-13 | 2018-06-01 | 中芯国际集成电路制造(上海)有限公司 | Lithographic method |
| CN108493104A (en) * | 2018-04-10 | 2018-09-04 | 睿力集成电路有限公司 | Method for etching plasma and plasma etching post-processing approach |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103426813B (en) | 2016-02-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8686535B2 (en) | Trench isolation implantation | |
| US8975729B2 (en) | Integrating through substrate vias into middle-of-line layers of integrated circuits | |
| US20100072569A1 (en) | Method of forming an isolation layer, method of manufacturing a semiconductor device using the same, and semiconductor device having an isolation layer | |
| CN102569164A (en) | Semiconductor integrated circuit device | |
| US8669152B2 (en) | Methods of manufacturing semiconductor devices | |
| KR20120026313A (en) | Non-volatile memory device and method of fabricating the same | |
| CN103456606A (en) | Method for forming hard mask layer | |
| CN102386126B (en) | Method for manufacturing structure of semiconductor device for forming structure of dual damascene | |
| US20070210339A1 (en) | Shared contact structures for integrated circuits | |
| CN106298673B (en) | A kind of semiconductor devices and its manufacturing method | |
| CN103426813B (en) | For carrying out the method etching reprocessing to low dielectric constant material layer | |
| CN102487087A (en) | Thin-film transistor applied to three-dimensional on-chip integration system and manufacturing method of thin film transistor | |
| US7972941B2 (en) | Method of manufacturing a semiconductor device | |
| US20090278227A1 (en) | Isolation trench structure | |
| KR20020011476A (en) | The method of fabricating metal-line improved rc delay in semiconductor device | |
| CN105355599A (en) | Semiconductor memory device and preparation method thereof, and electronic device | |
| CN102148190A (en) | Method for manufacturing semiconductor interconnection structure | |
| CN102623306A (en) | Metal-multilayer insulator-metal capacitor, manufacture method for same and integrated circuit thereof | |
| CN103531531B (en) | A kind of method being used for producing the semiconductor devices | |
| CN103165436B (en) | Make the method for semiconductor device | |
| JP2013197288A (en) | Semiconductor device and manufacturing method therefore | |
| CN102347206B (en) | Method for manufacturing semiconductor device | |
| CN102386089B (en) | Method for preparing semiconductor device structure | |
| US11081478B2 (en) | Interconnect structure having a fluorocarbon layer | |
| CN101504916A (en) | Production method for transistor, method for forming channel stop and semi-conductor element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |