CN103354949B - 引脚连接装置 - Google Patents

引脚连接装置 Download PDF

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Publication number
CN103354949B
CN103354949B CN201180067393.2A CN201180067393A CN103354949B CN 103354949 B CN103354949 B CN 103354949B CN 201180067393 A CN201180067393 A CN 201180067393A CN 103354949 B CN103354949 B CN 103354949B
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Prior art keywords
hardware
microelectronics packaging
substrate
face
dielectric layer
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CN103354949A (zh
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贝勒卡西姆·哈巴
伊利亚斯·默罕默德
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Abstract

微电子封装(10)包括基板(20)，该基板(20)具有第一区域(26)和第二区域(28)，第一表面(22)和远离第一表面(22)的第二表面(24)。至少一个微电子元件(60)设置在第一表面(22)上的第一区域(26)之上。第一导电元件(30)暴露在基板(20)的第一表面(22)和第二表面(24)之一的第二区域(26)之内，并且至少一些第一导电元件(30)与至少一个微电子元件(60)形成电连接。基本上刚性的金属元件(40)设置在第一导电元件(30)之上，并具有远离第一导电元件(30)的端面(42)。结合金属(41)接合在金属元件(40)和第一导电元件(30)之间，模制介电层(50)覆盖在基板(20)的至少第二区域(28)上并具有远离基板的表面(52)。该金属元件(40)的端面(42)的至少一部分暴露于模制介电层(50)的表面。

Description

引脚连接装置
相关申请的交叉引用
本申请要求申请序列号为12/966225，申请日为2010年12月13日，名称为“引脚连接装置”的专利申请的申请日之利益，其公开的内容以引用的方式并入本文。
技术领域
本发明涉及微电子封装技术领域，特别是涉及微电子封装、 微电子组件、制造微电子封装或组件的方法以及包含微电子封装或组件的系统。
背景技术
典型的微电子器件，如半导体芯片，需要许多与其他电子元器件进行输入和输出的电连接接点。半导体芯片或者其他类似设备的输入输出触点通常以栅格形式覆盖在器件的表面（也就是通常所说的“面阵”），或者以平行并且毗邻器件正面的每一个边缘的方式呈长列形分布，或者设置在正面的中心位置。典型的器件如芯片，必须被物理地安装在类似印刷电路板的基板上，器件的触点必须与电路板上的导电特征形成电连接。
半导体芯片一般设置在封装内，在加工过程及在把芯片安装在如电路板或其他电路面板的外部基板上的过程中，封装方便对芯片进行处理。例如，许多半导体芯片设置在适于表面安装的封装内。为了各种应用，已推出了大量的这种普通类型的封装。最常见的，这种封装包括一般称为“芯片载体”的介电元件，介电元件具有如在电介质上电镀或蚀刻金属结构而形成的端子。这些端子通常与芯片自身的触点，通过如沿芯片载体自身延伸的薄迹线，及在芯片触点与端子或迹线之间延伸的精细引脚或引线等导电特征而连接。在表面安装操作中，封装放置在电路板上，使得封装上的每个端子与电路板上相对应的接触垫对齐。在端子与接触垫之间设置焊料或其他结合材料。通过加热组件使得焊料熔融或“回流”或以其他方式使结合材料起作用，封装可永久地结合定位。
许多封装包括附接至封装的端子上的以焊料球形式的焊料块，焊料块通常具有约0.1毫米与约0.8毫米（5密耳及30密耳）的直径。具有从其底面突出的焊料球的阵列的封装，一般称为球格栅阵列封装或“BGA”封装。称为格栅阵列封装(land grid array)或“LGA”封装的其他封装，通过焊料形成的薄层或面而固定至基板上。这种类型的封装可非常紧凑。一般称为“芯片级封装”的某些封装，占据电路板的面积等于或仅稍大于纳入封装内的器件的面积。这对降低组件的总体尺寸，及在基板上的各器件之间允许使用较短的互连来说是有利的，互连反过来限定器件间的信号延迟时间，因此便于组件在高速下工作。
多个被封装的半导体芯片通常以堆叠的方式布置，例如，一个封装被安装在一个电路板上，另一个封装能够被安装在第一封装的上部。这些布置能够允许若干不同的芯片被堆叠在电路板的单一区域内，这样，由于各个封装之间的互连距离短，又进一步提高了组件的运行速度。通常，这一互连距离仅比芯片自身的厚度大一点点。为了实现堆叠在一起的芯片封装之间的互连，有必要在每一封装（除了最顶部的封装之外）的两侧设置机械和电子的连接结构。例如，可以在安装芯片的基板的两侧设置接触垫和连接盘以实现上述目的，通过导电通路或类似结构，接触垫可以穿过基板被连接。焊料球或类似结构也可以用来桥接较下层基板顶部的触点和较上层基板底部的触点。为了连接触点，焊料球必须比芯片的高度要高。关于堆叠芯片的布置以及互连结构的实施例已经在公开号为2010/0232129的美国专利申请公开说明书（简称“'129号公开说明书”）中公开，其公开的内容以引用的方式全部并入本文。
以细长柱或者引脚形式存在的微触点元件可以用于将微电子封装连接在电路板上并且用于微电子封装中的其他连接。在某些情况下，微触点元件也可以以通过蚀刻包括一层或多层金属层的金属结构而形成。蚀刻工艺限制了微触点的尺寸。传统的蚀刻工艺通常无法形成具有大的高度对最大宽度的比值（本文称为“高宽比”）的微触点。现有的技术也很难或不可能制作出既具有可观的高度，又使相邻微触点之间具有极小间距或间隙的微触点阵列。此外，传统蚀刻工艺形成的微触点结构也受到限制。
尽管在微电子封装的制造和测试方面，本领域已取得上述进展，但仍有待于作出进一步的改善。
发明内容
本发明提供了一种微电子封装。该微电子封装包括基板，该基板具有第一区域和第二区域，且具有第一表面和远离第一表面的第二表面。至少一个微电子元件设置在第一表面上的第一区域之上。第一导电元件暴露在基板的第一表面和第二表面之一的第二区域之内，并且至少一些第一导电元件与至少一个微电子元件形成电连接。复数个基本上刚性的金属元件设置在第一导电元件之上，并具有远离第一导电元件的端面。结合金属使金属元件与第一导电元件接合，模制介电层覆盖在基板的至少第二区域上并具有远离基板的表面。该金属元件端面至少部分地暴露于模制介电层的表面。
至少一些第一导电元件暴露在基板第二表面的第二区域内。而且，模制介电层覆盖在基板的至少第二表面上。进一步的或可选择的，第一导电元件暴露在基板第一表面的第二区域内，并且模制介电层覆盖在基板的至少第一表面上。本发明提供的微电子封装还包括第二导电元件，第二导电元件暴露在基板的第二表面上并且与至少一些第一导电元件电连接。在其他实施例中，模制介电层进一步覆盖在微电子元件之上。在进一步的实施例中，微电子封装还可能包括一并非事先成型好、用于替代模制介电层的密封层。
在一个实施例中，在复数个金属元件中，第一金属元件适于承载第一信号电位，第二金属元件适于同步承载第二电位。第二电位可以与第一信号电位不同。
在另外的实施例中，模制介电层可以具有不同的区域，各个区域的主表面相对基板具有不同的高度。这些区域可以与基板的第一和第二区域相对应。进一步的，金属元件的端面可以与模制介电层的表面共面；也可以利用在模制介电层上开通孔的方式使端面暴露，从而使金属元件的端面高于或低于模制介电层的表面。更进一步的，在模制介电层的表面上还可以设置具有导电垫的再分配层。
在另外的实施例中，微电子封装的金属元件从端面处的较大宽度在朝着第一导电元件延伸的方向上越来越小。金属元件还具有以一轴线为中心的旋转曲面，该旋转曲面包括一圆锥形表面或圆柱形表面。微电子封装中的金属元件的高度贯穿了模制介电层厚度的至少60%。可选择的，结合金属的高度也可以贯穿模制介电层厚度的至少60%。
本发明提供的各种微电子封装实施例可被集成在一微电子组件中，该微电子组件还包括第二微电子封装。该第二微电子封装包括一外表面和一微电子元件，该外表面上设有复数个暴露在外的连接元件，该微电子元件与这些连接元件电连接。第二微电子封装外表面的至少一部分覆盖在模制介电层的至少一部分的表面上，第二微电子封装的连接元件与第一微电子封装的导电凸起的端面形成机械连接和电连接。
进一步，本发明还提供了一种制造微电子封装的方法，包括提供一个微电子组件，该微电子组件具有第一基板。第一基板包括第一表面、载体和复数个刚性的金属元件，该第一表面上设置有复数个暴露的导电元件，该载体具有与基板的第一表面间隔一定距离的第二表面，该金属元件从载体延伸出来并与导电元件连接。该方法进一步包括从微电子组件中移除载体的步骤，从而暴露出金属元件远离第一导电垫的接触表面。在一实施例中，移除载体的步骤包括蚀刻、研磨和剥除载体中的至少一种。在另一实施例中，在移除载体之前，介电材料被注入到第一和第二表面之间以及导电凸起的周边，以便形成模制介电层。
微电子子组件由第一子组件和第二子组件组成，第一子组件包括第一基板和导电元件，第二子组件包括载体和金属元件。在该实施例中，金属元件具有远离第二表面的第一表面，在金属元件的第一表面与第二子组件的导电元件相连接之前，该第一表面是暴露在外的。通过形成附接至导电凸起的第一表面和对应的导电元件的复数个结合金属块，以使结合金属的至少一部分处于第一表面与导电元件之间的方式，将所述金属元件的至少第一表面附接在所述第二组件的导电垫上。
在一实施例中，微电子组件还包括能够附接在基板上并且与至少一些的导电元件电连接的微电子元件。该微电子元件在移除载体之前或之后能够附着在第一基板上。
进一步的，第一基板的第一表面包括第一和第二区域，导电元件暴露在第一表面的第一区域内，微电子元件连接在第一表面的第二区域内。一模制介电层覆盖在第一表面的第一区域和第二区域以及该微电子元件的至少一部分上。该模制介电层包括一外表面，金属元件的接触表面暴露在模制介电层的外表面上。模制介电层被成型成具有覆盖在不同区域上的第一介电层部分和第二介电层部分。覆盖在第一区域和第二区域之上的模制介电层的各个部分被成型成具有各自不同的高度。
进一步的，第一子组件的形成包括如下步骤：将刚性金属层连接到第二表面；沿刚性金属层的选定部分添附结合金属块，使第一表面被限定在结合金属块形成的区域内；去除刚性金属层在选定部分之外的部分。在刚性金属层上覆盖有掩模层，掩模层具有复数个通孔以便暴露金属层的选定部分。添附结合金属块的步骤包括从上述通孔中添附结合金属块的步骤。在一个实施例中，掩模层充当了至少一部分密封剂层的作用，该密封剂层是在转移导电凸起步骤之后形成的。
上述任意一实施例都可以被使用在一个包括微电子组件以及与该微电子组件电连接的一个或多个其他电子元器件的系统中。
附图说明
图1显示了根据本发明一个实施例的一个微电子组件。
图2显示了在一个堆叠关系中，图1中的微电子组件与一个第二微电子组件连接时的情况。
图3显示了根据替代实施例的微电子组件的变例。
图4显示了根据替代实施例的微电子组件的另一变例。
图5显示了在一个堆叠关系中，根据替代实施例的另一变例的微电子组件附接在另一个微电子组件上的情况。
图6显示了根据替代实施例的微电子组件的另一变例。
图7显示了根据替代实施例的微电子组件的另一变例。
图8显示了在一个堆叠关系中，根据替代实施例的另一变例的微电子组件附接在另一个微电子上的情况。
图9显示了根据替代实施例的微电子组件的另一变例。
图10-13显示了用于形成如图1所示微电子组件的方法的连续步骤。
图14-16显示了用于形成如图7所示微电子组件的方法的连续步骤。
图17-22显示了用于形成如图7所示微电子组件的替代方法的连续步骤。
图23-25显示了用于形成如图7所示微电子组件的另一替代方法的连续步骤。
图26显示了包含根据图1所示实施例的微电子组件的系统。
具体实施方式
参照附图，图1显示了根据本发明一个实施例的微电子组件，其中类似的标示代表类似的结构。图1显示的实施例是一个封装微电子元件形式的微电子组件，例如用于计算机或其他电子应用中的半导体芯片组件。
图1中的微电子组件10包括一个基板20，该基板20具有第一表面22和第二表面24。该基板通常为由介电晶圆材料制成的基本平直薄片形式。该基板优选为由硅或半导体芯片领域常用的适于此类应用的其他介电材料制成。第一表面22和第二表面24最好为大致相互平行并间隔一定距离，该间隔的距离垂直于表面22和表面24并限定了基板20的厚度。基板20的厚度可以处于本领域普通技术人员在阅读了本说明书之后所能理解的任何可被接受的范围。在一个实施例中，第一表面22和第二表面24的间距在25μm至500μm之间。为了表述方便，第一表面22可以被描述成位于第二表面24的上方。这类描述以及任何其他关于元件垂直或水平相对位置的描述，只是为了便于说明附图中的元件的相应位置，而不是限制性的。
在一个较优的实施例中，基板20可视为被划分成第一区域26和第二区域28。第一区域26处于在第二区域28内，并包括基板20的中心部分并由此向外延伸。第二区域28基本上将第一区域26包围并由此向外延伸至基板20的外边缘。更好地，基板本身并没有特定的特征被物理地划分成两个区域，本文只是为了方便说明施加于其上的处理方式或者其中包含的特征，而划分出不同的区域。
一个微电子元件60附接在位于基板20第一区域26内的第一表面22上。微电子元件60可以是半导体芯片或类似器件。在一个实施例中，微电子元件60可以以一种称为常规的或者“面朝上”的方式附接至第一表面22上。在本实施例中，微电子元件60通过引线（未显示）与暴露在第一表面22上的导电元件30进行电连接，这种连接方式可以通过将引线与基板20中的迹线（未显示）或其他导电特征进行连接来实现，同样，基板20中的导电迹线或其他导电结构也可以与导电元件30电连接。
一组第一导电元件30暴露在基板20的第一表面22上。在本说明书中，当提到一个元件“暴露”在另外一个诸如表面或类似物的元件之上时，“暴露”指的是，当一个理论点从介电结构的外部沿着垂直于介电结构表面的方向朝介电结构表面移动时，导电结构能够接触到这个理论点。因此，一个端子或者其他导电结构暴露在介电结构的表面，意味着该端子或其他导电结构可以从该介电结构表面突出，也可以与该介电结构表面平齐，或者凹进该介电结构表面并通过介电结构上的通孔或凹槽暴露出来。导电元件30可以是平的、薄的元件，形成有暴露在基板20第一表面22上的第一面32。在一个实施例中，导电元件30可以大致呈圆形垫的形式，并且相互之间可以电互连或者通过迹线（未显示）与微电子元件60电互连。导电元件30可至少形成在基板20的第二区域28内。另外，在某些实施例中，导电元件30也可以形成在第一区域26内。这样的布置在被称为“倒装芯片”的配置中，将微电子元件60连接到基板20上时尤其有用，此时，微电子元件60的触点可以通过微电子元件60下方的焊料凸点（未显示）或者类似结构在第一区域26内与导电元件30连接。
较好的，导电元件30由铜、金、镍等固体金属材料制成，也可以由其他公知的可以用于本领域的材料，包括含铜、金、镍或其组合中的一种或多种的各种合金制成。
至少一些导电元件30可以与对应的第二导电元件36互连，例如暴露在基板20的第二表面24上的导电垫。这种互连可以通过设置在基板20中的通路34实现，通路34可以通过在基板20中内衬或填充导电金属形成，该导电金属可以是与导电元件30和36相同的材料。可选择的，导电元件36可以进一步地通过基板20上的迹线互连。
组件10也包括附接在至少一些导电元件30上的复数个基本刚性的金属元件40。金属元件40可以附接在处于基板20第一区域26内的导电元件30上。金属元件40远离导电元件30并向端面42延伸，端面42分隔设置在导电元件30上方，或远离导电元件30。在另外的实施例中，金属元件40可以附接在暴露于第二表面24的导电元件36上。在该实施例中，金属元件40延伸至位于导电元件36下方的端面42。
金属元件40通过结合金属块41与导电元件30附接。结合金属块41由任意导电材料制成，该导电材料可以是公知的用于附接两个刚性或固体金属元件的材料，并且该导电材料具有相对较低的熔点（即300°C以下），以防止在熔化该导电材料用于上述连接时，将相邻的固体金属部分或微电子组件10的任何其他元器件也熔化了。结合金属块41可以包括易熔金属，例如焊料、锡或铟，或者其他熔点低于300°C的金属或合金。金属元件40由熔点相对较高的材料制成，以便它能够承受结合金属块41的熔点温度。另外，金属元件40应当由公知的具有可靠导电性能的材料制成，例如铜、金、镍或者包含它们的各种混合物或包含其他金属的合金。
结合金属块41附接在相应的导电元件30的第一面32上。金属元件40包括一个远离端面42的基座44以及一个在基座44和端面42之间延伸的边缘表面46。金属元件40的基座44与结合金属块41附接。基座44可与第一面32间隔开，以便结合金属块41能够处于基座44和第一面32之间。另外，一些结合金属块41可以沿着金属元件40的边缘表面46的一部分向上延伸。这样，结合金属块41可形成为相应的导电元件30第一面32上的焊料块，且金属元件40部分地保持在其内。在另外的实施例中，结合金属块41可以沿着几乎整个边缘表面46向上延伸。进一步的，一些结合金属块41也可以沿着金属元件40的一部分向上吸（wick）。
金属元件40可形成为端面42应当至少与基座44一样宽。每一基座44和端面42的宽度是指从垂直于金属元件40纵轴方向上进行测量时的尺寸，该方向也可以表述为平行于面32或者第一表面22的方向。在一个实施例中，金属元件40为一个旋转体，使得基座44和端面42呈大致圆形的形状，而边缘表面46为在端面42和基座44之间延伸的旋转曲面。在该实施例中，所谓基座44和端面42的宽度实际上就是它们的直径。在一个实施例中，金属元件40为截头圆锥体（在圆锥体的底面和顶点之间截断，使之具有两个平行的平面）。在其他实施例中，金属元件40也可以是双曲线体，或者是旋转轴在抛物线顶点之外的旋转抛物面体。在上述各实施例中，端面44均比基座42宽。金属元件40和导电凸起40可供选择的完整的形状和结构将在下文中进一步考虑和说明。
如图1所示的实施例，金属元件40的高度占据了封装10的高度48的大部分。在该实施例中，金属元件40的高度至少为封装高度48的60%。在该实施例的变例中，金属元件40的高度可以占到封装高度48的80%至90%。金属元件40所占的高度比例并不考虑结合金属块41沿边缘表面46延伸的量。
微电子组件10还包括密封剂层50。如图1所示的实施例，密封剂层50形成在基板20第一表面22的特定部分上 ，该特定部分没有被微电子元件60或导电元件30所覆盖或者占据；同样的，密封剂层50形成在导电元件30的特定部分上，包括导电元件30的面32，该特定部分没有被金属元件40或结合金属块41覆盖。密封剂层50也可以基本上覆盖微电子元件60，结合金属块41以及金属元件40的边缘表面46。金属元件40的端面42暴露在由密封剂层50限定的主表面52上。换句话说，除了端面42之外，密封剂层50可以覆盖微电子组件10的第一表面22及其之上的所有部分。
密封剂层50为保护微电子组件10内的其他元器件，尤其是金属元件40和结合金属块41提供了更坚固的结构，使它们在测试、运输或者安装到其他微电子结构中时免受损坏。密封剂层50可以由具有绝缘性能的介电材料制成，这类介电材料在申请公布号为2010/0232129的美国专利申请中被披露，其内容以全文引用的方式并入本文。
由于具有暴露在第二表面24上的第二导电元件36以及金属元件40的端面42 ，图1所示实施例的结构可以从微电子组件10下方或从上方与其他电子元器件连接。这就允许微电子组件10以直立或倒置的方式与一个半导体芯片或者其他微电子组件连接，也进一步允许微电子组件10从顶部或底部进行测试。如图2所示，微电子组件10可以与另一微电子组件90进行堆叠，微电子组件90具有自身的接触垫92和微电子元件94。此种堆叠布置还可以包括其他组件，并最终被连接到电子设备中的印刷电路板（PCB）等类似装置上。在这种堆叠布置中，金属元件40和导电元件30及32可以携带多种电信号，在单个堆叠中，每种电信号具有不同的信号电位以允许不同的信号被不同的微电子元件处理，例如微电子元件60或微电子元件92。在这样一种堆叠中，焊料块94例如通过电子和机械地使端面42附接于导电元件9，而实现微电子组件10和90之间的互连。
图1和图2的实施例显示的密封剂层50的主表面52与金属元件的端面42处于同一平面，从而形成一个基本连续的表面。密封剂层50的主表面52与端面42之间也可以存在不同的位置关系。如图3所示，该实施例中金属元件140的高度比密封剂层150的高度要低，从而导致端面142处于密封剂层150之内或者位于主表面152之下。在该实施例中，端面142通过密封剂层150上的孔154暴露于主表面152。孔154的横截面尺寸等于或略小于端面142的尺寸。孔154应设计得足够大以便保证与端面142的可靠连接。
图4显示了另一实施例，金属元件240的高度大于密封剂层250的高度。在该实施例中，端面242位于主表面252上方或主表面252之外。在该实施例中，在密封剂层250对应于导电凸起240的部分设置有复数个平台部256。平台部256沿着边缘表面246延伸至复数个第二表面258，第二表面258大致与端面242平齐。
在另外的实施例中，密封剂层350可以被设计成具有多个不同高度的部分。如图5所示，密封剂层350具有第一部分350a和第二部分350b，第一部分350a大致与基板320的第一区域326对应，第二部分350b大致与基板320的第二区域328对应。在该实施例中，第一部分350a的主表面352a高于第二部分350b的主表面352b，另外，金属元件340的端面342与主表面352b平齐并且处于主表面352a的下方。在另外的实施例中，主表面352a和主表面352b之间的关系可以反转，以致于主表面352b位于主表面352a的上方，优选地，端面342仍然大致与主表面352b平齐。
如图5所示，微电子组件310与微电子组件390之间形成堆叠关系，复数个焊料块396将端面342与导电元件392连接。在这种布置中，焊料块396足够高以便补偿较高的第一区域350a。
如上文所述，图1中的金属元件40还可以具有其他形式。一个实施例如图6所示，金属元件440进一步分为基部440a和端部440b。基部440a包括基座444和从基座444朝端面442延伸的一部分边缘表面446。同样的，端部440b包括端面442和从端面442向基座444延伸的一部分边缘表面446。金属元件440中，边缘表面446处于基部440a的部分向外倾斜以面朝第一表面422。边缘表面446处于端部440b的部分向内倾斜以背对第一表面422，使得边缘表面446的斜率在基部440a和端部440b的边界处突然改变。在一个实施例中，上述边界形成的边缘表面446的脊部447将基部440a和端部440b区分开来。脊部447或者其他类似形状突变可以位于基座444和端面442之间的任意位置，包括形成在靠近中部的位置，或者形成在靠近基座444或者靠近端面442的位置。上述金属元件440中，这种类似脊部447的锚定特征能够帮助金属元件440固定在密封剂层450中。具有锚定特征的导电凸起的相关实施例已经在申请公布号为2008/0003402的美国专利申请中被公开，其公开的内容以全文引用的方式并入本文；还有一些实施例已经在申请序列号为12/838974的美国专利申请中被公开，其公开的内容以全文引用的方式并入本文。
图7显示了另一微电子组件510的实施例，其中，结合金属块541贯穿密封剂层550高度548的大部分。在该实施例中，结合金属块541优选为至少贯穿高度548的60%。在一实施例中，结合金属块541甚至贯穿了高度548的约80%至90%。结合金属块541贯穿的部分是指完全处于金属元件540的基座544与导电元件430的面432之间的部分。进一步的，在该实施例中，金属元件540为大致位于结合金属块541顶上的基本圆形的接触垫。
图8和图9显示了一个具有上部再分配层的微电子子组件的另一实施例。图8中的再分配层670具有一个第二基板672，第二基板672被安装在密封剂层650的主表面652上。再分配层670进一步包括复数个暴露在基板672表面上的接触垫674。接触垫674优选地通过形成在基板672中一系列的迹线（未显示）互连，并可以通过形成在基板672中的导电通路676与端面642互连。
图9中的再分配层770的结构与图8中再分配层的结构类似，只是直接形成在密封剂层750的主表面752上。也就是说，形成迹线以将端面742与形成在主表面752上的接触垫774相连。
制造例如图1中显示的微电子组件的方法如图10-13所示，在该方法中，子组件12具有载体80，载体80具有第一表面82。固体金属元件40形成在载体80的第一表面82上。金属元件40的端面42可拆除地附接在表面82上，使得基座44远离表面82。金属元件40可以通过一些公知的方法形成在载体80上，这些公知的方法包括在理想的位置为形成金属元件40而镀金属层的方法。可选择的，也可以通过在载体80上沉积金属层并对金属元件40所在位置以外的区域进行选择性地蚀刻，来形成金属元件40。这种蚀刻方法可以是采用公知的化学成分、激光法或其他公知的方法。
图11显示了本方法的一个后续步骤，其中，子组件12与一个第二子组件14对齐，第二子组件14包括例如图1所示的已经制造好的微电子组件的基板20和导电元件30。这种对齐方式应当保证金属元件40基本与对应的导电元件30对齐。金属元件40的基座44可以与接触垫30相隔一定间距。如图12所示，结合金属块41形成在基座44和对应的接触垫30之间。结合金属块41可以被首先添附在导电元件30上、或者被首先添附在金属元件40上，或者同时在两者上添附一部分。这可以在金属元件40与导电元件30对齐之前或之后进行。
如图12所示，在图11所示步骤形成组件10’之后，载体80被从组件10’上移除。该移除步骤可以通过任何公知的技术完成，包括剥除、研磨或蚀刻。如图12所示，一旦载体80被去除，金属元件40的端面42就在远离基板20的表面22处暴露。
图13显示了微电子元件60连接在基板20上的步骤。完成该步骤可以通过任何描述图1所示实施例时提到的连接方式来完成，包括正面朝上或倒装芯片结合的方式。也可以通过在图11显示的步骤之前将微电子元件60连接在基板20上形成微电子组件10’’结构。
如图1-5所示，微电子组件10通过施加密封剂层来实现，例如可以通过包括注塑成型在内的公知方法形成。适用于这些实施例的、本领域普通技术人员在阅读本说明书时能够理解的注塑成型形成密封剂层的方法，已经在申请公布号为2010/0232129的美国专利申请（简称'129号专利文献）中公开，其公开的内容以全文引用的方式并入本文。密封剂层通常通过模制方法固定在组件10’’上，首先将该组件放置在一个模具中，该模具的尺寸不仅可以容纳组件10’’并且还具有一个与待成型密封剂层50形状对应的空腔（与'129号专利文献的附图10显示的相同）。介电材料通过一个端口被注射到该空腔中并且充满整个模腔，使得基板20的第一表面22、金属元件40的边缘表面46，以及结合金属块41或者导电元件30的所有暴露部分都被介电材料覆盖，该填充在空腔中的介电材料就形成了密封剂层50所需要的形状。另外，根据需要，密封剂层50也可以覆盖住图1中所示的微电子元件60。
用于形成密封剂层50的模具（如'129号专利文献的附图10所示的模具420）可以遮挡住端面42以便该端面可以暴露在密封剂层50的表面。'129号专利文献的附图10所示的模具420包括一个凸起的中心部分，该中心部分用于形成图5所示的密封剂层，该密封剂层具有处于基板20第一区域26上方的较高的主表面352a。在模具的另一实施例中，模具可以包括一个基本连续的主表面，用于形成图1所示的密封剂层50。另外，模具的上表面处于金属元件所在区域之上的部分可以包括复数个缺口，用于形成图4所示的封装类型，该封装类型在金属元件240所在区域具有凸起的平台部分256。
如图3所示的密封剂层150可以通过在模具中设置凸台形成，该凸台的位置与孔154的所需位置相对应，延伸并覆盖住金属元件140的端面142。可选择的，密封剂层150可以通过具有与表面152对应的基本平直表面的模具形成。在这种方法中，覆盖在金属元件140端面142上的密封剂材料层在后续步骤中可以用化学方法或机械方法被移除，例如通过激光蚀刻。同样的，图1、图6或图7中所示的密封剂层结构也可以通过先在金属元件40、440和540的端面42、442和552上覆盖密封剂层，然后通过蚀刻到预定深度从而暴露出端面42、442和552的方法形成。图4和图5所示的密封剂层也可以用同样的方法形成，包括向下蚀刻密封剂层250形成主表面252并保留平台凸起256，如图4所示；或者向下蚀刻密封剂层350形成较低的主表面352b，如图5所示。
在另外的实施例中，密封剂层50可以分步形成。例如，第一步，密封剂层50基本覆盖在第一表面22位于基板20第二区域28范围内的部分上，并且沿着边缘表面46延伸并覆盖住结合金属块41和导电元件30的其他未覆盖部分。第二步，密封剂层50的第二部分形成在第一表面22位于基板20第一区域26范围内的部分上。例如，该第二部分可以覆盖微电子元件60，而该微电子元件60可以在上述密封剂层50的第一模制步骤之前或之后连接在基板20上。
图6所示的具有锚定特征的导电凸起340可以通过一个附加步骤形成。该步骤包括从端面42蚀刻例如组件10’’中的如图12所示的导电凸起40的步骤。通过在端面42上施加掩模层，并蚀刻掉端面42以下的金属元件40的一部分，可以形成图6所示的固体金属部分340b的形状。而且，形成导电凸起的方法已经在申请公布号为2008/003402和申请序列号为12/838,974的美国专利文献中披露，其公开的内容以全文引用的方式并入本文。
图14-16显示了采用图10-13所示的方法形成图7所示的微电子组件410的方法步骤。在该方法中，金属元件440形成在载体480的第一表面482上，该载体480与金属元件440为可移除的连接，结合金属块441以焊料凸块441’的形式连接在金属元件440上。如图14所示，子组件412与第一表面422上暴露有导电元件430的基板420对齐，使得焊料凸块441’与对应的导电元件430对齐，并使载体480的第一表面482面对基板420的第一表面422。
如图15所示，通过加热焊料凸块441’而使焊料处于回流状态，金属元件440可以附接在导电元件430上。一旦处于回流状态，在焊料的表面张力以及沿导电元件430的毛细作用下，焊料凸块可以形成如图15所示的大致圆柱体形状的结合金属块441。然后，采用对图12进行说明时的方法，移除载体480，接着，采用对图12和图13进行说明时的方法进行进一步的加工，从而完成微电子组件410”的制作。
图17-22显示了制作图7所示的微电子组件410的另外的或可选的一个方法。在该方法中，基本上刚性的金属层484形成在载体480的第一表面482上。焊料掩模层486形成在刚性金属层484之上。在刚性金属层484的部分位置的上方形成有孔488，用于在后续步骤中为形成金属元件440预留位置。孔484可以在形成焊料掩模层486的过程中形成，也可以在形成焊料掩模层486之后形成图案。焊料凸块441’填充在孔488中，孔488为焊料凸块441’的至少一部分能够形成大致圆柱形提供了类似于模腔的作用。
如图19所示，子组件412在基板420的上方与基板420对齐，从而使焊料凸块441’能够与暴露在第一表面422上的对应的导电元件430对齐。在可选择的实施例中，焊料掩模层486可以通过化学方法或机械方法被移除，而整体金属层484可以通过如激光蚀刻或类似方法蚀刻形成金属元件440，从而形成与图14所示的子组件412类似的一个子组件，只是该子组件不具有通过焊料掩模层486的孔488形成的大致圆柱体部分。
如图20所示，焊料凸块441’通过加热呈回流状态，该焊料凸块441’形成结合金属块441并将金属元件440和导电元件430连接在一起。载体480可以被有选择的移除，例如通过机械加工或蚀刻，保留载体480位于整体金属层484上方的掩模部分480’。如图21所示，然后通过蚀刻工序将整体金属层484分割成间隔的金属元件440，之后移除掩模部分480’，使端面442暴露于外。接着，如图22所示，移除焊料掩模层486，或者在相应的位置保留焊料掩模层486以形成部分的密封剂层450。最后，通过前述的选定步骤完成组件410’’的加工。
图23-25显示了制造如图7所示的微电子组件410的另外的方法。在该方法中，焊料凸块441’形成在导电部分430上，而金属元件440或者以单个元件（图23）的形式或者以整体金属层484（图25）的形式形成在载体480上。焊料凸块441’被加热回流形成结合金属块441。如图25所示，具有孔488的焊料掩模层486被设置在整体金属层484上，这些孔488充当模腔的作用以便使结合金属部分440a形成大致圆柱体的形状。图25所示的结构，经过焊料块的回流步骤之后，基本与图20所示的结构类似并可以根据相关的后续步骤完成整个结构的加工。图24所示的载体480被移除后形成与图16所示类似的结构，并且根据相关的后续步骤完成整个结构的加工。
上述结构可以被各式的微电子系统所采用。例如，根据本发明的一个实施例，系统513包括上文描述过的微电子组件510以及其他电子元器件514和515。该实施例中，元器件514为一个半导体芯片而元器件515为一个显示屏幕，然而任何其他元器件也可以被使用。当然，为了清楚说明的目的，在图26中只描述了两个额外的元器件，但该系统也可以包括任何数量的这类元器件。例如，上述微电子组件510可以是一个如图1所示的微电子组件，或者是一个如图2所示包含复数个微电子组件的结构。组件510还可以进一步包括图3-25中任何一个实施例。在进一步的变例中，还可以具有多种变化形式，且可以应用任意数量的这种结构。
微电子组件510和元器件514和515被安装在一个如图中虚线所示的共同的壳体516中， 并且根据需要形成相互之间的电连接以形成所需要的电路。在该实施例中，系统包括一个电路板517，譬如一个柔性印刷电路板，该电路板包括大量的导体518，尽管图26中仅显示了一个，这些导体518使各元器件之间形成电互连，当然，这仅仅是一个示例，任何适于进行电连接的结构都可以被使用。
壳体516可以是任何适于该应用的便携式壳体，例如，在一个移动电话或者个人数字助理中，屏幕515暴露在该壳体的表面。微电子组件510包括光敏元件（如成像芯片）、镜头519或者其他可将光引入该结构的光学器件。同样的，图26所示的简化系统只是示例性的，其他系统，包括通常被视为固定设备，例如桌面电脑、路由器及其类似设备，也可以采用上述结构。
尽管本发明参照特定实施例进行描述，可以理解的是，这些实施例只是说明本发明的原理和应用。因此，应理解为，在不偏离由附加的权利要求书所限定的本发明实质和范围的情况下，说明的实施例可做出许多修改及可设计出其他布置。

Claims (22)

1.微电子封装，包括：
基板，具有第一区域和第二区域，所述基板具有第一表面和远离第一表面的第二表面；
至少一个微电子元件，设置在第一表面上的第一区域上；
第一导电元件，暴露在基板的第一表面和第二表面之一的第二区域之内，并且至少一些第一导电元件与至少一个微电子元件形成电连接；
刚性的金属元件，设置在第一导电元件之上，并具有远离第一导电元件的端面；
结合金属，使金属元件与第一导电元件接合；及
模制介电层，覆盖在基板的至少第二区域上并具有远离基板的表面；其中金属元件端面至少部分地暴露于模制介电层的所述表面；
其中金属元件中的第一金属元件适于承载第一信号电位，第二金属元件适于同步承载第二电位，所述第二电位不同于所述第一信号电位;
其中金属元件从端面处的较大宽度在朝着第一导电元件延伸的方向上越来越小。
2.根据权利要求1所述的微电子封装，其中至少一些第一导电元件暴露在基板的第二表面的第二区域内，并且模制介电层覆盖在至少第二表面上。
3.根据权利要求1所述的微电子封装，其中第一导电元件暴露在基板第一表面的第二区域内，并且模制介电层覆盖在至少第一表面上。
4.根据权利要求3所述的微电子封装，其中还包括第二导电元件，所述第二导电元件暴露在基板的第二表面上并且与至少一些第一导电元件电连接。
5.根据权利要求1所述的微电子封装，其中模制介电层覆盖在所述微电子元件上。
6.根据权利要求1所述的微电子封装，其中模制介电层具有高出第一区域的第一高度和高出第二区域的第二高度，所述第一高度不同于所述第二高度。
7.根据权利要求6所述的微电子封装，其中所述第一高度大于所述第二高度。
8.根据权利要求1所述的微电子封装，其中所述金属元件的端面与所述模制介电层的所述表面处于同一平面。
9.根据权利要求8所述的微电子封装，其中还包括暴露在模制介电层的所述表面上的导电垫，所述导电垫与所述金属元件电连接。
10.根据权利要求1所述的微电子封装，其中所述金属元件的端面位于基板第一表面与模制介电层的表面之间，并且，其中模制介电层中设置有从外表面延伸的孔，以便暴露所述金属元件的端面。
11.根据权利要求1所述的微电子封装，其中模制介电层具有主表面，所述主表面至少覆盖在基板的第二区域上，并且，所述金属元件的端面凸出在所述主表面之上。
12.根据权利要求1所述的微电子封装，其中金属元件还具有以一轴线为中心的旋转曲面。
13.根据权利要求1所述的微电子封装，其中金属元件包括邻接所述结合金属的基部和邻接所述端面的顶部；并且，其中每一刚性的金属元件具有轴以及圆周表面，所述圆周表面沿所述轴、在垂直方向上朝向或远离所述轴倾斜，使得圆周壁的斜率在所述顶部与所述基部之间的边界处突然改变。
14.根据权利要求1所述的微电子封装，其中金属元件由从下列材料组成的群组中选择的材料组成：铜、镍、金或它们的任意组合。
15.根据权利要求14所述的微电子封装，其中结合金属的熔点低于300ºC。
16.根据权利要求1所述的微电子封装，其中所述金属元件的高度贯穿了覆盖在至少基板第二区域之上的模制介电层的至少60%的厚度。
17.根据权利要求1所述的微电子封装，其中结合金属的高度贯穿了覆盖在至少基板第二区域之上的模制介电层的至少60%的厚度。
18.根据权利要求17所述的微电子封装，其中金属元件为垫。
19.根据权利要求1所述的微电子封装，进一步包括设置在所述模制介电层的外表面上的第二基板和暴露在所述第二基板的表面并与所述金属元件的端面电连接的第二导电垫。
20.微电子组件，包括：
根据权利要求1所述的微电子封装，其中该微电子封装为第一微电子封装，和
第二微电子封装，包括外表面和微电子元件，所述外表面上设有复数个暴露在其表面上的连接元件，所述微电子元件与所述连接元件电连接；
其中所述第二微电子封装的外表面的至少一部分覆盖在模制介电层的表面的至少一部分上，并且第二微电子封装的连接元件与第一微电子封装的导电凸起的端面形成电连接和机械连接。
21.微电子系统，包括根据权利要求1所述的微电子封装，以及与所述微电子封装电连接的一个或多个其他电子元器件。
22.根据权利要求21所述的微电子系统，还包括壳体，所述微电子封装和所述其他电子元器件安装至所述壳体。
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