CN103258228A - Ultrahigh frequency RFID reader, base band system on chip (SOC) and port control method - Google Patents
Ultrahigh frequency RFID reader, base band system on chip (SOC) and port control method Download PDFInfo
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Abstract
The invention discloses an ultrahigh frequency RFID reader, a base band system on chip (SOC) and a port control method. All functional units, such as a multi-protocol control unit, a modulation and demodulation unit, a radio frequency control unit, a predistortion unit, an analog-digital (AD/DA) conversion unit, which are required by base band signal processing are integrated with a microprocessor through the SOC, external equipment and system parameters of the chip are modified through an allocated open-type port so as to achieve functions such as collision prevention, protocol control, data bases and middleware and accord with specific application. The SOC chip supports all of the characteristics stated in the ISO18000-6B/6C and other protocols, is adjustable in reading speed, selectable in modulation mode, capable of conveniently maintaining and updating a system, and meanwhile has the advantages of being high in integrity, low in power consumption, high in generality, low in cost, high in performance.
Description
Technical field
The present invention relates to ultra-high frequency RFID technology, relate in particular to a kind of ultrahigh frequency radio frequency identification (RFID) reader, baseband SOC chip and interface control method.
Background technology
Passive type ultrahigh frequency identification UHF rfid system (working frequency range is 860MHz-960MHz) adopts the backscattered modulation pattern, work in the far-field radiation district, have reading/writing distance far away (can reach 3-10 rice), non-visual, characteristics such as read or write speed is fast, label is passive, make it be widely used in fields such as warehouse logistics, parking lot management, asset management, valuables be antitheft.Passive type super high frequency radio frequency identification rfid system is made of read write line, electronic tag and background application system, and wherein read write line and electronic tag are the keys of total system.Electronic tag internal passive and adopt the power supply of passive far end radio frequency, internal resource is limited, can't finish complicated signal to handle, and therefore, the design performance of read write line is the key point of total system performance in rfid system.
Ultrahigh frequency reader-writer is divided into radio-frequency module and baseband module two parts from structure.As shown in Figure 1, wherein radio-frequency module mainly is made up of modulation-demodulation circuit and antenna, mainly finishes the modulation of high-frequency signal, and send and receive, be the air wireless interface between label and the read write line.Baseband module mainly is made of digital signal processing module and agreement control module two parts, digital signal processing module mainly be responsible for to produce the required baseband signal of different modulating mode, and the agreement control module mainly is responsible for the coding/decoding, generation check code of the data of sending out or data are carried out verification, data are carried out framing or unpacked and to the control of radio-frequency head etc.The main task of radio-frequency module is specifically: 1) emission high-frequency signal, and the active electron label, and provide energy for electronic tag; 2) modulate emission signal is moved tremendously high frequency with the baseband signal that baseband module produces, and is sent to electronic tag by antenna; (3) receive also demodulation from the signal of electronic tag.The main task of baseband module is: 1) communicates with application systems software, and the action command that sends of executive system software; 2) signal that receives is carried out synchronously, carry out the filtering moulding to sending signal; 3) according to agreement regulation to the data that the receive reconciliation of encoding; 4) communication process of control and label; 5) anti-collision algorithm of the many labels of realization; 6) realize that the CRC Code And Decode advances control to radio-frequency module; 7) to the encryption that transmits data or decryption processing etc.
At present ultrahigh frequency radio frequency identification (RFID) reader often adopts special chip+MCU or discrete component+MCU or discrete component+DSP(FPGA) etc., but these schemes all have defective: 1) the read write line volume is big, is not suitable for miniaturized application; 2) peripheral circuit complexity; 3) Performance Match is limited, and power consumption is big, cost is high, has caused the such scheme application limitation big.
Summary of the invention
In view of this, technical matters to be solved by this invention is to propose a kind of ultrahigh frequency radio frequency identification (RFID) reader, baseband SOC chip and interface control method, and described card reader and baseband SOC chip have the advantage of high integration, low-power consumption, high universalizable, low cost, high-performance, highly versatile.
For reaching this purpose, the present invention by the following technical solutions:
A kind of baseband SOC chip of ultrahigh frequency radio frequency identification (RFID) reader, comprise microprocessor module, reset and clock control module, debugging interface, memory interface, high-speed communication interface, low-speed communication interface, bus on chip, timer module, external interrupt control module, A/D modular converter and D/A modular converter
Described chip also comprises multi-protocols processing module, bus control module and bus conversion module;
Wherein, described bus on chip comprises high speed system bus AHB and low speed peripheral bus APB, and described high speed system bus AHB and low speed peripheral bus APB carry out the bus conversion by bridge, and every bus all is provided with address decoder and bus arbiter; Microprocessor module, debugging interface, memory interface, high-speed communication interface, multi-protocols processing module, bus control module and bus conversion module are connected with described high speed system bus AHB;
Timer module, external interrupt control module and low-speed communication interface are connected with the low speed peripheral bus; The A/D modular converter is connected with the multi-protocols processing module respectively with the D/A modular converter, and resetting is connected with microprocessor module with clock control module;
Described multi-protocols processing module comprises the ahb bus interface, RAM, control register, downsampling unit, variable bandwidth filter, the phase place recovery unit, matched filter, the sampling decision unit, decoding unit, the first CRC check unit, string and converting unit, receive the state of a control machine, parallel serial conversion unit, send the state of a control machine, the second CRC check unit, coding unit, the power unit for scaling, hilbert filter, pre-distortion unit, lag line, frequency hopping control module and up-sampling unit.
Further, described downsampling unit comprises first order downsampling unit and second level downsampling unit, and described second level downsampling unit sampling multiple is adjustable; Described decoding unit comprises FM0 decoding unit and miller decoding unit; Described coding unit comprises PIE coding unit and Manchester coding unit.
Further, described multi-protocols processing module is supported PR-ASK, DSB-ASK and three kinds of modulation systems of SSB-ASK, wherein, the PR-ASK base band signal modulated is produced by the PIE coding unit, the SSB-ASK base band signal modulated is produced by Xi Er baud wave filter and lag line, and DSB-ASK produces by the output of shielding hilbert filter.
Further, described variable bandwidth filter adopts the algorithm structure of expansion Fourier transform to realize that filter bandwidht is variable; Perhaps, adopt and change the coefficient storage form into RAM, when chip initiation, write the adaptive-bandwidth that required bandwidth filter coefficient is realized wave filter.
Further, described chip also comprises one group of special I/O mouth, is used for the control information of feedback information or the transmission radio-frequency front-end of receiving radio frequency front end.
Further, described D/A modular converter comprises 10 DAC output channels of two-way, is respectively applied to the needed I passage of quadrature modulator and Q passage baseband digital signal; One tunnel 8 DAC output channel is used for providing power amplifier control information; Described A/D modular converter comprises 10 ADC input channels of two-way, is respectively applied to import I passage after the quadrature demodulation and the baseband digital signal of Q passage.
Further,
Described debugging interface comprises JTAG debugging interface and serial debugging interface;
Described high-speed communication interface disposes USB2.0 interface, Ethernet interface and GPIO interface;
Described low-speed communication interface configuration has UART interface, SPI interface and I2C interface;
Described timer module disposes 2 16 bit timing counter timers and real-time clocks;
Described memory interface disposes PROM, SRAM, SDRAM, DDR2 and FLASH interface.
Correspondingly, the present invention also discloses a kind of ultrahigh frequency radio frequency identification (RFID) reader, and described read write line comprises baseband SOC chip and radio-frequency module, and described baseband SOC chip and radio-frequency module are electrically connected,
Described radio-frequency module comprises modulation-demodulation circuit and antenna, and described modulation-demodulation circuit is used for finishing the modulation and demodulation of high-frequency signal, and described antenna is used for finishing transmission and the reception of high-frequency signal;
Described baseband SOC chip comprises microprocessor module, resets and clock control module, debugging interface, memory interface, high-speed communication interface, low-speed communication interface, bus on chip, timer module, external interrupt control module, A/D modular converter, D/A modular converter, multi-protocols processing module, bus control module and bus conversion module;
Wherein, described bus on chip comprises high speed system bus AHB and low speed peripheral bus APB, and described high speed system bus AHB and low speed peripheral bus APB carry out the bus conversion by bridge, and every bus all is provided with address decoder and bus arbiter; Microprocessor module, debugging interface, memory interface, high-speed communication interface, multi-protocols processing module, bus control module and bus conversion module are connected with described high speed system bus AHB;
Timer module, external interrupt control module and low-speed communication interface are connected with the low speed peripheral bus; The A/D modular converter is connected with the multi-protocols processing module respectively with the D/A modular converter, and resetting is connected with microprocessor module with clock control module;
Described multi-protocols processing module comprises the ahb bus interface, RAM, control register, downsampling unit, variable bandwidth filter, the phase place recovery unit, matched filter, the sampling decision unit, decoding unit, the first CRC check unit, string and converting unit, receive the state of a control machine, parallel serial conversion unit, send the state of a control machine, the second CRC check unit, coding unit, the power unit for scaling, hilbert filter, pre-distortion unit, lag line, frequency hopping control module and up-sampling unit.
Further, described downsampling unit comprises first order downsampling unit and second level downsampling unit, and described second level downsampling unit sampling multiple is adjustable; Described decoding unit comprises FM0 decoding unit and miller decoding unit; Described coding unit comprises PIE coding unit and Manchester coding unit.
A kind of control method of ultrahigh frequency RFID card reader transmission interface, this method comprise,
Write and send the data buffer memory;
Write control register;
Detection is sent completely zone bit;
Be sent completely zone bit zero clearing in the threshold value at the fixed time when described, return analog value and send successful information; Be sent completely zone bit not zero clearing in the threshold value at the fixed time when described, withdraw from behind the described zone bit that resets, and return error message.
A kind of control method of ultrahigh frequency RFID card reader receiving interface, this method comprise,
Write control register;
Receive the data buffer memory;
Detection is sent completely zone bit;
When being sent completely zone bit zero clearing in first schedule time threshold value, and detect CRC success zone bit in second schedule time threshold value built-in 1 o'clock, return analog value and receive successful information.
Technical scheme provided by the invention, support the characteristic of all ISO18000-6B/6C and other other New Deal defineds, read or write speed is adjustable, modulation system is optional, by each functional interface cutting in addition to having disposed, can carry out parameter modification, system maintenance and upgrading easily, to meet application-specific, simultaneously, has the advantage of high integration, low-power consumption, high universalizable, low cost, high-performance, highly versatile.
Description of drawings
Fig. 1 is the basic structure block diagram of read write line in the prior art;
The structured flowchart of the SOC chip of the ultrahigh frequency radio frequency identification (RFID) reader that Fig. 2 provides for first embodiment of the invention;
The structured flowchart of the multi-protocols processing module that Fig. 3 provides for second embodiment of the invention;
The structured flowchart of the ultrahigh frequency radio frequency identification (RFID) reader that Fig. 4 provides for third embodiment of the invention;
The ultrahigh frequency radio frequency identification (RFID) reader emission interface workflow diagram that Fig. 5 provides for the embodiment of the invention;
The ultrahigh frequency radio frequency identification (RFID) reader receiving interface workflow diagram that Fig. 6 provides for the embodiment of the invention.
Embodiment
Further specify technical scheme of the present invention below in conjunction with accompanying drawing and by embodiment.Specific embodiment described herein only is used for explaining the present invention, but not limitation of the invention.
SOC (System on Chip) is system level chip, be that functional units such as peripheral hardware, communication interface, A/D and D/A conversion in the needed microprocessor of system, the sheet are integrated on a slice chip, the SOC (system on a chip) that forms has characteristics such as high integration, cost are low, good reliability, low-power consumption.
The structured flowchart of the SOC chip of the ultrahigh frequency radio frequency identification (RFID) reader that Fig. 2 provides for first embodiment of the invention.As shown in Figure 2, described baseband SOC chip comprises microprocessor module, resets and clock control module, debugging interface, memory interface, high-speed communication interface, low-speed communication interface, bus on chip, timer module, external interrupt control module, A/D modular converter, D/A modular converter, multi-protocols processing module, bus control module and bus conversion module;
Wherein, described bus on chip comprises high speed system bus AHB and low speed peripheral bus APB, and described high speed system bus AHB and low speed peripheral bus APB carry out the bus conversion by bridge, and every bus all is provided with address decoder and bus arbiter; Microprocessor module, debugging interface, memory interface, high-speed communication interface, multi-protocols processing module, bus control module and bus conversion module are connected with described high speed system bus AHB;
Timer module, external interrupt control module and low-speed communication interface are connected with the low speed peripheral bus; The A/D modular converter is connected with the multi-protocols processing module respectively with the D/A modular converter, and resetting is connected with microprocessor module with clock control module, and described microprocessor module has the low power consumption control function;
Described multi-protocols processing module comprises the ahb bus interface, RAM, control register, downsampling unit, variable bandwidth filter, the phase place recovery unit, matched filter, the sampling decision unit, decoding unit, the first CRC check unit, string and converting unit, receive the state of a control machine, parallel serial conversion unit, send the state of a control machine, the second CRC check unit, coding unit, the power unit for scaling, hilbert filter, pre-distortion unit, lag line, frequency hopping control module and up-sampling unit.
In the present embodiment, microprocessor module adopts the CPU core (as the kernel based on leon3) of 32 SPARC frameworks, and this CPU core can be finished the functions such as coordination, configuration and status monitoring of whole SOC chip respectively being formed module by instruction.Utilize software to realize functions such as anti-collision algorithm, protocol stack control at this CPU nuclear, also can be at these kernel operation various common embedded OSs (as Linux or Windows etc.).Described microprocessor has the low power consumption control function, various modes such as support power down, standby, work, wake up, and can independently control each interface module.The mode that the implementation of low-power consumption adopts the dynamic clock Control of Voltage to be combined with gated clock.
Two buses of having followed the AMBA2.0 protocol configuration in the SOC chip based on the leon3 kernel certainly, just describe with specific embodiment herein.As adopting the core chip of other frameworks, the module of interface protocol can realize by the corresponding bus module modular converter of design.
Described debugging interface comprises JTAG debugging interface and serial debugging interface, supports on-line debugging and program to download.
Described memory interface disposes PROM, SRAM, SDRAM, DDR2 and FLASH interface etc.
Described D/A modular converter comprises 10 DAC output channels of two-way, is respectively applied to the needed I passage of quadrature modulator and Q passage baseband digital signal; One tunnel 8 DAC output channel is used for providing power amplifier control information; Described A/D modular converter comprises 10 ADC input channels of two-way, is respectively applied to import I passage after the quadrature demodulation and the baseband digital signal of Q passage.
Described chip also comprises one group of special I/O mouth, is used for the control information of feedback information or the transmission radio-frequency front-end of receiving radio frequency front end.Along with the different needed control of radio-frequency front-end is different with feedback information, this part is actual to be to design for chip adapts to different radio-frequency front-ends.
High-speed communication interface disposes USB2.0, Ethernet interface, GPIO interface, is convenient to expand new equipment.USB2.0 comprises two kinds of interfaces of principal and subordinate.
The low-speed communication interface configuration has UART interface, SPI interface, IIC interface and two groups 32 s' GPIO mouth.
Timer module comprises 2 16 bit timing counter timers and real-time clocks, can be used as WatchDog Timer, or the PWN output function.
The structured flowchart of the multi-protocols processing module that Fig. 3 provides for second embodiment of the invention.Described multi-protocols processing module is supported ISO18000-6C/6B agreement (this chip is not only supported two kinds of agreements of ISO18000-6B/6C, can also and be used in combination different functional modules by software and realize self-defining agreement).ISO18000-6C/6B is the most frequently used, state-of-the-art two kinds of read write line communication protocols at present, has plurality of advantages such as communication speed is fast, the anticollision performance is good, readable tag quantity is many.In the present embodiment, described multi-protocols processing module comprises the AHB high speed bus interface, RAM, control register, two 16 times of downsampling unit, two 1248 times of variable downsampling unit, a variable bandwidth filter unit, a digital phase place recovery unit, a matched filter unit, a power detector unit, a sampling decision unit, a FM0 decoding unit, a miller decoding unit, two CRC-16 verification unit, a CRC-5 verification unit, go here and there and converting unit for one, one receives the state of a control machine, a parallel serial conversion unit, one sends the state of a control machine, a PIE coding unit, a power unit for scaling, a hilbert filter, a pre-distortion unit, one group of lag line, a frequency hopping control module, a frequency correction unit, the up-sampling unit of multiplexed unit and two 4 times.Described PIE coding unit has the PR-ASK function.
Described multi-protocols processing module is supported PR-ASK, DSB-ASK and three kinds of modulation systems of SSB-ASK, wherein, the PR-ASK base band signal modulated is produced by the PIE coding unit, the SSB-ASK base band signal modulated is produced by Xi Er baud wave filter and lag line, and DSB-ASK produces by the output of shielding hilbert filter.Described pre-distortion unit is only worked under the situation that adopts the SSB-ASK mode to modulate.
Described variable bandwidth filter adopts the algorithm structure of expansion Fourier transform to realize that filter bandwidht is variable; Perhaps, adopt and change the coefficient storage form into RAM, when chip initiation, write the adaptive-bandwidth that required bandwidth filter coefficient is realized wave filter.
PIE coding, FM0 decoding, Miller decoding, CRC check, the RSSI that can finish baseband signal by described multi-protocols processing module detect, receive the clock information recovery of signal, the predistortion that transmits, generation frame synchronization sequence, the state control of requirement etc. that carries on an agreement, and the control information of protocol stack and anti-collision algorithm operate in microprocessor module with the form of software.This mode makes chip have stronger upgrading ability.
When described multi-protocols processing module sends information, the course of work is as follows: after main frame or input equipment are sent to leon3 with control information, leon3 writes required transmission data among the RAM in corresponding address space in the protocol process module according to the requirement of protocol stack, then control register is arranged, with required control information (as data length, the form of synchronous head, the data coded system, the CRC check mode, send data rate etc.) write in the control register, at last with the transmission enable bit set in the control register, module enters transmission flow, the state of a control machine is according to the information in the control register, data are read from RAM, after also string is changed, send into the CRC check module (CRC-5 or CRC-16) of the first CRC check unit correspondence, the CRC check module of described correspondence produces the corresponding check sign indicating number, and with the packing of data and check code (be about to check code be added on former data after), serial input coding module (PIE coding or Manchester coding), coding module to encode (PIE coding or Manchester coding or PR-ASK coding) back and add corresponding frame head of data, makes data form corresponding frame format according to the information in the control register.Then the data after the framing are sent into the raised cosine filter filtering moulding of roll-offing, after carry out the power convergent-divergent, send into modulation module.According to the information in the control register, select corresponding modulation system, if the DSB-ASK modulation system is then sent into the delayed line of the data after the filtering moulding DAC output of I path, the data after the filtering moulding are sent into the DAC output of Q channel after predistortion.If the SSB-ASK modulation system is then sent into the delayed line of the data after the filtering moulding DAC output of I path, the data after the filtering moulding are sent into the DAC output of Q channel after hilbert filter filtering.
When described multi-protocols processing module receives information, the course of work is as follows: through the I of quadrature receiver output, the Q two paths of signals, at first be converted to digital signal through built-in A/D converter after sending into chip, because A/D is over-sampling a/d C, so digital signal needs the down-sampling through 16 times, the back according to the different choice 1 of receiving velocity 248 times down-sampling (receiving velocity is determined by the order of taking inventory in the agreement, the speed that this means the label return data is determined by read write line, so label return data speed is known for read write line is seen), after the data process variable bandwidth filter filtering of the down-sampling second time, send into digital CDR module (phase bit recovery module) and carry out the recovery of data clock information, the clock information that recovers to come out is sent into the sampling judging module, data message through matched filtering is sampled, data after the sampling are sent into corresponding decoder module (FM0 or miller are determined by control register) decoding, decoded data through the second CRC check unit verification after, after sending into string and modular converter, under the control that receives the state of a control machine, write the RAM in corresponding address space, and the set of accepting state position is represented to accept data finish.After leon3 detects the zone bit set, corresponding RAM data are read, require to handle accordingly according to protocol stack.
The ultrahigh frequency radio frequency identification (RFID) reader emission interface workflow diagram that Fig. 5 provides for the embodiment of the invention.As shown in Figure 5, during this interface routine of application call, idiographic flow comprises:
Step 501: interface routine carries out initialization earlier.
Step 502: write and send the data buffer memory.
The data that reception is passed over by primary application program, and will send the AHB address that data are write protocol processing unit transmission path correspondence continuously.
Step 503: write control register.
After writing data and finishing, interface routine will receive the control register information that master routine transmits, and these information are write in the control register (such as: send data length, the selection of transmission rate, the selection of modulation system, the coefficient of wave filter, the coefficient of predistortion etc.).
Step 504: detect and be sent completely zone bit.Send in the control register link enable position 1 time, the transtation mission circuit of protocol processing unit is started working and will send the link enable bit after being finished dealing with and passes through the hardware zero clearing.
Step 505: judge to be sent completely zone bit whether zero clearing in the threshold value T at the fixed time, in this way, execution in step 506; Otherwise, execution in step 507.
Described schedule time threshold value T is the time-out time that interface software arranges, and this time can be according to the actual conditions setting.
Step 506: detected in the T at the fixed time when this position has been cleared in the control register, returned analog value and send successful information.
Step 507: do not detect the control register corresponding positions at the fixed time in the T and be cleared, software quits a program this zone bit zero clearing, and returns error message.
The ultrahigh frequency radio frequency identification (RFID) reader receiving interface workflow diagram that Fig. 6 provides for the embodiment of the invention.During this interface routine of application call, idiographic flow is as follows:
Step 601: interface routine at first carries out initialization.
Step 602: write control register.
The control register information that reception is transmitted by master routine, and write appropriate address.
Step 603: receive the data buffer memory.
After the reception enable bit put 1 by program in the control register, the receiving circuit of protocol processing unit began to receive the label return data that analog end transmits, and these data are write the AHB address that protocol processing unit receives the path correspondence.
Step 604: detect and be sent completely zone bit.After data all write, hardware will finish receiving the sign zero clearing to data.
Step 605: judge to be sent completely zone bit whether zero clearing in the threshold value T1 at the fixed time, in this way, execution in step 606; Otherwise, execution in step 609.
Described schedule time threshold value T1 is the time-out time that interface software arranges, and this time can be according to the actual conditions setting.
Step 606: interface routine begins to detect CRC check success zone bit in the control register.
Step 607: judge whether CRC success zone bit puts 1 in the threshold value T2 at the fixed time, in this way, execution in step 608; Otherwise, execution in step 609.
Described schedule time threshold value T2 also is the time-out time that interface software arranges, and this time can be according to the actual conditions setting.
Step 608: return analog value and receive successful information.
Step 609: withdraw from after being resetted by interface routine, and return error message.
The structured flowchart of the ultrahigh frequency radio frequency identification (RFID) reader that Fig. 4 provides for third embodiment of the invention.As shown in Figure 4, described read write line comprises baseband SOC chip and radio-frequency module, described baseband SOC chip is connected with radio-frequency module, described radio-frequency module comprises modulation-demodulation circuit and antenna, described modulation-demodulation circuit is used for finishing the modulation and demodulation of high-frequency signal, and described antenna is used for finishing transmission and the reception of high-frequency signal;
Described baseband SOC chip comprises microprocessor module, resets and clock control module, debugging interface, memory interface, high-speed communication interface, low-speed communication interface, bus on chip, timer module, external interrupt control module, GPIO interface, A/D modular converter, D/A modular converter, multi-protocols processing module, bus control module and bus conversion module;
Wherein, described bus on chip comprises high speed system bus AHB and low speed peripheral bus APB, and described high speed system bus AHB is connected by bridge with low speed peripheral bus APB, and every bus all is provided with address decoder and bus arbiter; Microprocessor module, debugging interface, memory interface, high-speed communication interface, GPIO interface, multi-protocols processing module, bus control module and bus conversion module are connected with described high speed system bus AHB;
Timer module, external interrupt control module and low-speed communication interface are connected with the low speed peripheral bus; The A/D modular converter is connected with the multi-protocols processing module respectively with the D/A modular converter, and resetting is connected with microprocessor module with clock control module, and described microprocessor module has the low power consumption control function;
Described multi-protocols processing module comprises the ahb bus interface, RAM, control register, downsampling unit, variable bandwidth filter, the phase place recovery unit, matched filter, the sampling decision unit, decoding unit, the first CRC check unit, string and converting unit, receive the state of a control machine, parallel serial conversion unit, send the state of a control machine, the second CRC check unit, coding unit, the power unit for scaling, hilbert filter, pre-distortion unit, lag line, frequency hopping control module and up-sampling unit.
Wherein, described downsampling unit comprises first order downsampling unit and second level downsampling unit, and described second level downsampling unit sampling multiple is adjustable; Described decoding unit comprises FM0 decoding unit and miller decoding unit; Described coding unit comprises PIE coding unit and Manchester coding unit.
Described multi-protocols processing module is supported PR-ASK, DSB-ASK and three kinds of modulation systems of SSB-ASK, wherein, the PR-ASK base band signal modulated is produced by the PIE coding unit, the SSB-ASK base band signal modulated is produced by Xi Er baud wave filter and lag line, and DSB-ASK produces by the output of shielding hilbert filter.
The technical scheme that present embodiment provides, support required various base band signal process functions, agreement control function, codec functions, radio frequency control function, predistortion function, synchronizing function, modulatedemodulate Power Regulation and the processor of UHF rfid interrogator of ISO18000-6C/B agreement to integrate, and can realize support to custom protocol by the mode of revising software.Microprocessor unit (realizing based on the 32bit SPARC framework CPU leon3 that increases income) is arranged in the chip, can Embedded Operating System (linux, uc-os etc.), but the capacity of extended memory, the protocol processing unit of integrated support ISO18000-6C/B, this unit is embedded in the bus as an AHB slave module, and chip also provides open software interface, is used for realizing functions such as anticollision, agreement control, database, middleware.Can be applied to various UHFRFID application scenario easily.
All or part of content in the technical scheme that above embodiment provides can realize that its software program is stored in the storage medium that can read by software programming, storage medium for example: small-sized storages such as FLASH chip, SD card are equipped with.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. the baseband SOC chip of a ultrahigh frequency radio frequency identification (RFID) reader, comprise microprocessor module, reset and clock control module, debugging interface, memory interface, high-speed communication interface, low-speed communication interface, bus on chip, timer module, external interrupt control module, A/D modular converter and D/A modular converter, it is characterized in that
Described chip also comprises multi-protocols processing module, bus control module and bus conversion module;
Wherein, described bus on chip comprises high speed system bus AHB and low speed peripheral bus APB, and described high speed system bus AHB and low speed peripheral bus APB carry out the bus conversion by bridge, and every bus all is provided with address decoder and bus arbiter; Microprocessor module, debugging interface, memory interface, high-speed communication interface, multi-protocols processing module, bus control module and bus conversion module are connected with described high speed system bus AHB;
Timer module, external interrupt control module and low-speed communication interface are connected with the low speed peripheral bus; The A/D modular converter is connected with the multi-protocols processing module respectively with the D/A modular converter, and resetting is connected with microprocessor module with clock control module;
Described multi-protocols processing module comprises the ahb bus interface, RAM, control register, downsampling unit, variable bandwidth filter, the phase place recovery unit, matched filter, the sampling decision unit, decoding unit, the first CRC check unit, string and converting unit, receive the state of a control machine, parallel serial conversion unit, send the state of a control machine, the second CRC check unit, coding unit, the power unit for scaling, hilbert filter, pre-distortion unit, lag line, frequency hopping control module and up-sampling unit.
2. the baseband SOC chip of ultrahigh frequency radio frequency identification (RFID) reader according to claim 1 is characterized in that, described downsampling unit comprises first order downsampling unit and second level downsampling unit, and described second level downsampling unit sampling multiple is adjustable; Described decoding unit comprises FM0 decoding unit and miller decoding unit; Described coding unit comprises PIE coding unit and Manchester coding unit.
3. the baseband SOC chip of ultrahigh frequency radio frequency identification (RFID) reader according to claim 2, it is characterized in that, described multi-protocols processing module is supported PR-ASK, DSB-ASK and three kinds of modulation systems of SSB-ASK, wherein, the PR-ASK base band signal modulated is produced by the PIE coding unit, the SSB-ASK base band signal modulated is produced by Xi Er baud wave filter and lag line, and DSB-ASK produces by the output of shielding hilbert filter.
4. the baseband SOC chip of ultrahigh frequency radio frequency identification (RFID) reader according to claim 1 is characterized in that, described variable bandwidth filter adopts the algorithm structure of expansion Fourier transform to realize that filter bandwidht is variable; Perhaps, adopt and change the coefficient storage form into RAM, when chip initiation, write the adaptive-bandwidth that required bandwidth filter coefficient is realized wave filter.
5. according to the baseband SOC chip of the described ultrahigh frequency radio frequency identification (RFID) reader of one of claim 1 to 4, it is characterized in that, described D/A modular converter comprises 10 DAC output channels of two-way, is respectively applied to the needed I passage of quadrature modulator and Q passage baseband digital signal; One tunnel 8 DAC output channel is used for providing power amplifier control information; Described A/D modular converter comprises 10 ADC input channels of two-way, is respectively applied to import I passage after the quadrature demodulation and the baseband digital signal of Q passage.
6. according to the baseband SOC chip of the described ultrahigh frequency radio frequency identification (RFID) reader of one of claim 1 to 4, it is characterized in that,
Described debugging interface comprises JTAG debugging interface and serial debugging interface;
Described high-speed communication interface disposes USB2.0 interface, Ethernet interface and GPIO interface;
Described low-speed communication interface configuration has UART interface, SPI interface and I2C interface;
Described timer module disposes 2 16 bit timing counter timers and real-time clocks;
Described memory interface disposes PROM, SRAM, SDRAM, DDR2 and FLASH interface.
7. a ultrahigh frequency radio frequency identification (RFID) reader is characterized in that, described read write line comprises baseband SOC chip and radio-frequency module, and described baseband SOC chip and radio-frequency module are electrically connected,
Described radio-frequency module comprises modulation-demodulation circuit and antenna, and described modulation-demodulation circuit is used for finishing the modulation and demodulation of high-frequency signal, and described antenna is used for finishing transmission and the reception of high-frequency signal;
Described baseband SOC chip comprises microprocessor module, resets and clock control module, debugging interface, memory interface, high-speed communication interface, low-speed communication interface, bus on chip, timer module, external interrupt control module, A/D modular converter, D/A modular converter, multi-protocols processing module, bus control module and bus conversion module;
Wherein, described bus on chip comprises high speed system bus AHB and low speed peripheral bus APB, and described high speed system bus AHB and low speed peripheral bus APB carry out the bus conversion by bridge, and every bus all is provided with address decoder and bus arbiter; Microprocessor module, debugging interface, memory interface, high-speed communication interface, multi-protocols processing module, bus control module and bus conversion module are connected with described high speed system bus AHB;
Timer module, external interrupt control module and low-speed communication interface are connected with the low speed peripheral bus; The A/D modular converter is connected with the multi-protocols processing module respectively with the D/A modular converter, and resetting is connected with microprocessor module with clock control module;
Described multi-protocols processing module comprises the ahb bus interface, RAM, control register, downsampling unit, variable bandwidth filter, the phase place recovery unit, matched filter, the sampling decision unit, decoding unit, the first CRC check unit, string and converting unit, receive the state of a control machine, parallel serial conversion unit, send the state of a control machine, the second CRC check unit, coding unit, the power unit for scaling, hilbert filter, pre-distortion unit, lag line, frequency hopping control module and up-sampling unit.
8. ultrahigh frequency radio frequency identification (RFID) reader according to claim 7 is characterized in that, described downsampling unit comprises first order downsampling unit and second level downsampling unit, and described second level downsampling unit sampling multiple is adjustable; Described decoding unit comprises FM0 decoding unit and miller decoding unit; Described coding unit comprises PIE coding unit and Manchester coding unit.
9. the control method of a ultrahigh frequency RFID card reader transmission interface is characterized in that, this method comprises,
Write and send the data buffer memory;
Write control register;
Detection is sent completely zone bit;
Be sent completely zone bit zero clearing in the threshold value at the fixed time when described, return analog value and send successful information; Be sent completely zone bit not zero clearing in the threshold value at the fixed time when described, withdraw from behind the described zone bit that resets, and return error message.
10. the control method of a ultrahigh frequency RFID card reader receiving interface is characterized in that, this method comprises,
Write control register;
Receive the data buffer memory;
Detection is sent completely zone bit;
When being sent completely zone bit zero clearing in first schedule time threshold value, and detect CRC success zone bit in second schedule time threshold value built-in 1 o'clock, return analog value and receive successful information.
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