CN103226169A

CN103226169A - Square wave detector for wireless wake-up circuit

Info

Publication number: CN103226169A
Application number: CN2012101910984A
Authority: CN
Inventors: 何文涛; 葛亮; 甘业兵; 钱敏; 马成炎
Original assignee: JIAXING LIANXING MICROELECTRONIC CO Ltd
Current assignee: HANGZHOU ZHONGKE MICROELECTRONICS Co.,Ltd.
Priority date: 2012-06-12
Filing date: 2012-06-12
Publication date: 2013-07-31
Anticipated expiration: 2032-06-12
Also published as: CN103226169B

Abstract

The invention provides a square wave detector for a wireless wake-up circuit. The frequency of the square wave detector can be configured within the range of 10-200 kHz. The square wave detector comprises a signal acquisition circuit and a square wave detection circuit, wherein the square wave detection circuit comprises a jitter detection module path, a frequency detection module path, a relevant detection module path and an AND circuit which are used for respectively detecting the duty factor, the frequency and the relevance of an input sampling signal; and when outputs of the three detection module paths are high levels respectively, the output of the AND circuit is also high level and the square wave detection circuit outputs a wake-up signal. By detecting the jitter, the frequency and the relevance of the input sampling signal, the accurate judgment and clutter reduction are realized, the mistaken wake-up probability is effectively reduced, the wake-up probability is increased and the wake-up time is remarkably shortened, thereby increasing the work efficiency of a wake-up receiver and reducing the power consumption of the system. The square wave detector provided by the invention is suitable for wake-up receiving circuits of an RFID (Radio Frequency Identification) system and an ETC (Electronic Toll Collection) system.

Description

A kind of square wave detecting device that is used for the wireless awakening circuit

Technical field

The invention belongs to the radio frequency electric technical field, the receiving circuit that wakes up that relates to the radio frequency discrimination RFID system, relate in particular to a kind of square wave detecting device that is used for the wireless awakening circuit, be applicable to active RFID system and electric non-stop toll ETC system, improve the work efficiency of waking receiver up effectively.

Background technology

In recent years, radio-frequency (RF) identification (RFID) technical development is swift and violent, and rfid system mainly is made up of radio-frequency identification reader (reader) and radio-frequency (RF) tag (tag).Whether rfid system has built-in power according to radio-frequency (RF) tag, is divided into active RFID system and passive RFID system two classes.The label of active RFID system has built-in power, has advantages such as high reliability, telecommunication, therefore, gains great popularity in recent years.Yet because radio-frequency (RF) tag relies on powered battery, power consumption is determining the mission life of radio-frequency (RF) tag.So, low-power consumption and energy-conservation be the major issue that active RFID system is paid close attention to the most.

On video tab, add and wake receiving circuit up, can reduce power consumption effectively.Waking ultimate principle up is: the high-frequency signal that wakes receiver up is after ovennodulation, send into the interior radio frequency envelope detector (RFED) of sheet and carry out rectification, obtain the modulation signal envelope, signal envelope amplifies through operational amplifier, the signal that is exaggerated is sent into comparer and is compared, and is driven into logic level, obtains the square-wave signal of demodulation, by the logical frequency discriminator of band the square-wave signal of demodulation is adjudicated again, take a decision as to whether effective wake-up signal.If the square-wave signal frequency of this demodulation is positioned within the frequency range of setting, be judged to be effective wake-up signal, send into the interrupt that wakes receiver MCU up and interrupt.

Yet, not effective radiofrequency signal if wake the signal that receiver receives up, but mixed and disorderly waveform, late-class circuit also may have signal and produce, and will produce false wake-up this time.The square wave detecting device then is to be added in to wake the receiver rear end up, mainly is with the problem that solves false wake-up.Input signal judges through the laggard capable detection of over-sampling whether NkHz (for example 14kHz) square wave is correct, if, then export high level, drive late-class circuit work, if input has problem, then do not wake up.Thereby realization condition wakes up and the low-power consumption purpose of energy saving.

The patent No. 200820141876.8 of prior art, name is called the patent of " scale transformation stochastic resonance square wave pick-up unit ", make up peripheral circuit by modulus (AD) conversion chip and digital signal processing (DSP) chip and finish the square wave detection, this prior art exists utilizes peripheral circuit to increase the defective of the poor reliability of circuit cost and circuit.

The patent No. 200810151278.3 of prior art, name is called " system for detecting cascade programmed control frequency accidental resonance square wave ", and this invention is based on the design of printed circuit board (PCB) (PCB), has peripheral circuit complex structure and the high defective of false wake-up probability.

The patent No. 01144557.2 of prior art, name are called " detection method that synchronization signal detection circuit device and this device thereof detect synchronizing signal ", and this invention exists the detection method structure too single, the defective that the false wake-up probability is high.

Summary of the invention

The objective of the invention is for problems such as the design cost height that overcomes the printed circuit board (PCB) level that prior art exists, peripheral circuit complex structure, false wake-up probability height, to the NkHz(that wakes receiver output among the RFID up 14K for example) square wave distinguishes processing, improve the probability that wakes up of correct signal, reduce the probability that rub-out signal produces false wake-up, and reduce wakeup time.

The objective of the invention is to be achieved through the following technical solutions:

A kind of square wave detecting device that is used for the wireless awakening circuit, it is that the square wave detecting device comprises:

A signal sample circuit, sample frequency are M times of input signal NkHz, and the span of N is 10～200, and be definite by the system at wireless awakening circuit place; The square wave that with sample frequency is MNkHz is sampled to the NkHz intermediate-freuqncy signal of input, and the span of M is 4,8,16;

The N value is according to the intermediate-freuqncy signal frequency setting of upper system, and the electric non-stop toll ETC N of system value is 14 usually, and active RFID system N value is 156.Realize the configuration of square wave detecting device to detection signal frequency N kHz, the configuration scope that detects frequency N kHz is 10～200KHz, and finishing the detection signal frequency is best configuration, and the wakeup time of wake-up circuit is reduced.Sample frequency is by finishing configuration to digital oscillator local oscillation signal M frequency multiplication, and the span of M is 4,8,16, is 8 as preferably getting the M value.For example N is 14, and M is 8, and input intermediate-freuqncy signal 14kHz samples to the 14kHz intermediate-freuqncy signal of input with the square wave of 112kHz.

A square wave testing circuit has shake detection module path, frequency detection module path and correlation detection module path, the input end of three detection module paths of square wave testing circuit all connects the output terminal of signal sample circuit, is used for the correctness judgement to dutycycle, frequency and the correlativity of input sample signal; The square wave testing circuit also has AND circuit, and AND circuit judges the output signal of three detection module paths, is used for being judged as output wake-up signal when correct;

Signal sample circuit is a kind of sampling hold circuit, the intermediate-freuqncy signal output terminal of the outer wireless awakening circuit of its input end brace, the output terminal of signal sample circuit connects the input end of square wave testing circuit, the wake-up signal end of the outer wireless awakening circuit of the output terminal brace of square wave testing circuit.

Described square wave detecting device, its shake detection, frequency detecting and three module paths of correlation detection and AND circuit that is described square wave testing circuit is integrated in same chip, and it constitutes:

A shake detection module path comprises a shake detection module, is used to detect the dutycycle of input signal;

A frequency detection module path comprises a frequency detection module, is used to detect the frequency of input signal;

A correlation detection module path comprises a correlation detection module, is used to detect the phase of input signals correlativity;

The AND circuit of one three input is used to export wake-up signal;

Shake detection module, frequency detection module and the input end of correlation detection module are connected the signal output part of signal sample circuit respectively, the output terminal of shake detection module, frequency detection module and correlation detection module is connected the input end of AND circuit of one three input respectively, be used to realize high level with export the correct wake-up signal of high level.

Described square wave detecting device, it is that described correlation detection module path comprises sampling hold circuit, digital oscillator, a pair of digital mixer, a pair of integration and summation circuit, envelope detected circuit and first comparator circuit; A pair of digital mixer and a pair of integration and summation circuit constitute computing cross-correlation device circuit; The output terminal of sampling hold circuit links to each other with the input end of a pair of digital mixer respectively, the signal end of a pair of digital mixer links to each other with the digital oscillator output terminal respectively, the signal end of a pair of digital mixer links to each other with the digital oscillator output terminal respectively, and the output terminal of a pair of digital mixer links to each other with the corresponding first integrator and the input end of second integral device respectively; The output terminal of first integrator connects the input end of first totalizer, and the output terminal of second integral connects the input end of second totalizer; The output terminal of the output terminal of first totalizer and second totalizer is corresponding respectively to link to each other with an input end of envelope detected circuit, is used for the mean value of comprehensive detection input signal dutycycle and frequency; The output terminal of envelope detected circuit links to each other with the input end of first comparator circuit, and the output terminal of first comparer connects an input end of AND circuit.

The correlation detection module be based on sampled signal and the local oscillation signal of pair of orthogonal do phase place relevant after, send the envelope detected circuit to make envelope detected again, the root mean square that is used for two-way totalizer output signal is handled, detect the mean value of input signal dutycycle and frequency, thereby realize the correlation detection of comprehensive input sample signal.

Described square wave detecting device, it is that described frequency detection module path comprises sampling hold circuit, and the frequency detection module that is made of an edge sense circuit and second comparator circuit; Frequency detection module is for adopting the structure of Digital Analog Hybrid Circuits, the input end of edge sense circuit connects sampling hold circuit, the output terminal of edge sense circuit connects an input end of second comparator circuit, another input end of second comparator circuit inserts the second amplitude threshold setting value, and the output terminal of second comparator circuit connects an input end of AND circuit; Frequency detection module adopts the Digital Analog Hybrid Circuits structure, and frequency detection module has a register, is used to be provided with the amplitude threshold value of second comparer; Wherein:

Described edge sense circuit comprises peak detection circuit, third integral device and the 3rd totalizer that connects successively; Related peak detecting circuit is a kind of amplitude detection circuit, its input end connects the output terminal of the sampling hold circuit of square wave detecting device, the output terminal of peak detection circuit links to each other with the input end of third integral device, third integral device band integration holding circuit, third integral device output terminal links to each other with the input end of the 3rd totalizer, the output terminal of the 3rd totalizer connects an input end of second comparator circuit, is used to detect the frequency of input sample signal; The reference signal termination of second comparator circuit is gone into the second amplitude threshold setting value; Reset signal inserts the reset terminal or the clear terminal of third integral device, the 3rd totalizer and second comparator circuit; Frequency detection module is used to detect the frequency of input signal, and the number of the hopping edge by detecting sampled signal realizes the frequency detecting to the input sample signal.

The detection window number of the peak detection circuit of frequency detection module is configurable, and system's control SPI interface is connected to the window number end is set, and the detection window number disposes by the value of setting k; The value of the setting k of detection window number is provided with by system's control SPI interface; Frequency detection module is by judging k the detected hopping edge of detection window number 〉=2k-permissible variation value, judges frequency dutycycle correct of input signal, and realization is to the detection of frequency input signal.

Described square wave detecting device, it is that described shake detection module and frequency detection module merge formation shake and frequency detection module; Shake and frequency detection module comprise the shake testing circuit that is made of dither signal detection circuit and reset signal generating circuit, the edge sense circuit that constitutes by the related peak detecting circuit, third integral device and the 3rd totalizer that connect successively, and second comparator circuit; Wherein:

Described dither signal detection circuit is made of the related peak detecting circuit, the 4th integrator and the 4th totalizer that connect successively; The output terminal of sampling hold circuit links to each other with the dither signal detection circuit input end, dither signal detection circuit is linked to each other with the reset signal generating circuit input end by output terminal, and the output terminal of reset signal generating circuit connects an input end of the second logical comparator circuit of frequency detection module; The reset signal that connects reset signal generating circuit output inserts the reset terminal of the envelope detected circuit in the correlation detection module and the reset terminal or the clear terminal of integration in the frequency detection module and summation circuit respectively;

Described related peak detecting circuit is a kind of amplitude detection circuit, its input end connects the output terminal of the sampling hold circuit of square wave detecting device, the output terminal of related peak detecting circuit links to each other with the input end of third integral device, third integral device band integration holding circuit, the integration holding circuit output terminal links to each other with the input end of the 3rd totalizer, the output terminal of the 3rd totalizer connects an input end of second comparator circuit, is used to detect the frequency of input sample signal; The reference signal termination of second comparator circuit is gone into the second amplitude threshold setting value; Reset signal inserts the reset terminal or the clear terminal of third integral device, the 3rd totalizer and second comparator circuit; Frequency detection module is used to detect the frequency of input signal, and the number of the hopping edge by detecting sampled signal realizes the frequency detecting to the input sample signal.

Shake and frequency detection module are used to detect the sampled signal dutycycle, whether respectively contain M/2 sampled point by detecting sampled signal high level and low level, thereby whether the dutycycle of judging input signal is 50%, realization judges to the detection of the dutycycle of input sample signal whether the frequency dutycycle of input signal is correct.

Described square wave detecting device, it is that described correlation detection module, frequency detection module and shake detection module also comprise a register separately: be respectively first register, second register and the 3rd register; Corresponding three fields that connect the register controlled word of upper system of the data input pin of three registers: wherein:

The data input pin of described first register connects first field of the register controlled word of upper system, the initial value that is used for configure amplitude threshold T H_MAG, the data output end of first register connects the first comparator circuit reference signal end, and the first amplitude threshold setting value is provided;

The data input pin of described second register connects second field of the register controlled word of upper system, the initial value that is used for configuration frequency comparison threshold value TH_FREQ, the data output end of second register connects the second comparator circuit reference signal end, and the second amplitude threshold setting value is provided;

The data input pin of described the 3rd register connects the 3rd field of the register controlled word of upper system, be used to dispose the initial value of shake comparison threshold value TH_ JITTER, the data output end of the 3rd register connects the 3rd comparator circuit reference signal end, and the shake comparison threshold value of setting is provided.

Described square wave detecting device, it is that described shake detection module path comprises sampling hold circuit and shake detection module;

The shake detection module comprises dither signal detection circuit and reset signal generating circuit; Dither signal detection circuit is made of the related peak detecting circuit, the 4th integrator and the 4th totalizer that connect successively, is used to detect the dutycycle of input sample signal; The output terminal of sampling hold circuit links to each other with the dither signal detection circuit input end, dither signal detection circuit is linked to each other with the reset signal generating circuit input end by output terminal, and the output terminal of the reset signal generating circuit of shake detection module directly connects an input end of the AND circuit of square wave detecting device; The reset signal of reset signal generating circuit output inserts the reset terminal of the envelope detected circuit in the correlation detection module and the reset terminal or the clear terminal of integration in the frequency detection module and summation circuit respectively.

Described square wave detecting device, it is that described shake and frequency detection module also comprise second register and the 3rd register, wherein:

Show that by test result the wakeup time of square wave detecting device is 640us～850us, be better than the wakeup time of existing wake-up circuit the emulation experiment of the square wave detecting device of 14kHz intermediate frequency input signal.

Described square wave detecting device, it is the wake-up signal end of wireless transceiver circuit of the output terminal connecting band wireless awakening circuit of described square wave detecting device; Be used in frequency detection module, the output terminal of shake detection module and correlation detection module all is a high level, and when the AND circuit output terminal of square wave detecting device was high level, the wake-up signal of output high level was realized waking up wireless transceiver circuit.

Described square wave detecting device, it also is the signal sample circuit of described square wave detecting device, and the correlation detection module of square wave testing circuit, shake detection module and frequency detection module, perhaps above-mentioned shake detection module and frequency detection module merge shake and the frequency detection module that constitutes, and AND circuit, adopt CMOS technology to be integrated in the chip, the chip-scale circuit is based on the Digital Analog Hybrid Circuits structure; Adopt the Digital Analog Hybrid Circuits structure to be used to improve the reliability height of square wave detecting device, thereby satisfy the high reliability request of wireless awakening circuit;

The circuit of first totalizer, second totalizer and the 3rd totalizer in the described chip constitutes identical, all comprise three delay circuits and a totalizer, a totalizer is the time diversity totalizer, the time diversity number of times is 3, the range signal diversity that is used for finishing by the two-stage delay circuit testing result of three sense cycle adds up, and the output wake-up signal of a sense cycle and zero clearing or reset, significantly improve and wake probability up, reduce the false wake-up probability.

The local oscillator square-wave cycle is respective settings with input intermediate-freuqncy signal frequency, detection window number k is directly related with the delay time of the delay circuit of totalizer again, the time diversity number of times is 3, detection window number k value be set be 6,9,12,15(k is 3 multiple), one detection period is a k/3 local oscillator square-wave cycle.If it is 9 that the k value is set, one detection period is 3 local oscillator square-wave cycle; If k is 12, then one detection period is 4 local square-wave cycle; The delay circuit of totalizer is configurable delay circuit, and the delay time of digital delay circuit is synchronized with the setting of local oscillator square-wave cycle, and corresponding adjustment delay time is an one detection period;

The shake testing circuit is the distortion of fast detecting input intermediate-freuqncy signal in one detection period, when bigger distortion takes place in input signal, the deviate of shake testing circuit detected high level number of transitions in one detection period is greater than permissible value, output jitter reset signal immediately, totalizer intermission diversity is added up, re-execute and newly once wake detection up, be beneficial to effectively shorten wakeup time.

With N=14 is example, and input signal 14kHz enters three detection module paths respectively through the sampled output signal of sampling of 112kHz local oscillator and maintenance:

Shake detection module, be used to detect the dutycycle of input signal, for the sampled signal of 112kHz, high level and low level should respectively have four sampled points in a kind of cycle of input signal, if deviation is excessive, think that then signal is not correct input signal, produce shake (Jitter) and reset;

Whether frequency detection module is used to detect the frequency of input signal, be 18 to judge whether the frequency of input signal is correct according to 9 the detected hopping edge of detection window signals;

The correlation detection module is used for the correlativity of comprehensive detection signal, and actual is amplitude detection to the input signal dutycycle, and it is different from shake detects, and amplitude detection is the amplitude mean value at whole detection window;

Have only each detection module testing result to meet the demands, this circuit just can be exported high level, drives late-class circuit work.

The present invention can reduce the false wake-up probability that wakes receiver up effectively, improves and wakes probability up, reduces wakeup time, wakes efficient up thereby improve, and reduces the useless power consumption of false wake-up, reduces system power dissipation.

Substantial effect of the present invention:

1, the present invention uses correlation detection to come comprehensive detection dutycycle and frequency, has improved the false wake-up probability that detects.

2, frequency detecting and shake detection, correlation detection are combined by handling with door, improved the accuracy that detects, reduced the probability of false wake-up.

3 adopt correlativity, shake and three detection module paths of frequency to realize the processing of sampled signal comprehensive detection, and treatment effect is optimized, and saves the processing time, has improved and has waken efficient up, has shortened wakeup time.

4, the module of square wave detecting device of the present invention and circuit are integrated in same chip, and no peripheral circuit based on Digital Analog Hybrid Circuits, satisfies the high reliability of wireless awakening circuit and the requirement of low-power consumption on the chip.

Description of drawings

Wake the schematic block circuit diagram of receiver in the system of Fig. 1 for the electronic charging system without parking ETC of 5.8GHz up;

Among Fig. 1: 11-receiver, 12-square wave detecting device waken up.

Fig. 2 is the circuit principle of compositionality block diagram of square wave detecting device in the RFID wireless awakening circuit;

Among Fig. 2: 21-sample circuit, 22-square wave testing circuit, 221-shake detection module, 222-frequency detection module, 223-correlation detection module, 224-AND circuit.

Fig. 3 a is the structured flowchart that is applied to the first embodiment of the invention 14kHz square wave testing circuit in the ETC system;

Among Fig. 3 a: 3a-square wave testing circuit, 31-sample circuit, 32-in closing property detection module, 321-correlation detection circuit, 322-envelope detected circuit, 323-the first comparator circuit, 33-shake detection module, 34-AND circuit, 35-frequency detection module, 351-edge sense circuit, 352-the second comparator circuit, the intermediate-freuqncy signal of 301-input, the clock signal of 302-input, the power-on reset signal of 303-input, the reset signal of 304-input, 305-register controlled word, the first amplitude threshold setting value of 306-input, the second amplitude threshold setting value of 307-input, the wake-up signal of 308-output.

Fig. 3 b is the structured flowchart that is applied to the second embodiment of the invention 14kHz square wave testing circuit in the ETC system;

Among Fig. 3 b: 36-shake and frequency detection module.

Fig. 4 constitutes block diagram for the correlation detection modular circuit;

Among Fig. 4: 41-related operation circuit, 411,412-related operation frequency mixer, 413-numerically-controlled oscillator, 42,43-integration and summation circuit, 421-first integrator, 431-second integral device, 422-the first totalizer, 432-the second totalizer, 322-envelope detected circuit, 323-the first comparator circuit, 34-AND circuit.

Fig. 5 constitutes block diagram for frequency detection module circuit of the present invention;

Among Fig. 5: 362-edge sense circuit, 51-related peak detecting circuit, 52-third integral device, 53-the three totalizer.

Fig. 6 a is that a kind of shake detection module circuit of first embodiment of the invention square wave testing circuit constitutes block diagram;

Fig. 6 b is a kind of formation block diagram of shaking testing circuit in the shake of second embodiment of the invention square wave testing circuit and the frequency detection module;

Among Fig. 6 a and Fig. 6 b: 61-dither signal detection circuit, 611-related peak detecting circuit, 612-integration and totalizer, 613-shake comparer, 62-reset signal generating circuit.

Fig. 7 is that embodiment of the invention square wave detecting device on-chip circuit constitutes block diagram;

Among Fig. 7: 71-sample circuit, 72-correlation detection module, 720-digital oscillator, 721,722-related operation frequency mixer, 723-first integrator, 724-second integral device, 725-the first totalizer, 726-the second totalizer, 727-envelope detected circuit, 728-the first comparator circuit, 73-shake and frequency detection module, 731-shake testing circuit, 732-peak detection circuit, 733-third integral device, 734-the three totalizer, 735-the second comparator circuit, 74-AND circuit, 741-holding circuit.

Embodiment

Fig. 1 provides the schematic block circuit diagram of waking receiver in the ETC electronic charging system without parking of 5.8GHz up, and the wake-up signal that wakes receiver 11 up is to be provided by a square wave detecting device 12.The output terminal of square wave detecting device connects the input end that wakes up that wakes receiver up as the output terminal of the enable signal that wakes up, when the vehicle with ETC electronics message accounting does not stop when normally sailing into, wake-up signal of square wave detecting device output is given the ETC chip, realization wakes the ETC(electronic charging system without parking up) the chip operation purpose, be used for the ETC of charge station electronics message accounting from vehicle ETC chip withholding expense.But there are defectives such as peripheral circuit complex structure and measuring ability are single in the square wave detecting device of prior art, causes the false wake-up probability that detects higher, and wakeup time is longer, and it is lower to wake efficient up, and directly influence efficiently wakes the realization with the energy-conservation purpose of low-power consumption up.

Below in conjunction with drawings and Examples technical scheme of the present invention is described further.

Fig. 2 is used for the square wave detecting device of RFID wireless awakening circuit for the present invention the three module path of a kind of embodiment constitutes block diagram, and as shown in Figure 2, the circuit of square wave testing circuit constitutes block diagram and comprises sample circuit 21 and the square wave testing circuit 22 that is connected in series.Square wave testing circuit 22 comprises shake detection module 221, frequency detection module 222 and correlation detection module 223 and AND circuit 224, the be connected in parallel output terminal of sample circuit 21 of the input end of shake detection module 221, frequency detection module 222 and correlation detection module 223.The output terminal of shake detection module 221, frequency detection module 222 and correlation detection module 223 is connected an input end of AND circuit 224 respectively.Shake detection module 221, frequency detection module 222 and correlation detection module 223 constitute shake detection module path, frequency detection module path and correlation detection module path with sample circuit 21 respectively.The input end of sample circuit 21 inserts intermediate-freuqncy signal, the output terminal output wake-up signal of gate circuit 224.

First embodiment

Fig. 3 a provides the structured flowchart that the first embodiment of the invention N that is applied in the ETC system is 14 14kHz square wave detecting device, shown in Fig. 3 a: square wave detecting device 3a comprises sample circuit 31, correlation detection mould 32, shake detection module 33, frequency detection module 35 and AND circuit 34.Correlation detection module 32 comprises the correlation detection circuit 321 that is connected in series successively, the envelope detected circuit 322 and first comparator circuit 323.Frequency detection module 35 comprises edge sense circuit 351, and second comparator circuit 352.The output terminal of second comparator circuit 352 of shake detection module 33 output terminals and frequency detection module 35 is connected an input end of AND circuit respectively, the output terminal of first comparator circuit 323 of correlation detection module 32 also connects an input end of AND circuit 34, and the output terminal of AND circuit 34 transfers out the receiving circuit that wakes up that wake-up signal 307 is delivered to radio-frequency (RF) identification (RFID) system.The shake reset signal of shake detection module 33 output is connected to the reset terminal of envelope detected circuit 322 of correlation detection module 32 and the reset terminal of edge sense circuit 332 simultaneously.The intermediate-freuqncy signal 301 of input inserts the input end of sample circuit 31, the input end of the correlation detection circuit 321 shake detection modules 33 of the output terminal connection square wave testing circuit of sample circuit 31 and the edge sense circuit 351 of frequency detection module 35, the clock signal 302 of input is as the reference clock signal of square wave detecting device 3a.Power-on reset signal 303 RSTN of system input, the resetting of control sample circuit 31, correlation detection mould 32, shake detection module 33 and frequency detection module 35 is for the square wave detecting device provides start-up time after resetting.The reset signal CLEAR 304 that imports when system is added to the square wave detecting device, then the register zero clearing of system's control square wave detecting device.Simultaneity factor input register control word SETTING, the register controlled word 305 " SETTING " of 18 bit wides are provided with initial value for three registers in correlation detection module 32, frequency detection module 35 and the shake detection module.The first amplitude threshold setting value TH_MAG 306 of first register inserts the reference value input end of first comparator circuit 323 of correlation detection mould 32, the output terminal of envelope detected circuit 322 connects the signal value input end of first comparator circuit 323, the comparative result of first comparator circuit, 323 outputs.The second amplitude threshold setting value 307 of second register inserts the reference value input end of second comparator circuit 333 of frequency detection module 36; The shake threshold setting value TH_JITTER of the 3rd register output inserts the shake detection comparator reference edge of shake detection module 33, determines whether to control whether output jitter reset signal of reset signal generating circuit after being used for relatively.The output terminal of the output terminal of edge sense circuit 351 and shake detection module 33 connects a signal input part of second comparator circuit 352 respectively, second comparator circuit, 352 output comparative results.Intermediate-freuqncy signal IFDATA 301 inserts the input end of sampling hold circuit 31, and the output terminal of sampling hold circuit 31 links to each other with the input end of correlation detection module 32 paths, shake detection module 33 paths, frequency detection module 35 paths respectively through three the tunnel.The comparative result of the comparative result of first comparator circuit, 323 outputs and 352 outputs of second comparator circuit is added to an input end of AND circuit 34 respectively.When the shake reset signal of the comparative result of the comparative result of first comparator circuit 323 output and 352 outputs of second comparator circuit and 33 outputs of shake detection module all be high level, AND circuit 34 was exported the wake-up signal " WAKEUP " 308 of a high level.Otherwise AND circuit 34 is output as low level, does not export wake-up signal.

Second embodiment

Fig. 3 b is applied to the structured flowchart that second embodiment of the invention N in the ETC system is 14 14kHz square wave detecting device.Shown in Fig. 3 b: the square wave detecting device comprises sample circuit 31, correlation detection mould 32, and by the shake and the frequency detection module 36 of shake testing circuit and frequency detection circuit combination, and AND circuit 34.Correlation detection module 32 comprises the correlation detection circuit 321 that is connected in series successively, the envelope detected circuit 322 and first comparator circuit 323.Shake detection module and frequency detection module are combined as a shake and frequency detection module 36, and it comprises shake testing circuit 361, edge sense circuit 362, and second comparator circuit 363.The output terminal of shake testing circuit 361 and edge sense circuit 362 is connected an input end of second comparator circuit 363 separately, and the shake reset signal of shake testing circuit 361 outputs is connected to the reset terminal of envelope detected circuit 362 of correlation detection module 32 and the reset terminal of edge sense circuit 362 simultaneously.The output terminal of second comparator circuit 363 of the output terminal of first comparator circuit 323 of correlation detection module 32 and shake and frequency detection module 36 is connected an input end of AND circuit 34 separately, and the output terminal of AND circuit 34 transfers out wake-up signal 308.The intermediate-freuqncy signal 301 of input inserts the input end of sample circuit 31, the output terminal of sample circuit 31 inserts the correlation detection circuit 321 of square wave testing circuit and the input end of shake testing circuit 361 and edge sense circuit 362 simultaneously, the clock signal 302 of input is as the reference clock signal of square wave detecting device 3b, the power-on reset signal 303 control sample circuits 31 of input, correlation detection mould 32 and shake and frequency detection module 33 reset, and be provided the start-up time after resetting.Reset signal when input " CLEAR " 304 be added to the square wave detecting device, the then register initial value CLEAR zero clearing of system's control square wave detecting device.When system gives related register by register controlled word " SETTING " 305 assignment, register controlled word " SETTING " 305 is provided with initial value to the register in correlation detection module 32 in the square wave detecting device and shake and the frequency detection module 36, the first amplitude threshold setting value TH_MAG 306 of first register inserts the reference value input end of first comparator circuit 323 of correlation detection mould 32, the output terminal of envelope detected circuit 322 connects the signal value input end of first comparator circuit 323, the comparative result of first comparator circuit, 323 outputs.The second amplitude threshold setting value 307 of second register inserts the reference value input end of second comparator circuit 363 of shake and frequency detection module 36, the output terminal of edge sense circuit 362 connects the signal value input end of second comparator circuit 363, second comparator circuit, 363 output comparative results.The shake threshold setting value TH_JITTER of the 3rd register output inserts shake and frequency detection module 36 shake testing circuit comparator reference ends, after comparing, determines whether to control whether output jitter reset signal of reset signal generating circuit.The comparative result of the comparative result of first comparator circuit, 323 outputs and 363 outputs of second comparator circuit is added to an input end of AND circuit 34 respectively.When the comparative result of the first amplitude threshold setting value of the comparative result of first comparator circuit 323 output and input and 363 outputs of second comparator circuit all was high level with the second amplitude threshold setting value of input, AND circuit 34 was exported the wake-up signal 307 of a high level.Otherwise AND circuit 34 is output as low level, does not export wake-up signal.

The 3rd embodiment

The circuit principle of compositionality block diagram of correlation detection module as shown in Figure 4.The correlation detection module is by computing cross-correlation frequency mixer 411,412, digital oscillator 413, and the integration of two-way simple crosscorrelation and summation circuit 42,43, the envelope detected circuit 322 and first comparator circuit 323 constitute.Integration and summation circuit 42 comprise the first integrator circuit 421 and first accumulator circuit 422 that is connected in series; Integration and summation circuit 43 comprise the second integral device circuit 431 and second accumulator circuit 432 that is connected in series; The output terminal of second integral device circuit 431 is added to the input end of first integrator circuit 421.The circuit of correlation detection module path connects as follows: No. two frequency mixer 411 of the output terminal of digital oscillator 413 and computing cross-correlation link to each other with 412 local oscillation signal input end, No. two frequency mixer 411 of computing cross-correlation and 412 output terminal link to each other with the input end of the integrator circuit 431 of the input end of the integrator circuit 421 of integration and summation circuit 42 and integration and summation circuit 43 separately, the output terminal of integrator circuit 421 of integration and summation circuit 42 and linking to each other of first accumulator circuit 422, the output terminal of integrator circuit 431 of integration and summation circuit 43 and linking to each other of first accumulator circuit 432, the output terminal of first totalizer 422 and second totalizer 432 links to each other with an input end of envelope detected circuit 322 separately, the output terminal of envelope detected circuit 322 links to each other with the input end of first comparer 323, and 34 1 input ends of AND circuit of square wave detecting device are delivered in the output of first comparer 323.

The course of work of correlation detection module: under the reset signal effect, envelope detected circuit 322 resets, and the start time that the correlation detection module is determined according to clock signal starts working.The sampled signal of sampling hold circuit output arrives No. two frequency mixer 411 of computing cross-correlation and 412 signal input part simultaneously, the local oscillation signal of sampled signal and digital oscillator output is made computing cross-correlation in No. two frequency mixer 411 and 412, the output signal of No. one frequency mixer 412 send second totalizer 432 to make accumulation process behind second integral device 431 integrations, the integrated signal of the output signal of another road frequency mixer 411 and 431 outputs of second integral device send first totalizer 422 to make accumulation process through first integrator 421 integrations.After the cumulative signal of the cumulative signal of first totalizer 422 output and 432 outputs of second totalizer is delivered to envelope detected circuit 322 respectively and is carried out envelope detected, the output signal of envelope detected circuit 322 is delivered to an input end of first comparator circuit 323, value with first register of determining by the register controlled word, this value is added in the reference signal end of first comparator circuit as the first amplitude threshold setting value, make comparisons through first comparator circuit, if the output signal of envelope detected circuit 322 is within the first amplitude threshold setting value, comparative result is output as high level, otherwise comparative result is output as low level.

The 4th embodiment

The embodiment of the invention provides the frequency detection module circuit and constitutes block diagram, as shown in Figure 5.Frequency detection module is made of the edge sense circuit 332 and second comparator circuit 303, and edge sense circuit 332 comprises the related peak detecting circuit 51 that is connected in series successively, third integral device 52 and the 3rd totalizer 53.The sampled signal of sample circuit 31 outputs is delivered to the input end of related peak detecting circuit 51, the output terminal of the 3rd totalizer 53 is delivered to an input end of second comparator circuit 303, reset signal inserts the RESET input of third integral device 52 and the 3rd totalizer 53, and reset signal also inserts another input end of second comparator circuit 303.Described reset signal comprises from the power-on reset signal outside the sheet with from the reset signal of shaking testing circuit output in the sheet.Frequency detection module is by comprising that the edge sense circuit 362 and second comparator circuit 303 of related peak detecting circuit 51, third integral device 52 and the 3rd totalizer 53 of series connection constitute successively.The circuit of frequency detection module path connects as follows, the output terminal of sampling hold circuit links to each other with the input end of the related peak detecting circuit 51 of edge sense circuit 362, the output terminal of edge sense circuit 362 third integral device circuit 53 links to each other with the input end of second comparer 303, and an input end of the output terminal AND circuit of second comparer 303 links to each other.The output terminal of AND circuit produces circuit with wake-up signal and links to each other, and the output terminal of wake-up signal generation circuit links to each other with wireless transceiver circuit to be waken up.

Under the reset signal effect, frequency detection module enters testing: the input end that the sampled signal of sampling hold circuit 31 outputs enters the related peak detecting circuit 51 of edge sense circuit 362 carries out the sampled point detection, the sampled point detection signal is outputed to third integral device circuit 52 integrations, after the Integral Processing, third integral device circuit 52 integral results send the 3rd totalizer 53 to finish the sampling number accumulation process of sense cycle for the first time; Enter sense cycle for the second time, equally for the second time the sampling number accumulation process in the sense cycle; Integral result by third integral device circuit 52 send 53 pairs of sampling numbers of the 3rd totalizer to continue to add up, up to entering sense cycle for the third time, sampling number accumulation process in the sense cycle is finished adding up of three detected sampling numbers of sense cycle time diversity equally for the third time; Again through the processing of a sense cycle time, by the 3rd accumulator circuit 52 diversity is detected the sampling number result who adds up and send into second comparator circuit 303, compare judgement with the second amplitude threshold setting value that is added in second comparator circuit, 303 reference signal ends, improved the judgement precision, judged that signal output is sent to the input end of AND circuit.

A kind of shake detection module circuit of the square wave testing circuit of first embodiment of the invention constitutes block diagram shown in Fig. 6 a, the another kind shake detection module circuit of the square wave testing circuit of second embodiment of the invention constitutes block diagram shown in Fig. 6 b, and it is 8 that embodiment is provided with M.

Shake detection module 33 is made of dither signal detection circuit 61 and reset signal generating circuit 62.Dither signal detection circuit 61 comprises related peak detecting circuit 611, integration and totalizer 612 and the shake comparer 613 that is connected in series, and the reference signal termination of shake comparer 613 goes into to shake the initial value of comparison threshold.The output terminal of sampling hold circuit links to each other with the input end of dither signal detection circuit 61, the output terminal of dither signal detection circuit 61 links to each other with the input end of reset signal generating circuit 62, the output terminal of reset signal generating circuit 62 respectively with the reset terminal of delivering to two road integrator circuits in the correlation detection module and frequency detection module in the input end of integrator circuit.

Under the reset signal effect, the shake detection module enters testing, the sampled signal of sampling hold circuit output enters the input end of related peak detecting circuit 611, the sampled signal dutycycle is carried out mutually and computing with the local oscillation signal of 50% 8NkHz, the output signal of related peak detecting circuit 611 is made integration and accumulation process through integration and totalizer 612, in a sense cycle, the sampled point of sampled signal is added up, the value of setting of the statistics of the sampled point of sampled signal being delivered to shake comparer 613 and shake comparison threshold in sense cycle of the output of integration and totalizer 612 compares, if the deviate of sampled point statistical number is greater than shake comparison threshold value, then shaking comparer 613 gives reset signal generating circuit 62 output high level, the shake reset signal of reset signal generating circuit 62 outputs, be added to AND circuit 34, make AND circuit 34 be in low level, shake reset signal simultaneously and deliver to correlation detection module and frequency detection module, each module is resetted.

A kind of formation block diagram of testing circuit of shaking is shown in Fig. 6 b in the shake of square wave testing circuit and the frequency detection module.Shaking testing circuit among the formation of shake testing circuit and Fig. 6 a among Fig. 6 b constitutes basic identical, difference is that the output terminal of the former reset signal generating circuit directly connects AND circuit 34, and the output terminal of the latter's reset signal generating circuit connects an input end of second comparator circuit 303, delivers to gate circuit 34 again after second comparator circuit, 303 comparison process.

The dynamic duty process of embodiment that the present invention is applied to the square wave detecting device of wireless awakening circuit is described in detail as follows:

Be used for the wireless awakening circuit the square wave detecting device the embodiment chip interface configuration as shown in Table 1, in the table one: the register controlled word SETTING of 18 bit wides carries out the initial value configuration to three registers, and the bit wide that first register, second register and the 3rd register account for register controlled word SETTING is respectively 8,5 and 3.The register initial value configuration of square wave detecting device as shown in Table 2.

The basic design of technical solution of the present invention is to utilize Digital Analog Hybrid Circuits the square wave of input intermediate-freuqncy signal to be provided the Characteristics Detection of frequency, dutycycle; shake detection, frequency detecting, correlation detection are integrated; improve the accuracy rate of input; wake the efficient of waking up that receiver wakes late-class circuit up up thereby provide, reduce the false wake-up rate.All DLC (digital logic circuit) adopt CMOS technology to be integrated in the chip and realize.

Shake detection module path, the circuit of this shake detection module 33 constitutes related peak detecting circuit and reset signal generating circuit that a digital-to-analogue is mixed, and the output terminal of peak detection circuit links to each other with the input end of reset generation circuit.Setting N is 14, and M is that 8,14 kHz intermediate-freuqncy signals enter into a related peak detecting circuit through behind the sampling hold circuit, in the peak detection circuit 14 kHz and dutycycle be 50% 112 kHz local oscillation signal with.In one-period, the high level of local oscillation signal and low level place can produce 4 sampled points respectively, and 8 sampled points are arranged altogether.

Signal just often, input signal is the square wave of 14kHz, dutycycle is 50%.When the frequency of sampling clock is 112kHz, the related peak detecting circuit of shake detection module detects the high level of square wave and 4 sampled points that low level all comprises time detecting, related peak detecting circuit is output as low level so, and reset generation circuit is not just exported reset signal.When if signal is undesired, related peak detecting circuit detects the high level of square wave and the sampling number of low level time detection is less than the shake comparison threshold TH_JITTER initial value that the 3rd register is provided with, just be output as high level, reset generation circuit can produce reset signal.This reset generation circuit is made up of an automatically reset inner accumulator register and a data chainning, the output terminal of this reset circuit respectively with the correlation detection module in input end and the frequency detection module of integrator circuit in the input end of integrator circuit link to each other.By inner accumulator register and the data of automatically reseting, can make testing circuit can't export high level.

Shake (Jitter) detection threshold TH_JITTER can dispose, if allow the error 2 of a sampled point, promptly shaking detection threshold default value (M-2) is 6.If the M value of setting is 16, allow the error 2 of a sampled point, shake detection threshold default value (M-2) is 14, revises the value of Jitter detection threshold TH_JITTER, can optimize square wave and detect performance by the emulation experiment choose reasonable M value of setting.

Frequency detection module path, this module 36 are the frequency detection circuit that a digital-to-analogue is mixed.14 kHz intermediate-freuqncy signals 301 enter into an edge sense circuit 332 through behind the sampling hold circuit 31, whether edge sense circuit 332 changes to judge whether input signal saltus step takes place according to previous clock and present clock signal level, thereby detects the edge of input signal.If the generation saltus step, high level of edge sense circuit output, thinking has a sampled point.The output terminal of edge sense circuit links to each other with the input end of third integral device, if the reset signal generating circuit in the shake detection path 731 does not produce reset signal, the high level of input third integral device is counted one by one through 733 pairs of sampled points of third integral device, being sent to totalizer 3 when first sense cycle finishes adds up, through the time of a sense cycle of delay circuit 7 time-delays, the third integral device is delivered to totalizer 3 to the sampled point count value again and is added up when second sense cycle finishes, equally, through the time of a sense cycle of delay circuit 8 time-delays, when the 3rd sense cycle finishes, the third integral device is delivered to totalizer 3 to the sampled point count value again and is added up, through three sampled point numbers add up with keep after, in the time of a sense cycle of delay circuit 8 time-delays, when the 4th sense cycle finishes, the sampled point number that three time diversities are added up is sent in second comparator circuit 735, compares with the second amplitude threshold setting value of definite frequency detecting permissible variation.If comparative result then can be exported high level for satisfying comparison condition, be sent to the AND circuit 74 of back one-level.The frequency detecting path is by sampled signal is judged the correctness that frequency input signal detects at the number or the title sampling number at the saltus step edge of certain hour in the cycle, in theory, if the detection window number is set to 9, so total saltus step edge number should be 18, if is 18 with frequency ratio than threshold setting, detect the sampled point of 18 high level at totalizer 3, compare than the threshold setting value with frequency ratio at second comparator circuit 735, be judged to be normally, second comparator circuit, 735 output high level are to the AND circuit 74 of back one-level.If totalizer 3 detected sampled point numbers and frequency ratio are compared than the threshold setting value, less than 18, think then that frequency input signal is undesired as the output valve of totalizer 3, second comparator circuit, 735 output low levels are to the back AND circuit of one-level.In fact input signal is faint and be subject to disturb, the sampled point number accumulated value that the totalizer 3 of edge sense circuit occurs is lower than frequency ratio than the threshold setting value, usually allow deviation value according to the experience configuration, by the value of setting of the comparison threshold of adjusting frequency, the optimization that realizes improving the speed of waking up and reduce false wake-up probability two aspects.

Correlation detection path, correlation detection are called amplitude detection again, and reality also is the detection to the input signal dutycycle, and different with the shake detection is that amplitude detection is the mean value to whole detection window.This path is by forming through the Digital Analog Hybrid Circuits that comprehensively constitutes.The intermediate frequency input signal is sent in the two-way related operation circuit after the sampling hold circuit sampling, the related operation circuit is a digital mixer, input intermediate-freuqncy signal orthogonal signal (square wave) identical with the input intermediate-freuqncy signal with the cycle of two-way in two-way related operation circuit are made related operation, and the two-way orthogonal signal are produced by the numerically controlled oscillator of built-in chip type.The output signal of two-way related operation circuit enters respectively by an integrator circuit and an integration and the summation circuit that accumulator circuit is formed, earlier make Integral Processing by integrator, and then send into totalizer and make accumulation process, integration is connected the input end of an envelope detector with the summation circuit output terminal, the output terminal of envelope detector connects the first comparator circuit input end, the comparison of in first comparer output signal and the first amplitude threshold setting value of envelope detector being made correlation detection judges whether signal is correct.The first amplitude threshold value of correlation detection can dispose by upper computer software.The default value of the first amplitude threshold value is 40, and is relevant with the size of detection window.In the square wave detecting device of first embodiment of the invention: sample frequency FS is 112KHz, and input intermediate-freuqncy signal frequency FIN is 14KHz, and the size of detection window is 9 cycle FIN.

Fig. 7 provides embodiment of the invention square wave detecting device on-chip circuit and constitutes block diagram; Initial value allocation list below in conjunction with shown in chip interface table shown in Fig. 7 and the table one and the table two is described in detail as follows square wave detecting device dynamic duty process:

1, for it initial value of following respectively value of setting is set by square wave detecting device place system

1) the window number value of setting k, by the control PRD of the system realization configuration of the outer input of sheet, acquiescence k initial value is 9;

2) the amplitude comparison threshold value of setting TH_MAG realizes configuration by the register controlled word of the outer input of sheet, and acquiescence TH_MAG initial value is 40, and relevant with the size of detection window, the right-on envelope detection output amplitude of correlation detection value is 50.It is 14KHz that embodiment sets input intermediate-freuqncy signal frequency FIN, and sample frequency FS is 112KHz, and the detection window time is 9 FIN frequency square-wave cycle.

3) frequency ratio realizes configuration than threshold setting value TH_FREQ by the register controlled word of the outer input of sheet, and acquiescence TH_FREQ initial value is 3;

4) the shake comparison threshold value of setting TH_JITTER, by the real configuration of the register controlled word of the outer input of sheet, acquiescence TH_JITTER initial value is 2;

2, electrification reset: 14kHz intermediate-freuqncy signal IFDATA, delivers to correlation detection module, shake detection module and frequency detection module three tunnel module paths then respectively and detects through the sampling clock sampling of 112k from 701 interface input sampling circuits 71.The frequency FIN of input intermediate-freuqncy signal is made as 14kHz, and the frequency FS of sampling clock is made as 112 kHz, and this locality of digital oscillator 720 outputs also is FIN=14kHz with reference to the frequency of square wave.

1) the correlation detection module channels course of work:

It is 9 that the window number is provided with initial value k, and the relevant diversity number of times of setting-up time is 3.Digital oscillator 720 output local oscillator square waves, be 9/3 FIN frequency local oscillator square-wave cycle the integral time of first integrator 723 and second integral device 724, the time of total detection window equals 3*9/3=9 FIN frequency local oscillator square-wave cycle.The cycle of local oscillator square wave that corresponding to FIN is the intermediate-freuqncy signal of 14kHz is 71us, one detection period and an integral time are 213us so, the time of total detection window equals 639us, and the quiescent interval after three times diversity detects is that one detection period is 213us.When input 14k square-wave signal, the time interval that detects this signal is 639us, adds that the intermittent phase is 852us, so wakeup time is 639us～852us.

The correlation detection of the correlation detection module correlativity amplitude detection that is otherwise known as, it is the detection to the mean value of whole detection window to the detection of if sampling input signal dutycycle.The if sampling signal through a pair of based on digital mixer 721 and 722 and the quadrature related operation processing of circuit of digital oscillator 720, digital mixer 721 is delivered to reference to the square wave cosine signal in this locality of digital mixer 721 outputs, and digital mixer 722 is delivered to reference to the sinusoidal signal of square wave in this locality of digital mixer 721 outputs.The cosine and the sinusoidal local oscillation signal of digital mixer 721 and 722 outputs, the corresponding separately input end of delivering to first integrator 723 and second integral device 724, simultaneously second integral device 724 outputs to first integrator 723, participate in the integration of first integrator 723, be used to finish cosine and sinusoidal local oscillation signal.The integral output signal of first integrator 723 and second integral device 724, the delay circuit of respectively hanging oneself are delivered to first totalizer 725 and second totalizer, 726 input ends.The totalizer that first totalizer 725 and second totalizer 726 are deposited for the band time-delay, be used for by time-delay, the time diversity of finishing three integral time detects, improve correct detection probability, and with an integral time as resetting and the stand-by period, make correlation detection path and frequency detecting path be input to the AND circuit input end to separately testing result synchronously, if success of one-time detection enters after resetting next time and detects.The integral output signal correspondence of first integrator 723 and second integral device 724 delivers to first totalizer 725 and second totalizer 726 is made accumulation process, first totalizer 725 is the Cos phase accumulator, second totalizer 726 is the Sin phase accumulator, first totalizer 725 of two-way quadrature channel and the output signal of second totalizer 726, correspondence is through the time-delay of the integral time of delay circuit 727-1 and delay circuit 717-2 separately, again with the corresponding input end importing envelope detector 728 of two paths of signals, envelope detector 728 output correlativity count values are sent into first comparator circuit 729, compare with the initial value 40 that is provided with of the first amplitude threshold value 706, envelope detected range value 〉=40 of correlation detection module, the dutycycle of decision signal and the mean value of frequency are correct, first comparator circuit 729 is output as high level, otherwise envelope detected range value＜40, the first comparator circuits 729 are output as low level.

2) the shake detection module passage course of work: from adopting the if sampling signal of circuit 71 outputs, the input end of input jiffer testing circuit 731, compare with the shake comparison reference by shake testing circuit 731 output sampled point numerical value, the default value of Jitter detection threshold TH_JITTER initial value configuration is 2, promptly allows the detection error of a sampled point.If to count detection time in k detection time clock period be that sampled point in the 213us detects margin of error 〉=2 sampled point setting detection window, judge that immediately shake appears in sampled signal, produce low level Jitter reset signal by reset generation circuit, output Jitter reset signal, make integrator 723,724 relevant in the sheet and 733 and totalizer 725,726 and 734 automatically reset, thereby the AND circuit 74 that makes the square wave testing circuit can't be exported the wake-up signal of high level, starts new one-time detection simultaneously.

3) the frequency detection module passage course of work:

The detection window number of the related peak detecting circuit of edge sense circuit 732 is configurable in shake and the frequency detection module, and the detection window number disposes by the value of setting k, and the value of the setting k of detection window number is provided with by system's control SPI interface.In addition, frequency ratio is that the second amplitude threshold setting value also is configurable than threshold T H_FREQ.The frequency detection module path of shake and frequency detection module 73 is the frequency detection circuit 732 that a digital-to-analogue is mixed.14 kHz intermediate-freuqncy signals 701 enter into an edge sense circuit 732 through behind the sampling hold circuit 71, whether edge sense circuit 732 changes to judge whether the input intermediate-freuqncy signal saltus step takes place according to previous clock and present clock signal level, thereby detects the edge of input intermediate-freuqncy signal.If the generation saltus step, edge sense circuit 732 is output as high level.The input end that the output terminal of edge sense circuit 732 is delivered to third integral device 733 carries out Integral Processing, if the reset signal generating circuit in the shake detection path does not produce reset signal, the high level one by one of 733 pairs of edge testing circuits of third integral device, 73 outputs, integration one by one.The integrated value of third integral device 733 outputs is sent in the 3rd totalizer 734 through time-delay, and the integral output signal of third integral device 733 is delivered to the 3rd totalizer 734 input ends through delay circuit.The totalizer that the 3rd totalizer 734 is also deposited for the band time-delay is used for by time-delay, and the time diversity of finishing three integral time detects, and improves correct detection probability.The output signal of the 3rd totalizer 734 is sent in second comparer 736 after depositing through a time-delay, compares with the second amplitude threshold setting value of definite frequency detecting permissible variation.If signal correctly then can export high level, is sent to the AND circuit 74 of back one-level.The frequency detecting path is a frequency of calculating input signal by the counting input signal at the saltus step edge of certain hour in mid-term.Under the normal condition, be 9 for the detection window number, total saltus step edge number should be 18, should be able to detect 18 high level signals at the input end of accumulator circuit.Be 18 with frequency ratio than threshold setting this moment.The count value and the second amplitude thresholding fiducial value with the totalizer output terminal in second comparer 736 compare.Frequency comparison threshold initial value is 3, promptly allow to occur detecting deviation≤3, if the output valve of the 3rd totalizer 734＞(18-3), when promptly differing big with permission detection deviate, think then not to be normal signal that second comparer, 736 output low levels are to the AND circuit 74 of back one-level.Avoided false wake-up like this, will reduce but wake probability up.In concrete enforcement, the detection saltus step high level number that edge sense circuit 732 can occur can send and depart from permissible value, make the output valve deviation theory value of third integral device 733 and the 3rd totalizer 734 thus, giving tacit consent to configurable permission detection deviation is 5, then the value of setting of frequency comparison threshold TH_FREQ correspondence is 5, as long as the output valve of the 3rd totalizer 734 greater than frequency ratio than threshold value respective value (18-5), with regard to the frequency of judging the input intermediate-freuqncy signal is normal, and second comparer, 736 output high level are to the AND circuit 74 of back one-level.By the value of setting of the comparison threshold of adjusting frequency, the optimization that realizes improving the speed of waking up and reduce false wake-up probability two aspects, realization provides the square wave detecting device that is used for the wireless awakening circuit of low false wake-up, high recall rate.

Finally, three module paths of the correlation detection of square wave detecting device, shake detection and frequency detecting are through the detection of three sense cycle, if the magcmp as a result of correlation detection is a high level, the freqcmp as a result of frequency detecting is a high level, and the shake testing circuit does not produce low level reset signal in each sense cycle, AND circuit is just exported testing result in a processing cycle be the wake-up signal decision of high level, thereby on the corresponding time of output wake-up signal, by its wireless awakening circuit of upper system drive.

Table one

Figure 2012101910984100002DEST_PATH_IMAGE002

Table two

Title	Symbol	Bit wide	Explanation
				PRD	k	3	Detection window number, default value are 9
The amplitude threshold value	TH_MAG	8	Amplitude comparison threshold, default value are 40
				Frequency threshold	TH_FREQ	5	The frequency comparison threshold, the acquiescence deviate is 3
The shake threshold value	TH_JITTER	3	The shake comparison threshold, the acquiescence deviate is 2

Protection scope of the present invention is not limited to embodiments described herein.As long as various variations claims limit and the technical characterictic of the present invention and protection domain determined in, these variations are conspicuous, all utilize example that the present invention conceives all at the row of protection.

Claims

1. square wave detecting device that is used for the wireless awakening circuit is characterized in that the square wave detecting device comprises:

A signal sample circuit, sample frequency is M times of input intermediate-freuqncy signal NkHz, the span of N is 10～200; The square wave that with sample frequency is MNkHz is sampled to the NkHz intermediate-freuqncy signal of input, and the span of M is 4,8,16;

2. square wave detecting device according to claim 1 is characterized in that: shake detection module path, frequency detection module path and correlation detection piece path and the AND circuit of described square wave testing circuit are integrated in same chip, and it constitutes:

The AND circuit of one three input is used to export wake-up signal;

3. square wave detecting device as claimed in claim 2 is characterized in that: described correlation detection module path comprises sampling hold circuit, digital oscillator, a pair of digital mixer, a pair of integration and summation circuit, envelope detected circuit and first comparator circuit; A pair of digital mixer and a pair of integration and summation circuit constitute computing cross-correlation device circuit; The output terminal of sampling hold circuit links to each other with the input end of a pair of digital mixer respectively, the signal end of a pair of digital mixer links to each other with the digital oscillator output terminal respectively, and the output terminal of a pair of digital mixer links to each other with the corresponding first integrator and the input end of second integral device respectively; The output terminal of first integrator connects the input end of first totalizer, and the output terminal of second integral connects the input end of second totalizer; The output terminal of the output terminal of first totalizer and second totalizer is corresponding respectively to link to each other with an input end of envelope detected circuit, is used for the mean value of comprehensive detection input signal dutycycle and frequency; The output terminal of envelope detected circuit links to each other with the input end of first comparator circuit, and the output terminal of first comparer connects an input end of AND circuit.

4. square wave detecting device as claimed in claim 2 is characterized in that: described frequency detection module path comprises sampling hold circuit, and the frequency detection module that is made of an edge sense circuit and second comparator circuit; Frequency detection module is for adopting the structure of Digital Analog Hybrid Circuits, the input end of edge sense circuit connects sampling hold circuit, the output terminal of edge sense circuit connects an input end of second comparator circuit, another input end of second comparator circuit inserts the second amplitude threshold setting value, and the output terminal of second comparator circuit connects an input end of AND circuit; Frequency detection module adopts the Digital Analog Hybrid Circuits structure; Wherein:

Described edge sense circuit comprises peak detection circuit, third integral device and the 3rd totalizer that connects successively; Related peak detecting circuit is a kind of amplitude detection circuit, its input end connects the output terminal of the sampling hold circuit of square wave detecting device, the output terminal of peak detection circuit links to each other with the input end of third integral device, third integral device band integration holding circuit, third integral device output terminal links to each other with the input end of the 3rd totalizer, the output terminal of the 3rd totalizer connects an input end of second comparator circuit, is used to detect the frequency of input sample signal; The reference signal termination of second comparator circuit is gone into the second amplitude threshold setting value; Reset signal inserts the reset terminal or the clear terminal of third integral device, the 3rd totalizer and second comparator circuit; Frequency detection module is used to detect the frequency of input signal, and the number of the hopping edge by detecting sampled signal realizes the frequency detecting to the input sample signal;

5. square wave detecting device as claimed in claim 2 is characterized in that: described shake detection module path comprises sampling hold circuit, and the shake detection module that is made of dither signal detection circuit that is connected in series and reset signal generating circuit;

Described dither signal detection circuit is made of the related peak detecting circuit, the 4th integrator and the 4th totalizer that connect successively, is used to detect the dutycycle of input sample signal; The output terminal of sampling hold circuit links to each other with the dither signal detection circuit input end, and dither signal detection circuit is linked to each other with the reset signal generating circuit input end by output terminal;

The output terminal of described reset signal generating circuit directly connects an input end of the AND circuit of square wave detecting device; The reset signal of reset signal generating circuit output inserts the reset terminal of the envelope detected circuit in the correlation detection module and the reset terminal or the clear terminal of integration in the frequency detection module and summation circuit respectively.

6. square wave detecting device as claimed in claim 2, its feature also is: described shake detection module and frequency detection module merge to constitute shakes and frequency detection module; Shake and frequency detection module comprise the shake testing circuit that is made of dither signal detection circuit and reset signal generating circuit, the edge sense circuit that constitutes by the related peak detecting circuit, third integral device and the 3rd totalizer that connect successively, and second comparator circuit; Wherein

Described dither signal detection circuit is made of the related peak detecting circuit, the 4th integrator and the 4th totalizer that connect successively; The output terminal of sampling hold circuit links to each other with the dither signal detection circuit input end, dither signal detection circuit is linked to each other with the reset signal generating circuit input end by output terminal, and the output terminal of reset signal generating circuit connects an input end of the second logical comparator circuit of frequency detection module; The reset signal of reset signal generating circuit output inserts the reset terminal of the envelope detected circuit in the correlation detection module and the reset terminal or the clear terminal of integration in the frequency detection module and summation circuit respectively;

7. as claim 3 or 4 or 5 or 6 described square wave detecting devices, it is characterized in that: described correlation detection module, frequency detection module and shake detection module also comprise a register separately: be respectively first register, second register and the 3rd register; Corresponding three fields that connect the register controlled word of upper system of the data input pin of three registers: wherein:

8. square wave detecting device as claimed in claim 6, its feature also is: described shake and frequency detection module also comprise second register and the 3rd register, wherein:

9. square wave detecting device as claimed in claim 2 is characterized in that: the wake-up signal end of the wireless transceiver circuit of the output terminal connecting band wireless awakening circuit of described square wave detecting device; Be used for when the AND circuit output terminal of square wave detecting device is high level, the wake-up signal WAKEUP of output high level realizes waking up wireless transceiver circuit.

10. as claim 1-6 or 8 described square wave detecting devices, its feature also is: the signal sample circuit of described square wave detecting device, and the correlation detection module of square wave testing circuit, shake detection module and frequency detection module, perhaps above-mentioned shake detection module and frequency detection module merge shake and the frequency detection module that constitutes, and AND circuit, adopt CMOS technology to be integrated in the chip, the chip-scale circuit is based on the Digital Analog Hybrid Circuits structure; Adopt the Digital Analog Hybrid Circuits structure to be used to improve the reliability height of square wave detecting device, thereby satisfy the high reliability request of wireless awakening circuit;