CN103178051B - 半导体元件堆叠结构 - Google Patents

半导体元件堆叠结构 Download PDF

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CN103178051B
CN103178051B CN201210111141.1A CN201210111141A CN103178051B CN 103178051 B CN103178051 B CN 103178051B CN 201210111141 A CN201210111141 A CN 201210111141A CN 103178051 B CN103178051 B CN 103178051B
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semiconductor element
silicon hole
connecting piece
girth member
element stacked
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CN103178051A (zh
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蒯定明
周永发
龙巧玲
钱睿宏
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Industrial Technology Research Institute ITRI
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Abstract

本揭露公开一种半导体元件堆叠结构，其包括多个半导体元件及至少一加固结构。半导体元件相互堆叠，其中至少一半导体元件具有至少一穿硅孔。各至少一加固结构围绕相应的至少一穿硅孔，并且电性隔绝于半导体元件。至少一加固结构包括多个加固件及至少一连结件。加固件位于半导体元件之间，其中加固件在平面上的垂直投影围出封闭区域，且至少一穿硅孔在平面上的投影位于封闭区域内。连结件位于加固件在平面上的垂直投影的重叠区域内，用以连接加固件，而构成至少一加固结构。

Description

半导体元件堆叠结构
技术领域
本申请涉及一种堆叠结构，且特别是涉及一种半导体元件堆叠结构。
背景技术
在现今的资讯社会中，电子产品的设计是朝向轻、薄、短、小的趋势迈进，因此发展出诸如堆叠式半导体元件封装等有利于微型化的封装技术。
堆叠式半导体元件封装是利用垂直堆叠的方式将多个半导体元件封装于同一封装结构中，如此可提升封装密度以使封装体小型化，且可利用立体堆叠的方式缩短半导体元件之间的信号传输的路径长度，以提升半导体元件之间信号传输的速度，并可将不同功能的半导体元件组合于同一封装体中。
现行的堆叠式半导体元件封装通常会在半导体元件内制作多个穿硅孔(throughsiliconvia，TSV)，以通过穿硅孔提供垂直方向的电连接路径。穿硅孔需具备良好的热机械可靠性(Thermo-Mechanicalreliability)，以便于批量生产，但由于穿硅孔内填材料与硅晶之间热膨胀系数(coefficientofthermalexpansion，CTE)的差异，使穿硅孔内产生热应力，进而导致塑料变形(plasticdeformation)、应力诱发孔洞(stressinducedvoiding)和应力迁移(stressmigration)，界面处的应力能导致剥离和填孔弹出(popup)甚至导致芯片断裂等不可挽救的情形。
发明内容
本揭露的目的在于提供一种半导体元件堆叠结构，其能有效减少穿硅孔的热应力所造成的半导体元件的翘曲变形。
为达上述目的，本揭露一实施范例提出一种半导体元件堆叠结构，包括多个半导体元件及至少一加固结构。半导体元件相互堆叠，其中至少一半导体元件具有至少一穿硅孔。各至少一加固结构围绕相应的至少一穿硅孔，并且电性隔绝于半导体元件。至少一加固结构包括多个加固件及至少一连结件。加固件位于半导体元件之间，其中加固件在平面上的垂直投影围出封闭区域，且至少一穿硅孔在平面上的投影位于封闭区域内。连结件位于加固件在平面上的垂直投影的重叠区域内，用以连接加固件，而构成至少一加固结构。
为让本揭露的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1为本揭露一实施例的半导体元件堆叠结构的局部分解示意图；
图2为本揭露一实施例的加固结构及硅穿孔于平面上垂直投影的示意图；
图3为本揭露一实施例的加固结构的俯视示意图；
图4为设置加固结构与未设置加固结构的半导体元件的应力比较图；
图5A至图5E为本揭露五种不同实施例的加固结构的部分构件俯视图。
主要元件符号说明
100：半导体元件堆叠结构
110：半导体元件
110a：第一半导体元件
110b：第二半导体元件
112：穿硅孔
114：第一表面
116：第二表面
120：加固结构
122：加固件
122a：第一加固件
122b：第二加固件
124：连结件
130：缓冲层
140、140a、140b、140c：加固区段
142：开口
144：第一部分
146：第二部分
148a：凸出部
148b：缺口
150：线路
CR：封闭区域
D：连结件外径
d：穿硅孔外径
L：距离
OR：重叠区域
P1：加固件投影
P2：穿硅孔投影
W：加固件宽度
W1：第一部分宽度
W2：第二部分宽度
具体实施方式
图1为本揭露一实施例的半导体元件堆叠结构的局部分解示意图。图2为本揭露一实施例的加固结构及硅穿孔于平面上垂直投影的示意图。其中，图1将上方的半导体元件110与加固结构120分离，以更清楚地绘示加固结构120。请同时参考图1及图2，本揭露一实施例提出一种半导体元件堆叠结构100，其包括多个半导体元件110(绘示为两个)及加固结构120。半导体元件110彼此相互堆叠，且其中半导体元件110具有穿硅孔112。在本实施例中，半导体元件110包括相互堆叠的第一半导体元件110a以及第二半导体元件110b，而穿硅孔112可以位于第一半导体元件110a中，或是配置于第一半导体组件110a与第二半导体组件110b之间，或是穿过第一半导体组件110a以及第二半导体组件110b。换言之，穿硅孔112可由第一半导体组件110a以及第二半导体组件110b的实际线路布局来决定。当然，本揭露并不限制半导体元件及其上的穿硅孔的数量或是穿硅孔112在所述半导体组件110之间的位置。
加固结构120围绕相应的穿硅孔112，并且电性隔绝于半导体元件110，意即，加固结构120不与穿硅孔112及半导体元件110中的其他主动元件形成电连接。对应于半导体元件110上的穿硅孔112，本实施例绘示一个加固结构120。实际上，加固结构120的数量与位置可以随半导体元件110上的穿硅孔112数量以及位置来进行调整。
本实施例的加固结构120包括多个加固件122及至少一连结件124，加固件122位于半导体元件110之间，其中加固件122在平面上的垂直投影P1围出封闭区域CR(CloseRegion)，且穿硅孔112在平面上的投影P2位于封闭区域CR内。连结件124位于加固件122在平面上的垂直投影P1的重叠区域OR内，用以连接加固件122，而构成加固结构120。换言之，加固结构120通过位在重叠区域OR内的连结件124，连结位于不同平面的多个加固件122。
在本实施例中，第一半导体元件110a具有第一表面114，第一表面114面向第二半导体元件110b的第二表面116。加固件122包括至少一第一加固件122a及至少一第二加固件122b，而第一加固件122a即位于第一表面114上，第二加固件122b则位于第二表面116上。连结件124的数量为多个，分别位于第一表面114与第二表面116之间，用以连接第一加固件122a与第二加固件122b。在本揭露的其他实施例中，第一加固件及第二加固件也可分别设置于不相邻的半导体元件的表面上，且第一加固件及第二加固件于平面上的垂直投影围出封闭区域。
详细而言，半导体元件堆叠结构100还包括缓冲层130，位于第一加固件122a与第二加固件122b之间，用以吸收穿硅孔112周围的热应力所导致的半导体元件110的变形，还可增加第一加固件122a及第二加固件122b的刚性(rigidity)，使半导体元件堆叠结构100的应力分布更为均匀。在本实施例中，第一半导体元件110a及第二半导体元件110b可为芯片、中介片(interposer)、晶圆(wafer)或封装件，而第一加固件122a可为第一半导体元件110a的第一表层金属图案，第二加固件122b可为第二半导体元件110b的第二表层金属图案。连结件124的材料包括铜、锡、铁、金、钨、钢、上开金属的复合物、化合物及合金等热膨胀系数相近的金属，且其形状可为圆形、方形或三角形等，在本实施例中，连结件124为焊球。如上述的配置，半导体元件110可利用其本身的结构形成围绕穿硅孔112的加固结构120，原则上可减少半导体元件110的翘曲变形，并降低穿硅孔112周围的应力。
图3为本揭露一实施例的加固结构的俯视示意图。请参考图3，加固结构120与穿硅孔112应符合一定的尺寸比例，以达到较佳的降低热应力的效果。本实施例，连结件124的外径D与加固件122的宽度W的比值大于或等于0.5，且小于或等于1.5。穿硅孔112的外径d与连结件124的外径D的比值应小于或等于2。穿硅孔112的中心至各连结件124的中心的距离为L，而L≤2(d+D)。并且，其中各连结件124与穿硅孔112的材料的热膨胀系数比值介于0.75至1.25之间。
图4为设置加固结构与未设置加固结构的半导体元件的应力比较图。图4的横轴座标为穿硅孔的外径，纵轴座标为穿硅孔周围的应力，具斜线的长条图则代表实施例的半导体元件堆叠结构于不同的穿硅孔外径下，其穿硅孔周围的应力。由图4可知，依穿硅孔的外径设置如前述的尺寸比例的加固结构于半导体元件上，其穿硅孔周围的应力与未设置加固结构的半导体元件相比，原则上将降低，并可改善现有半导体元件因应力过大而产生断裂的情形。
图5A至图5E为本揭露五种不同实施例的加固结构的部分构件俯视图。图5A至图5E的加固结构并未绘示第二加固件，以方便呈现其下方的结构。请先参考图5A，第一加固件122a包括串连连结件124的多个加固区段140。半导体元件堆叠结构还包括线路150，位于第一表面114上，线路150的一端连接穿硅孔112，而线路150的另一端朝向其中之加固区段140a延伸，且所述的加固区段140a具有开口142，以供线路150通过。在本揭露的另一实施例中，如图5B所示，线路150的两端分别朝向相邻的两个加固区段140b延伸，所述两个加固区段140b分别具有开口142，以供线路150的两端通过，且线路150在连接穿硅孔112的位置上形成接近90度的转折。在本揭露的另一实施例中，如图5C所示，线路150的两端分别朝向相对的两个加固区段140c延伸，所述两个加固区段140c分别具有开口142，以供线路150的两端通过。如上述的配置，穿硅孔112即可通过线路150与半导体元件110上的其他元件电连接。
承上述，加固区段140的宽度及形状还可因应半导体元件110上不同的线路及元件布局，或依热应力分布的大小，而做不同的改变。例如，如图5D及图5E所示，加固区段140中的至少一个可具有第一部分144以及第二部分146，且第一部分144的宽度W1大于第二部分146的宽度W2，或是，加固件122的边缘可具有至少一凸出部148a或至少一缺口148b。如此，加固区段140可依半导体元件110上的布局，改变其宽度或设置缺口148b以绕过半导体元件110上的线路及元件，还可依半导体元件110上的应力分布大小，于应力较大的部分增加加固区段140的宽度或设置凸出部148a以加强其结构强度。
下表1为本揭露五种不同实施例与现有的半导体元件堆叠结构所承受的最大应力比较表。其中，现有的半导体元件堆叠结构即为未设置加固结构的半导体元件。由下表1可推论，本揭露相较现有原则上可减少的半导体元件堆叠结构的内应力。
(表一)
综上所述，本揭露于半导体元件间设置围绕其穿硅孔的加固结构，本揭露实施例的加固结构还可依半导体元件上线路及元件的布局，或应力分布的大小，改变其加固结构的加固区段的宽度，以增加加固结构的应用性及弹性。
虽然结合以上实施例揭露了发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应以附上的权利要求所界定的为准。

Claims (21)

1.一种半导体元件堆叠结构，包括：
多个半导体元件，沿着垂直于一平面的方向相互堆叠，其中至少一半导体元件具有至少一穿硅孔；以及
至少一加固结构，各该至少一加固结构围绕相应的该至少一穿硅孔，并且电性隔绝于该些半导体元件，该至少一加固结构包括：
多个加固件，位于该些半导体元件之间，其中该些加固件在该平面上的垂直投影围出封闭区域，且该至少一穿硅孔在该平面上的投影位于该封闭区域内；以及
至少一连结件，在该平面上的垂直投影位于该些加固件在该平面上的垂直投影的重叠区域内，用以连接该些加固件，而构成该至少一加固结构。
2.如权利要求1所述的半导体元件堆叠结构，其中各该连结件的外径与各该加固件的宽度的比值大于或等于0.5，且小于或等于1.5。
3.如权利要求1所述的半导体元件堆叠结构，其中该至少一穿硅孔的外径与各该连结件的外径的比值小于或等于2。
4.如权利要求1所述的半导体元件堆叠结构，其中该至少一穿硅孔的中心至各该连结件的中心的距离为L，该至少一穿硅孔的外径为d，各该连结件的外径为D，且L≦2(d+D)。
5.如权利要求1所述的半导体元件堆叠结构，其中各该半导体元件包括芯片、中介片、晶圆或封装件。
6.如权利要求1所述的半导体元件堆叠结构，其中各该连结件的形状包括圆形、方形或三角形。
7.如权利要求1所述的半导体元件堆叠结构，其中各该连结件与该至少一穿硅孔的材料的热膨胀系数比值介于0.75至1.25之间。
8.如权利要求1所述的半导体元件堆叠结构，其中各该连结件的材料是与该至少一穿硅孔热膨胀系数相近的金属。
9.如权利要求1所述的半导体元件堆叠结构，其中该些半导体元件包括相互堆叠的第一半导体元件以及第二半导体元件，该第一半导体元件具有第一表面，该第一表面面向该第二半导体元件的第二表面，该至少一穿硅孔位于该第一半导体元件中，该些加固件包括位于该第一表面上的至少一第一加固件以及位于该第二表面上的至少一第二加固件，该至少一连结件位于该第一表面与该第二表面之间，用以连接该至少一第一加固件与该至少一第二加固件。
10.如权利要求9所述的半导体元件堆叠结构，其中该第一加固件包括该第一半导体元件的第一表层金属图案。
11.如权利要求9所述的半导体元件堆叠结构，其中该第二加固件包括该第二半导体元件的第二表层金属图案。
12.如权利要求1所述的半导体元件堆叠结构，其中各该连结件包括焊球。
13.如权利要求9所述的半导体元件堆叠结构，还包括缓冲层，位于该第一加固件与该第二加固件之间。
14.如权利要求9所述的半导体元件堆叠结构，其中该至少一连结件的数量为多个，且该第一加固件包括串连该至少一连结件的多个加固区段。
15.如权利要求14所述的半导体元件堆叠结构，还包括线路，位于该第一表面上，该线路的端连接该至少一穿硅孔，且该些加固区段中的一个具有开口，以供该线路通过。
16.如权利要求14所述的半导体元件堆叠结构，还包括线路，位于该第一表面上，该线路连接该至少一穿硅孔，且该线路的两端分别朝向相邻的两个加固区段延伸，所述两个加固区段分别具有开口，以供该线路的两端通过。
17.如权利要求16所述的半导体元件堆叠结构，其中该线路在连接该至少一穿硅孔的位置上形成90度的转折。
18.如权利要求14所述的半导体元件堆叠结构，还包括线路，位于该第一表面上，该线路连接该至少一穿硅孔，且该线路的两端分别朝向相对的两个加固区段延伸，所述两个加固区段分别具有开口，以供该线路的两端通过。
19.如权利要求14所述的半导体元件堆叠结构，其中该些加固区段中的至少一个具有第一部分以及第二部分，其中该第一部分的宽度大于该第二部分的宽度。
20.如权利要求1所述的半导体元件堆叠结构，其中各该加固件的边缘具有至少一凸出部或至少一缺口。
21.如权利要求1所述的半导体元件堆叠结构，其中各该连结件的材料包括金、钨、铜、锡、钢、铁、上述金属的复合物、化合物及合金。
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CN101740415A (zh) * 2008-11-07 2010-06-16 台湾积体电路制造股份有限公司 集成电路结构及其形成方法
CN102148220A (zh) * 2010-02-05 2011-08-10 台湾积体电路制造股份有限公司 半导体装置
CN102263090A (zh) * 2010-05-26 2011-11-30 台湾积体电路制造股份有限公司 封装系统

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