CN103066072A - Positive-intrinsic-negative (PIN) diode array structure and manufacturing method thereof - Google Patents

Positive-intrinsic-negative (PIN) diode array structure and manufacturing method thereof Download PDF

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CN103066072A
CN103066072A CN2011103161073A CN201110316107A CN103066072A CN 103066072 A CN103066072 A CN 103066072A CN 2011103161073 A CN2011103161073 A CN 2011103161073A CN 201110316107 A CN201110316107 A CN 201110316107A CN 103066072 A CN103066072 A CN 103066072A
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CN103066072B (en
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周正良
李�昊
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Abstract

The invention discloses a positive-intrinsic-negative (PIN) diode array structure. The structure is formed by a plurality of PIN diodes which are connected in parallel. The each PIN diode comprises a substrate, an N type cathode, an intrinsic semiconductor, a P type anode, an isolation region and an N-type outer-base-region cathode. The N type cathode which is in a round sheet shape is formed above the substrate. The 1.2 micron-3 micron intrinsic semiconductor is grown above a middle portion of the N type cathode with the round sheet shape. The N-type outer-base-region cathode with an annular shape is formed above a peripheral portion of the N type cathode with the round sheet shape. The P type anode with the round sheet shape is formed above a central area of the intrinsic semiconductor which is far from an N type cathode terminal. The invention also discloses a manufacturing method of the PIN diode array structure. According to the invention, through increasing a thickness of an epitaxial layer and reducing leakage of electricity during reverse bias, reverse isolation of a large signal is improved when a reverse bias voltage is increased. A stray capacitance is minimized through a parallel connection of same units and design optimization. A small positive series resistance and the positive and negative stray capacitances are obtained so as to reduce positive insertion losses.

Description

PIN diode array structure and manufacture method thereof
Technical field
The present invention relates to the semiconductor integrated circuit field, specifically belong to a kind of PIN diode array and manufacture method thereof that is compatible with the high-isolation low-insertion loss of bipolar technology.
Background technology
It is wireless transceiver that the typical case of radio frequency electric switch uses.Wireless transceiver is comprised of following four parts as shown in Figure 1 usually: power amplifier (PA), low noise amplifier (LNA), radio frequency electric switch, logic control circuit.Power amplifier and low noise amplifier are connected to antenna by the radio frequency electric switch, and radiofrequency signal is transmitted and received.Because passing to the signal of antenna from power amplifier must be enough strong, the forward conduction loss that connected radio frequency electric switch need to be tried one's best low.And to low noise amplifier, thereby can come in to form signal cross-talk from anti-inclined to one side radio frequency electric switch from the signal that power amplifier comes, the connected radio frequency electric switch high reverse isolation of need to trying one's best.Owing to being applied to transmitting and receiving of radio-frequency front-end, the radio frequency electric switch must possess transmission delay as far as possible low, low, reverse isolation degree is as far as possible high and can process feature greater than 100 milliwatt signals as far as possible to insert (forward conduction) loss.
PIN diode satisfies above requirement, and it is a kind of radio frequency electric switch, is widely used in and need to carries out in the circuit of opening and closing radiofrequency signal.PIN diode (positive-intrinsic-negative diode) is by highly doped p type anode, non-impurity-doped or low-doped wide intrinsic silicon area (Intrinsic), and highly doped N-type negative electrode forms, its operation principle is: when PIN diode adds a voltage that surpasses conduction threshold, low-doped intrinsic silicon area is completely depleted, junction capacitance increases rapidly, and conducting resistance (insertion loss) reduces; When diode was anti-inclined to one side, width of depletion region was approximately equal to the intrinsic silicon sector width, and junction capacitance is very little, and conducting resistance is very large, and isolation is very high.Square being directly proportional of the approximate thickness with the intrinsic silicon area of the insertion loss of PIN diode and isolation.So, to the low insertion loss requirement, reduce intrinsic silicon area thickness; To the high-isolation requirement, then need to increase intrinsic silicon area thickness as far as possible.
Conventional PIN diode adopts the form of discrete device more, and product existing packaged on the market is sold, and shortcoming is need to be external on pcb board, and volume is large, and expense is high.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of PIN diode array structure, and insertion loss is low, and high and its manufacturing process of reverse isolation degree can be compatible with bipolar technology.
For solving the problems of the technologies described above, the invention provides a kind of PIN diode array structure, described array structure is composed in parallel by a plurality of PIN diode single tubes; Each PIN diode single tube comprises substrate, N-type negative electrode, intrinsic semiconductor, p type anode, isolated area, N-type outer base area negative electrode; Described substrate top is formed with disc-shaped N-type negative electrode, it is the intrinsic semiconductor of 1.2 μ m～3 μ m that the mid portion top growth of disc-shaped N-type negative electrode has thickness, the peripheral part top of disc-shaped N-type negative electrode is formed with the circular N-type outer base area negative electrode coaxial with disc-shaped N-type negative electrode, described intrinsic semiconductor is affixed with circular N-type outer base area negative electrode near the periphery of described N-type cathode terminal, described intrinsic semiconductor is formed with the disc-shaped p type anode coaxial with disc-shaped N-type negative electrode away from the middle section of N-type cathode terminal top, described intrinsic semiconductor away from the periphery of N-type cathode terminal and disc-shaped p type anode periphery with between the circular N-type outer base area negative electrode by the circular isolated area isolation coaxial with disc-shaped N-type negative electrode.
Further, described array structure is square, and adjacent PIN diode single tube shares N-type outer base area negative electrode.
Preferably, described N-type negative electrode is the octagon disc-shaped, and described N-type outer base area negative electrode is that octagon is circular, and described isolated area is that octagon is circular, and described p type anode is the octagon disc-shaped.
Further, the isolated area below between described p type anode and the N-type outer base area negative electrode is formed with P type isolated area, and described intrinsic semiconductor is formed with P type isolated area away from periphery and the below of the isolated area between the N-type outer base area negative electrode of N-type cathode terminal.
Further, described isolated area is the isolation of oxygen, or shallow trench isolation from, perhaps an oxygen isolation or shallow trench isolation from the middle of increase deep trench.
For solving the problems of the technologies described above, the present invention also provides a kind of manufacture method of PIN diode array structure, may further comprise the steps:
Step 1 is carried out the N-type Implantation at P type substrate, forms a disc-shaped N-type negative electrode;
Step 2 is carried out outer layer growth at the whole upper surface of base plate that comprises disc-shaped N-type negative electrode, and forming thickness is the intrinsic semiconductor of 1.2 μ m～3 μ m;
Step 3, the epitaxial loayer above disc-shaped N-type negative electrode forms the circular isolated area coaxial with disc-shaped N-type negative electrode;
Step 4, the epitaxial loayer outside circular isolated area outer rim carries out the through disc-shaped N-type negative electrode of N Implantation along the outer rim of circular isolated area, forms coaxial with disc-shaped N-type negative electrode and is connected the circular N-type outer base area negative electrode of disc-shaped N-type negative electrode;
Step 5, above the epitaxial loayer in circular isolated area inner edge, the boron Implantation that carries out high dose forms the highly doped disc-shaped p type anode coaxial with disc-shaped N-type negative electrode, forms the PIN diode single tube;
Step 6 is carried out parallel connection with a plurality of PIN diode single tubes, and adjacent PIN diode single tube shares circular N-type outer base area negative electrode, forms array structure.
Further, below the circular isolated area between disc-shaped p type anode and the circular N-type outer base area negative electrode, carry out P type Implantation, form circular P type isolated area, simultaneously carry out P type Implantation at epitaxial loayer below away from the periphery of disc-shaped N-type cathode terminal and the circular isolated area between the circular N-type outer base area negative electrode, form circular P type isolated area.The ion implantation dosage of described circular P type isolated area is 10 14Cm -2～5x10 15Cm -2, Implantation Energy is 50keV～200keV.
Wherein, the ion of described disc-shaped N-type negative electrode is arsenic, and implantation dosage is 10 15Cm -2～10 16Cm -2, Implantation Energy is 50keV～100keV; Described epitaxial loayer is that non-impurity-doped or N-type are low-doped, and doping content is 10 14Cm -3～10 16Cm -3The ion of described circular N-type outer base area negative electrode is phosphorus, and implantation dosage is 10 15Cm -2～10 16Cm -2, Implantation Energy is 50keV～100keV; The ion of disc-shaped p type anode is boron, and implantation dosage is 10 15Cm -2～10 16Cm -2, Implantation Energy is 5keV～50keV.
Wherein, described N-type negative electrode is the octagon disc-shaped, and described N-type outer base area negative electrode is that octagon is circular, and described isolated area is that octagon is circular, and described p type anode is the octagon disc-shaped.
Pin diode switch of the present invention is by increasing the thickness of epitaxial loayer, electric leakage when reducing reverse bias, when increasing reverse bias voltage, improve the reverse isolation degree of large-signal, and by in parallel identical unit optimization design, regulate forward and reverse quiescent biasing voltage, parasitic capacitance is minimized, obtain less forward series resistance and forward and reverse parasitic capacitance, reduce the forward insertion loss, satisfy simultaneously the requirement of insertion loss and reverse isolation degree when realizing processing unlike signal intensity.Simultaneously, pin diode switch of the present invention can be integrated in germanium silicon (or conventional) bipolar technology, does not need to increase the cost of technology, for realizing that at single-chip the complete function of wireless transceiver provides low-cost solution.
Description of drawings
Below in conjunction with the drawings and the specific embodiments the present invention is described in further detail.
Fig. 1 is the wireless transceiver schematic diagram;
Fig. 2 is the schematic top plan view of PIN diode array structure of the present invention;
Fig. 3-Fig. 5 is the device architecture schematic diagram in the PIN diode single tube manufacturing process of the present invention;
Fig. 6 is the device architecture schematic top plan view of PIN diode single tube of the present invention.
Embodiment
PIN diode array structure of the present invention is composed in parallel by a plurality of PIN diode single tubes, and each PIN diode single tube comprises substrate 1, N-type negative electrode 2, intrinsic semiconductor 3, p type anode 7, isolated area 4, N-type outer base area negative electrode 5.For making parasitic capacitance minimum, the array that forms in parallel is preferably or close to square, array structure vertical view as shown in Figure 2, described array structure have 9 PIN diode single tubes to consist of 3 * 3 quadrate array, and adjacent PIN diode single tube shares N-type outer base area negative electrode 5.
Described substrate 1 top is formed with disc-shaped N-type negative electrode 2, it is the intrinsic semiconductor 3 of 1.2 μ m～3 μ m that the mid portion top growth of disc-shaped N-type negative electrode 2 has thickness, the peripheral part of disc-shaped N-type negative electrode 2 top is formed with the circular N-type outer base area negative electrode 5 coaxial with disc-shaped N-type negative electrode 2, described intrinsic semiconductor 3 is affixed with circular N-type outer base area negative electrode 5 near the periphery of described N-type negative electrode 2 ends, described intrinsic semiconductor 3 is formed with the disc-shaped p type anode 7 coaxial with disc-shaped N-type negative electrode 2 away from the middle section of N-type negative electrode 2 ends top, described intrinsic semiconductor 3 away from the periphery of N-type negative electrode 2 ends and disc-shaped p type anode 7 peripheries with between circular N-type outer base area 5 negative electrodes by circular isolated area 4 isolation coaxial with disc-shaped N-type negative electrode 2.
Isolated area 4 belows between described p type anode 7 and the N-type outer base area negative electrode 5 are formed with P type isolated area 6, and described intrinsic semiconductor 3 is formed with P type isolated area 6 away from the periphery of N-type negative electrode 2 ends and isolated area 4 belows between the N-type outer base area negative electrode 5.
Described isolated area 4 is the isolation of oxygen, or shallow trench isolation from, perhaps oxygen isolation on the scene or shallow trench isolation from the middle of increase deep trench.
Described substrate 1, N-type negative electrode 2, p type anode 7, isolated area 4, N-type outer base area negative electrode 5, P type isolated area 6 can be that regular hexagon, octagon, positive ten hexagons etc. are near the shape of circle simultaneously, in preferred embodiment of the present invention, as shown in Figure 6, described N-type negative electrode 2 is the octagon disc-shaped, described N-type outer base area negative electrode 5 is that octagon is circular, described isolated area 4 is that octagon is circular, described p type anode 7 is the octagon disc-shaped, and described P type isolated area 6 is that octagon is circular.
The manufacture method of the PIN diode array structure in the present embodiment, may further comprise the steps to shown in Figure 5 such as Fig. 3:
Step 1 is carried out the N-type Implantation at P type silicon substrate 1, forms a disc-shaped N-type negative electrode 2, and the ion of N-type negative electrode 2 is arsenic, and implantation dosage is 10 15Cm -2～10 16Cm -2, Implantation Energy is 50keV～100keV;
Step 2 is carried out outer layer growth at whole silicon substrate 1 upper surface that comprises disc-shaped N-type negative electrode 2, and forming thickness is the intrinsic semiconductor 3 of 1.2 μ m～3 μ m, as shown in Figure 3, described epitaxial loayer is that non-impurity-doped or N-type are low-doped, and impurity is phosphorus, and doping content is 10 14Cm -3～10 16Cm -3
Step 3, epitaxial loayer outside circular isolated area 4 outer rims, carry out the through disc-shaped N-type negative electrode 2 of N Implantation along the outer rim of circular isolated area 4, form coaxial with disc-shaped N-type negative electrode 2 and be connected the circular N-type outer base area negative electrode 5 of disc-shaped N-type negative electrode 2, the ion of described circular N-type outer base area negative electrode 5 is phosphorus, and implantation dosage is 10 15Cm -2～10 16Cm -2, Implantation Energy is 50keV～100keV;
Step 4, below the circular isolated area 4 between disc-shaped p type anode 7 and the circular N-type outer base area negative electrode 5, carry out P type Implantation, form circular P type isolated area 6, simultaneously carry out P type Implantation at epitaxial loayer below away from the periphery of disc-shaped N-type negative electrode 2 ends and the circular isolated area 4 between the circular N-type outer base area negative electrode 5, form circular P type isolated area 6; The ion implantation dosage of described circular P type isolated area is 10 14Cm -2～5x10 15Cm -2, Implantation Energy is 50keV～200keV, the distance between described annular P type isolated area 6 and the N-type negative electrode 2 is 2～5 microns, forms the reverse junction isolation;
Step 5, epitaxial loayer above disc-shaped N-type negative electrode 2 form the circular isolated area 4 coaxial with disc-shaped N-type negative electrode 2, and described isolated area 4 be an oxygen isolation, or shallow trench isolation from, perhaps oxygen isolation on the scene or shallow trench isolation from middle increase deep trench;
Step 6, above the epitaxial loayer in circular isolated area 4 inner edges, carry out the boron Implantation of high dose, form the highly doped disc-shaped p type anode 7 coaxial with disc-shaped N-type negative electrode, perhaps in the germanium silicon technology, add that with germanium and silicon epitaxial outer base area boron injects the highly doped p type anode of formation; The ion of disc-shaped p type anode 7 is boron, and implantation dosage is 10 15Cm -2～10 16Cm -2, Implantation Energy is 5keV～50keV, forms the PIN diode single tube;
Step 7 is carried out parallel connection with a plurality of PIN diode single tubes, and adjacent PIN diode single tube shares circular N-type outer base area negative electrode 5, forms array structure.
The peripheral use oxygen of array structure or shallow trench isolation from, also can oxygen on the scene or shallow trench in the middle of add again deep trench isolation.
The present invention passes through to increase the thickness of N-type epitaxial loayer, the electric leakage when having reduced reverse bias, thus utilize the method that increases reverse bias voltage to improve the reverse isolation degree of large-signal.The increase that simultaneously causes the forward series resistance for fear of the increase of N-type epitaxy layer thickness i.e. higher insertion loss, the present invention comes minimum parasitic capacitance by parallel connection identical unit and optimal design again, obtain less forward series resistance and forward and reverse parasitic capacitance, can be integrated into like this and realize satisfactory radio frequency electric switch in the bipolar technology flow process, thereby realize the complete function of wireless transceiver at single-chip, do not need to increase the cost of technology, for realizing that at single-chip the complete function of wireless transceiver provides low-cost solution.
Abovely by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that do not break away from the principle of the invention, those skilled in the art can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (10)

1. a PIN diode array structure is characterized in that,
Described array structure is composed in parallel by a plurality of PIN diode single tubes;
Each PIN diode single tube comprises substrate, N-type negative electrode, intrinsic semiconductor, p type anode, isolated area, N-type outer base area negative electrode;
Described substrate top is formed with disc-shaped N-type negative electrode, it is the intrinsic semiconductor of 1.2 μ m～3 μ m that the mid portion top growth of disc-shaped N-type negative electrode has thickness, the peripheral part top of disc-shaped N-type negative electrode is formed with the circular N-type outer base area negative electrode coaxial with disc-shaped N-type negative electrode, described intrinsic semiconductor is affixed with circular N-type outer base area negative electrode near the periphery of described N-type cathode terminal, described intrinsic semiconductor is formed with the disc-shaped p type anode coaxial with disc-shaped N-type negative electrode away from the middle section of N-type cathode terminal top, described intrinsic semiconductor away from the periphery of N-type cathode terminal and disc-shaped p type anode periphery with between the circular N-type outer base area negative electrode by the circular isolated area isolation coaxial with disc-shaped N-type negative electrode.
2. PIN diode array structure according to claim 1 is characterized in that, described array structure is square, and adjacent PIN diode single tube shares N-type outer base area negative electrode.
3. PIN diode array structure according to claim 1, it is characterized in that, described N-type negative electrode is the octagon disc-shaped, and described N-type outer base area negative electrode is that octagon is circular, described isolated area is that octagon is circular, and described p type anode is the octagon disc-shaped.
4. PIN diode array structure according to claim 1, it is characterized in that, isolated area below between described p type anode and the N-type outer base area negative electrode is formed with P type isolated area, and described intrinsic semiconductor is formed with P type isolated area away from periphery and the below of the isolated area between the N-type outer base area negative electrode of N-type cathode terminal.
5. PIN diode array structure according to claim 4 is characterized in that, described isolated area is the isolation of oxygen, or shallow trench isolation from, perhaps an oxygen isolation or shallow trench isolation from the middle of increase deep trench.
6. the manufacture method of a PIN diode array structure is characterized in that, may further comprise the steps:
Step 1 is carried out the N-type Implantation at P type substrate, forms a disc-shaped N-type negative electrode;
Step 2 is carried out outer layer growth at the whole upper surface of base plate that comprises disc-shaped N-type negative electrode, and forming thickness is the intrinsic semiconductor of 1.2 μ m～3 μ m;
Step 3, the epitaxial loayer outside circular isolated area outer rim carries out the through disc-shaped N-type negative electrode of N Implantation along the outer rim of circular isolated area, forms coaxial with disc-shaped N-type negative electrode and is connected the circular N-type outer base area negative electrode of disc-shaped N-type negative electrode;
Step 4, the epitaxial loayer above disc-shaped N-type negative electrode forms the circular isolated area coaxial with disc-shaped N-type negative electrode;
Step 5, above the epitaxial loayer in circular isolated area inner edge, the boron Implantation that carries out high dose forms the highly doped disc-shaped p type anode coaxial with disc-shaped N-type negative electrode, forms the PIN diode single tube;
Step 6 is carried out parallel connection with a plurality of PIN diode single tubes, and adjacent PIN diode single tube shares circular N-type outer base area negative electrode, forms array structure.
7. the manufacture method of PIN diode array structure according to claim 6, it is characterized in that, after step 3, below the circular isolated area between disc-shaped p type anode and the circular N-type outer base area negative electrode, carry out P type Implantation, form circular P type isolated area, simultaneously carry out P type Implantation at epitaxial loayer below away from the periphery of disc-shaped N-type cathode terminal and the circular isolated area between the circular N-type outer base area negative electrode, form circular P type isolated area, and then carry out step 4.
8. the manufacture method of PIN diode array structure according to claim 6 is characterized in that, the ion of described disc-shaped N-type negative electrode is arsenic, and implantation dosage is 10 15Cm -2～10 16Cm -2, Implantation Energy is 50keV～100keV; Described epitaxial loayer is that non-impurity-doped or N-type are low-doped, and doping content is 10 14Cm -3～1016cm -3The ion of described circular N-type outer base area negative electrode is phosphorus, and implantation dosage is 10 15Cm -2～10 16Cm -2, Implantation Energy is 50keV～100keV; The ion of disc-shaped p type anode is boron, and implantation dosage is 10 15Cm -2～10 16Cm -2, Implantation Energy is 5keV～50keV.
9. the manufacture method of PIN diode array structure according to claim 7 is characterized in that, the ion implantation dosage of described circular P type isolated area is 10 14Cm -2～5x10 15Cm -2, Implantation Energy is 50keV～200keV.
10. the manufacture method of PIN diode array structure according to claim 6, it is characterized in that, described N-type negative electrode is the octagon disc-shaped, and described N-type outer base area negative electrode is that octagon is circular, described isolated area is that octagon is circular, and described p type anode is the octagon disc-shaped.
CN201110316107.3A 2011-10-18 2011-10-18 Positive-intrinsic-negative (PIN) diode array structure and manufacturing method thereof Active CN103066072B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112713145A (en) * 2019-10-24 2021-04-27 华为技术有限公司 Switch semiconductor device, preparation method thereof and solid-state phase shifter

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050006729A1 (en) * 2002-05-03 2005-01-13 Hoag David Russell Method of making heterojunction P-I-N diode
US7242071B1 (en) * 2006-07-06 2007-07-10 International Business Machine Corporation Semiconductor structure
US20070278614A1 (en) * 2006-06-05 2007-12-06 Collins David S Lateral passive device having dual annular electrodes
CN101140955A (en) * 2006-09-06 2008-03-12 中国科学院微电子研究所 Gallium arsenide PIN diode and preparation method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050006729A1 (en) * 2002-05-03 2005-01-13 Hoag David Russell Method of making heterojunction P-I-N diode
US20070278614A1 (en) * 2006-06-05 2007-12-06 Collins David S Lateral passive device having dual annular electrodes
US7242071B1 (en) * 2006-07-06 2007-07-10 International Business Machine Corporation Semiconductor structure
CN101140955A (en) * 2006-09-06 2008-03-12 中国科学院微电子研究所 Gallium arsenide PIN diode and preparation method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112713145A (en) * 2019-10-24 2021-04-27 华为技术有限公司 Switch semiconductor device, preparation method thereof and solid-state phase shifter
WO2021078280A1 (en) * 2019-10-24 2021-04-29 华为技术有限公司 Switching semiconductor device and manufacturing method therefor, and solid-state phase shifter
JP7436648B2 (en) 2019-10-24 2024-02-21 華為技術有限公司 Semiconductor switch device, its manufacturing method, and solid state phase shifter

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