CN102955127B

CN102955127B - Debugging method for large-scale field programmable gate array (FPGA) design

Info

Publication number: CN102955127B
Application number: CN201110254985.7A
Authority: CN
Inventors: 龚永鑫
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2011-08-31
Filing date: 2011-08-31
Publication date: 2015-04-22
Anticipated expiration: 2031-08-31
Also published as: CN102955127A

Abstract

The invention provides a debugging method for large-scale field programmable gate array (FPGA) design, and mainly aims to provide a relatively general debugging method. By the debugging method, the time of debugging an FPGA prototype is saved, and the efficiency of debugging the FPGA prototype is improved. The main theory is that a redundant control logic is designed; and a main machine end configures a corresponding register of the control logic through operation of a universal asynchronous receiver/transmitter (UART), so that an external test pin is selectively connected to a signal to be tested in a certain FPGA chip. By the method, the structure is simple; the method is easy to implement; the external test pin can test a plurality of inner signals to be tested of the FPGA chips; and during test, the inner signals to be tested of certain FPGA chips can be freely selected, and the signals are not required to be grouped in advance.

Description

A kind of for the adjustment method in large-scale F PGA design

Technical field

The present invention relates to FPGA design field, particularly relate to the adjustment method in a kind of FPGA design.

Background technology

In recent years, along with the scale of FPGA design is increasing, the scale of fpga chip is also increasing, has seemed most important in the debugging in FPGA prototype on the impact of project process.Such as, in a WLAN (wireless local area network) FPGA design, debugging occupies very large ratio, so the debugging accelerated in FPGA prototype effectively can improve project process.

Now, about the debugging in FPGA prototype, also some debugging acid relatively commonly used and methods are had on the market, such as, direct amendment code by need signal assign to external testing pin, Embedded logic analyser, internal signal is guided to external testing pin by FPGA Editor, the dynamic probes etc. that Agilent is released.

Some method needs to re-start FPGA placement-and-routing, can cause the huge waste of time cost.

Some method needs the BRAM resource with FPGA inside, and data acquisition storage depth is limited, sometimes needs the signal time observed longer in the debugging of large-scale F PGA design, and these class methods also have its limitation.

Certain methods is also had to can be implemented in the test of a pin to multiple inner measured signal, but need to set grouping in advance, can not realize a pin to the selection of any one inside measured signal, need the software of respective producer to coordinate in addition, testing cost is more expensive.

This invention can be implemented in and do not re-start FPGA placement-and-routing, and main frame realizes an external testing pin by UART interface operation steering logic and tests multiple inner measured signal, and does not need to pre-set grouping.

Summary of the invention

The invention provides a kind of adjustment method be applicable in large-scale F PGA design, fundamental purpose is the debugging efficiency improved in FPGA prototype, reduces testing cost, and can realize an external testing pin to the selection of any one inside measured signal.Cardinal principle is that main frame realizes the connection of inner measured signal and external testing pin by the steering logic of UART interface operation FPGA inside.

First, set inner measured signal in advance, suppose have 2 ⁿindividual signal to be observed, in advance this 2 ⁿindividual signal is set to inner measured signal and is connected to the steering logic of FPGA inside, N be more than or equal to 1 integer; The steering logic of FPGA inside be input as 2 ⁿindividual inner measured signal, the external testing pin of FPGA is received in the output of FPGA, case of external test pin is X altogether, the steering logic of FPGA carries out register configuration by UART, each register bit wide is N, which inner measured signal configurable X register control X external testing pin is connected to, and finally, external testing pin is connected to inner measured signal.

The advantage of the method:

Do not need to re-start FPGA placement-and-routing, reduce time cost.

An external testing pin can be realized to the selection of any one inside measured signal, not need to pre-set grouping.

Accompanying drawing explanation

Accompanying drawing 1 is the signal wiring figure for the adjustment method in large-scale F PGA design.

Accompanying drawing 2 is this adjustment method FPGA inner control logic schematic diagrams.

Embodiment

Below in conjunction with accompanying drawing, illustrate the present invention.

The invention provides a kind of adjustment method be applicable in large-scale F PGA design, fundamental purpose is the debugging efficiency improved in FPGA prototype, reduces testing cost, and can realize an external testing pin to the selection of any one inside measured signal.Cardinal principle is the connection being realized inner measured signal and external testing pin by the steering logic of main frame UART interface operation FPGA inside.

First, need to set inner measured signal in advance, suppose have 2 ⁿthe individual signal wanting to observe, so to need when designing in advance this 2 ⁿindividual signal is set to the steering logic that inner measured signal is connected to FPGA inside.

Steering logic is input as 2 ⁿindividual inner measured signal, external testing pin is received in output, and suppose that output is received external testing pin and is X altogether, steering logic is similar to and is equivalent to 1 is carried out register configuration MUX selector switch by UART, one total configurable register X is individual, and each register bit wide is N.As can be seen from accompanying drawing 1 and accompanying drawing 2, a configurable X register (sel_0 ~ sel_X-1) is configured by main frame UART, and control X external testing pin (out [0] ~ out [X-1]) is connected to which inner measured signal (test [0] ~ test [2 ⁿ-1]), concrete FPGA inside realization is equivalent to a large MUX selector switch, after sel_n is set to a fixed value, external testing pin out [n] is connected to inner measured signal test [sel_n], such as: when sel_0 is set to fixed value 5, so namely out [0] is connected to test [5].It can thus be appreciated that the method external testing pin (out [0] ~ out [X-1]) can be connected to any one of inner measured signal.

Claims

1. for the adjustment method in large-scale F PGA design, it is characterized in that, main frame realizes the connection at inner measured signal and external testing pin by UART interface operation steering logic, and step is as follows:

Set inner measured signal, suppose have 2 ⁿindividual signal to be observed, in advance this 2 ⁿindividual signal is set to inner measured signal and is connected to the steering logic of FPGA inside, N be more than or equal to 1 integer; The steering logic of FPGA inside be input as 2 ⁿindividual inner measured signal, the external testing pin of FPGA is received in the output of FPGA, case of external test pin is X altogether, the steering logic of FPGA carries out register configuration by UART, which inner measured signal configurable X register control X external testing pin is connected to, finally, external testing pin is connected to inner measured signal.