CN102930065A

CN102930065A - Method for collecting multichannel and high-capacity data in real time

Info

Publication number: CN102930065A
Application number: CN2012104410275A
Authority: CN
Inventors: 于星光
Original assignee: Kunshan Beiji Photoelectron Science & Technology Co Ltd
Current assignee: Kunshan Beiji Photoelectron Science & Technology Co Ltd
Priority date: 2012-11-07
Filing date: 2012-11-07
Publication date: 2013-02-13

Abstract

The invention discloses a method for collecting multichannel and high-capacity data in real time. The method comprises high-speed A/D1#, high-speed A/D2#, high-speed A/D3# and high-speed A/D4#, a first-in first-out memory M and a system clock. The method is used for rapidly and collecting multichannel and high-capacity data in a mechanical fault diagnosis system rapidly, synchronously and in real time, and diagnosis response and analysis speeds of the mechanical fault diagnosis system are increased.

Description

A kind of multi-channel and high capacity real-time data acquisition method

Technical field

The invention belongs to the online detection field of plant equipment, related in particular to a kind of multi-channel and high capacity real-time data acquisition method.

Background technology

Online detection field in plant equipment, development and widespread use along with the High Resolution Method of Array Signal Processing, requirement to the real-time processing of multichannel array signal processing system is also more and more high, in order to finish the real-time implementation of the high-resolution methods such as the estimation of high-resolution orientation, distance estimations, Frequency Estimation, existing several modes all are difficult to finish a plurality of channel data collections of high speed real-time synchronization at present.

Summary of the invention

The object of the invention is to provide a kind of multi-channel and high capacity real-time data acquisition method.

The technical scheme that realizes above-mentioned purpose is: a kind of multi-channel and high capacity real-time data acquisition method comprises: high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, high-speed a/d 4#, and push-up storage M and system clock CLK, wherein:

Described high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, high-speed a/d 4#, be responsible for image data, its corresponding data-out bus D0～D7, D8～D15, D16～D23, D24～D31 access respectively input bus In0～In7, In8～In15, In16～In23, the In24～In31 of described push-up storage M accordingly, and the work clock of described high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, high-speed a/d 4# all is connected to described system clock CLK;

Described push-up storage M is responsible for the buffer-stored data, input bus In0～In7 that it is corresponding, In8～In15, In16～In23, In24～In31 connects respectively described high-speed a/d 1# accordingly, high-speed a/d 2#, high-speed a/d 3#, data-out bus D0～D7 of high-speed a/d 4#, D8～D15, D16～D23, D24～D31, output bus Out0～Out31 of described push-up storage M is with described high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, the data that high-speed a/d 4# collects flow to rear level processor and process, and the clock of described push-up storage M is connected to described system clock CLK.

Above-mentioned high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, high-speed a/d 4# are 8 A/D converters of high-speed parallel, described system clock CLK is high level, described high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, high-speed a/d 4# sampled data, described system clock CLK is low level, and output bus D0～D7, the D8～D15 of described high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, high-speed a/d 4#, D16～D23, D24～D31 export data.

Above-mentioned push-up storage M is 32 push-up storage, described system clock CLK is high level, output bus Out0～Out31 of described push-up storage M is with described high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, the data that high-speed a/d 4# collects flow to rear level processor and process, described system clock CLK is low level, input bus In0～In7 of described push-up storage M, In8～In15, In16～In23, In24～In31 inputs respectively described high-speed a/d 1# accordingly, high-speed a/d 2#, high-speed a/d 3#, data-out bus D0～D7 of high-speed a/d 4#, D8～D15, D16～D23, data on D24～D31.

There is a buffer space N between the output data of above-mentioned push-up storage M and the input data, in a certain moment of described system clock CLK, the data of described push-up storage M input bus when the data on the described push-up storage M output bus are beats of the described system clock CLK of top n of data of described push-up storage M input bus.

The frequency of said system clock CLK is less than the working clock frequency of described high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, high-speed a/d 4# and described push-up storage M.

The invention has the beneficial effects as follows: the Large Volume Data of a plurality of passages of collection that the present invention can the high speed real-time synchronization, can realize a plurality of channel datas transmission that high speed is real-time, be particularly useful for the online detection field of plant equipment.

Description of drawings

Fig. 1 is schematic flow sheet of the present invention.

Embodiment

The invention will be further described below in conjunction with accompanying drawing.

With reference to Fig. 1, embodiments of the present invention have been provided among the figure, in the present embodiment, high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, high-speed a/d 4# adopt 4 AD7864, and push-up storage M adopts fpga chip Spartan-6, system clock CLK frequency is 10MHz, wherein:

4 AD7864 are responsible for image data, its corresponding data-out bus D0～D7, D8～D15, D16～D23, D24～D31 access respectively input bus In0～In7, In8～In15, In16～In23, the In24～In31 of Spartan-6 accordingly, and the work clock of 4 AD7864 all is connected to system clock CLK;

Spartan-6 is responsible for the buffer-stored data, its corresponding input bus In0～In7, In8～In15, In16～In23, In24～In31 connect respectively data-out bus D0～D7, D8～D15, D16～D23, the D24～D31 of 4 AD7864 accordingly, the data that output bus Out0～Out31 of Spartan-6 collects 4 AD7864 flow to rear level processor and process, and the clock of Spartan-6 is connected to system clock CLK.

4 AD7864 are 8 A/D converters of high-speed parallel, and system clock CLK is high level, 4 AD7864 sampled datas, and system clock CLK is low level, output bus D0～D7, the D8～D15 of 4 AD7864, D16～D23, D24～D31 export data.

Spartan-6 is 32 push-up storage, system clock CLK is high level, the data that output bus Out0～Out31 of Spartan-6 collects 4 AD7864 flow to rear level processor and process, system clock CLK is low level, and input bus In0～In7, the In8～In15 of Spartan-6, In16～In23, In24～In31 input respectively data-out bus D0～D7, the D8～D15 of 4 AD7864, the data on D16～D23, the D24～D31 accordingly.

There is a buffer space N between the output data of Spartan-6 and the input data, when the work delay time of rear level processor is T=10uS, then the computing formula of buffer space is N=T*CLK=10uS*10MHz=100, namely in a certain moment of system clock CLK, the data the when data on the Spartan-6 output bus are the beats of 100 system clock CLK before the data of Spartan-6 input bus.

The work clock that 4 AD7864 working clock frequencies are 40MHz and Spartan-6 is 100MHz frequently.

Principle of the present invention is: the logic function growth data highway width that utilizes high-speed a/d and push-up storage, carry out parallel data processing, improve picking rate, utilize the data buffering function of push-up storage to preserve Large Volume Data, utilize unified system clock to control the synchronous working of each high speed device, thereby realize the Large Volume Data of a plurality of passages of collection of high speed real-time synchronization.

Below embodiment has been described in detail the present invention by reference to the accompanying drawings, and those skilled in the art can make the many variations example to the present invention according to the above description.Thereby some details among the embodiment should not consist of limitation of the invention, and the scope that the present invention will define with appended claims is as protection scope of the present invention.

Claims

1. a multi-channel and high capacity real-time data acquisition method is characterized in that, comprising: high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, high-speed a/d 4#, and push-up storage M and system clock CLK, wherein:

2. a kind of multi-channel and high capacity real-time data acquisition method according to claim 1, it is characterized in that, described high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, high-speed a/d 4# are 8 A/D converters of high-speed parallel, described system clock CLK is high level, described high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, high-speed a/d 4# sampled data, described system clock CLK is low level, and output bus D0～D7, the D8～D15 of described high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, high-speed a/d 4#, D16～D23, D24～D31 export data.

3. a kind of multi-channel and high capacity real-time data acquisition method according to claim 1, it is characterized in that, described push-up storage M is 32 push-up storage, described system clock CLK is high level, output bus Out0～Out31 of described push-up storage M is with described high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, the data that high-speed a/d 4# collects flow to rear level processor and process, described system clock CLK is low level, input bus In0～In7 of described push-up storage M, In8～In15, In16～In23, In24～In31 inputs respectively described high-speed a/d 1# accordingly, high-speed a/d 2#, high-speed a/d 3#, data-out bus D0～D7 of high-speed a/d 4#, D8～D15, D16～D23, data on D24～D31.

4. a kind of multi-channel and high capacity real-time data acquisition method according to claim 1, it is characterized in that, there is a buffer space N between the output data of described push-up storage M and the input data, in a certain moment of described system clock CLK, the data of described push-up storage M input bus when the data on the described push-up storage M output bus are beats of the described system clock CLK of top n of data of described push-up storage M input bus.

5. a kind of multi-channel and high capacity real-time data acquisition method according to claim 1, it is characterized in that, the frequency of described system clock CLK is less than the working clock frequency of described high-speed a/d 1#, high-speed a/d 2#, high-speed a/d 3#, high-speed a/d 4# and described push-up storage M.