CN102810491B - Rear grid technique removes the method for supervising of polycrystalline silicon dummy gate processing procedure - Google Patents
Rear grid technique removes the method for supervising of polycrystalline silicon dummy gate processing procedure Download PDFInfo
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- CN102810491B CN102810491B CN201110149722.XA CN201110149722A CN102810491B CN 102810491 B CN102810491 B CN 102810491B CN 201110149722 A CN201110149722 A CN 201110149722A CN 102810491 B CN102810491 B CN 102810491B
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Abstract
The invention provides the method for supervising that a kind of rear grid technique removes polycrystalline silicon dummy gate processing procedure, comprise the following steps: form polycrystalline silicon dummy gate structure and test structure at crystal column surface; Determine test structure density measurement target and error range; Use the density of XRR device measuring test structure, judge whether polycrystalline silicon dummy gate removes completely.This technology can the thickness of effective monitoring plural layers and density, and have rapid measuring, result is advantage accurately, and this technology is just in the starting stage in the application of integrated circuit industry circle, is a kind of wafer process monitoring means having very much development potentiality.According to method for measurement of the present invention, quick and precisely effective monitoring can judge whether polycrystalline silicon dummy gate thoroughly removes, this method for measurement can not bring damage to wafer simultaneously.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, more particularly, relate to the method for supervising that a kind of rear grid technique removes polycrystalline silicon dummy gate processing procedure.
Background technology
With the successful Application of high K/ metal gate engineering in 45 nm technology node, become the following technology node of sub-30 nanometer indispensable key modules chemical industry journey.After only adhering to high K/ at present, the Intel company of metal gate (gatelast) route achieves successfully in 45 nanometers and 32 nanometer volume productions.Follow the industry giants such as the Samsung of IBM industry alliance, Taiwan Semiconductor Manufacturing Co., Infineon in recent years closely and also the emphasis developed before is turned to gatelast engineering by the first metal gate (gatefirst) of high K/.
In Gatelast engineering, after completing ion at high temperature annealing, need polysilicon gate to dig up, be then filled into metal gate electrode, flow process refers to Fig. 1.As Figure 1A, substrate 1 is formed successively insulating barrier 2, polycrystalline silicon dummy gate pole 3, gate lateral wall 4, interlayer dielectric layer (IDL) 5.As Figure 1B, remove polycrystalline silicon dummy gate pole 3, form gate openings 6, then fill metal gate electrode material.Polysilicon gate sidewall 4 is the side wall (spacer) of silica or silicon nitride material, and the insulating barrier 2 below polysilicon gate is high K or silica or silicon oxy-nitride material that deposit is good.At present, industrial quarters has three process routes to complete the removal work of the false grid of polycrystalline, is dry etching respectively, wet etching, and dry method-wet-mixed etching; From the result of testing and report, be more prone to rear 2 kinds of methods.
The false grid 3 of polycrystalline need to carry out effective monitoring means to judge whether polysilicon is got rid of completely after removing, and the residual of any polycrystalline all can cause great negative effect to device electrical performance.How effective this technique belongs to 32nm and following advanced technologies, after the false grid 3 of polycrystalline remove monitor processing procedure, there is not yet any report.Method sees that the false grid 3 of polycrystalline remove the cross section of rear wafer by scanning electron microscopy the most intuitively, but this method has destructiveness to wafer, and feedback result is very slow, the effective monitoring to processing procedure when cannot be directly used in volume production.Meanwhile, what the monitoring of current integrated circuit industry bound pair manufacturing process major part adopted is optical measurement means, and constantly reducing with technology node, device architecture becomes increasingly complex, and the film of lamination is more and more thinner, and traditional optical method for measurement encounters very large challenge.For this reason, be badly in need of one intuitively, the undamaged quick and precisely effective method for supervising of wafer is judged that whether thorough the false grid of polycrystalline remove.
Summary of the invention
Therefore, the object of the invention is to propose the method for supervising that a kind of rear grid technique removes polycrystalline silicon dummy gate processing procedure, so that quick and precisely effective monitoring judges whether polycrystalline silicon dummy gate thoroughly removes, meanwhile, this method for measurement can not bring damage to wafer.
The invention provides the method for supervising that a kind of rear grid technique removes polycrystalline silicon dummy gate processing procedure, comprise the following steps: form polycrystalline silicon dummy gate structure and test structure at crystal column surface; Determine test structure density measurement target and error range; Use the density of XRR device measuring test structure, judge whether polycrystalline silicon dummy gate removes completely.
Present invention also offers the method for supervising that a kind of rear grid technique removes polycrystalline silicon dummy gate processing procedure, comprise the following steps: form polycrystalline silicon dummy gate structure and test structure at crystal column surface; Determine that in test structure, thickness of insulating layer measures target and error range; Use the thickness of XRR device measuring insulating barrier and polysilicon, judge whether polysilicon removes completely and/or over etching occurs.
Wherein, test structure and polycrystalline silicon dummy gate adopt same process to be produced in same horizontal plane simultaneously.Wherein, test structure comprises insulating barrier, polysilicon, sidewall, the interlayer dielectric layer on substrate.Wherein, test structure has predetermined pattern density, and this pattern density is defined as the ratio of polysilicon width and polysilicon distance.Wherein, the density range of test structure is 10%-100%.Wherein, the density range of test structure is 50%.
Wherein, test structure is positioned on the line of cut of inside wafer individual chips unit, or it is inner to be positioned at individual chips unit.
Wherein, test structure is rectangle or square.Wherein, test structure is of a size of the one in 20 μm × 20 μm, 30 μm × 30 μm, 50 μm × 50 μm.
Wherein, insulating barrier is high-g value, silica or silicon oxynitride.
Wherein, property design (DOE) is in conjunction with XRR means of testing by experiment, obtains the test structure density of sample wafer and/or thickness of insulating layer and error range that polysilicon is completely removed.
Wherein, if test structure density and/or thickness of insulating layer exceed error range, then judge that polysilicon is not removed completely, needs aftertreatment.
This patent propose the false grid of two polycrystalline remove after monitoring route and test structure, have employed X ray reflection technology (XRR) to monitor the false grid of polycrystalline and remove and whether remove thoroughly, this technology can the thickness of effective monitoring plural layers and density, there is rapid measuring, result is advantage accurately, this technology is just in the starting stage in the application of integrated circuit industry circle, is a kind of wafer process monitoring means having very much development potentiality.According to method for measurement of the present invention, quick and precisely effective monitoring can judge whether polycrystalline silicon dummy gate thoroughly removes, this method for measurement can not bring damage to wafer simultaneously.
Object of the present invention, and in these other unlisted objects, met in the scope of the application's independent claims.Embodiments of the invention limit in the independent claim, and specific features limits in dependent claims thereto.
Accompanying drawing explanation
Technical scheme of the present invention is described in detail referring to accompanying drawing, wherein:
Fig. 1 shows the rear grid technique schematic diagram of prior art;
Fig. 2 shows XRR measuring technique schematic diagram;
Fig. 3 shows the shape and size schematic diagram of resolution chart; And
Fig. 4 shows the structural representation of resolution chart.
Embodiment
Describe feature and the technique effect thereof of technical solution of the present invention in detail in conjunction with schematic embodiment referring to accompanying drawing, disclose and propose to adopt XRR measurement technology to remove rear grid technique polycrystalline silicon dummy gate and monitor, and provide corresponding test structure.It is pointed out that structure like similar Reference numeral representation class.
The method for measurement that the present invention proposes based on X ray reflection technology (X-rayreflectivity is called for short XRR) solves above-mentioned technical problem.This technology is just in the starting stage in the application of integrated circuit industry circle, is a kind of process monitoring means having very much development potentiality.Its general principle is that X ray is reached sample surfaces at a certain angle, can reflect when X ray runs into lower layer of material interface after penetrating film; The thickness of surveyed film is obtained by the phase difference calculating incident X-rays and reflection X-ray.The X ray reflected from film carries thin-film information, and this technology effectively can measure thickness and the density of complicated plural layers.Its outstanding strong penetrability feature of X ray makes measurement process not be subject to the restriction of metal and nonmetallic materials, and lamination is more many is more conducive to its modeling and measurement.Simultaneously to have measurement speed fast for the method, result is advantage accurately, and its measurement process is shown in sketch 2, launches X ray from x-ray source with a certain special angle to crystal column surface, its symmetric position arranges X-ray detector, obtains thickness by the calculating control system be connected according to phase difference.
embodiment 1
With reference to accompanying drawing 1, form insulating barrier 2, polycrystalline silicon dummy gate pole 3, gate lateral wall 4, interlayer dielectric layer (IDL) 5 successively on substrate 1, then remove polycrystalline silicon dummy gate pole 3, form gate openings 6.As seen from Figure 1, after the false grid 3 of polycrystalline remove, wafer when layer film quality (also namely on crystal column surface IDL5 and between the sidewall 4 of institute's sandwiched, each layer film quality sum of gate openings 6) will obviously reduce, density reduces thereupon; Therefore by the monitoring to wafer fc-specific test FC density of texture, can judge whether the false grid of polycrystalline are removed clean completely; Adopt the method to measure will to have test result directly perceived, to wafer not damaged and measure the high feature of efficiency, be applicable to polycrystalline vacation grid and remove the rear effective monitoring to technique.
Particularly, the method removing polycrystalline silicon dummy gate according to the rear grid technique of one embodiment of the present of invention comprises the following steps:
First, polycrystalline silicon dummy gate structure and test structure is formed at crystal column surface.As shown in Figure 1, crystal column surface is formed with polycrystalline silicon dummy gate structure, also namely forms insulating barrier 2, polycrystalline silicon dummy gate pole 3, gate lateral wall 4, interlayer dielectric layer (IDL) 5 successively on substrate 1, then removes polycrystalline silicon dummy gate pole 3, forms gate openings 6.Meanwhile, as shown in Figure 3, Figure 4, in same level, the test structure 7 of polysilicon material is formed at crystal column surface by the technique identical with forming polycrystalline silicon dummy gate.Test structure 7 shape is such as rectangle, and example can put to the proof square or rectangular structure, as long as its structure can form specific phase difference for the X ray reflection of special angle.For the square that embodiment is lifted, (long a is multiplied by and widely b) includes but not limited to 20 μm × 20 μm, 30 μm × 30 μm, 50 μm × 50 μm etc., see Fig. 3 size.The figure of test structure 7 is band side wall polysilicon gate, and unified with making technology, enlarged drawing is shown in Fig. 4, and also namely test structure 7 also comprises substrate 1, insulating barrier 2, gate lateral wall 4, IDL5.The pattern density of test structure 7 is defined as the ratio of width d between polysilicon gate width c and polysilicon gate, i.e. c/d, its density range 10%-100%, and example can put to the proof 50%; For the pattern density of 50%, the concrete size of c is as the criterion with the grid width of actual product (gateCD).Test structure 7 position can with saving chip area on the line of cut of inside wafer individual chips unit, or individual chips unit inner with the resolution chart between the different chip of personal settings to adjust for different grid widths.
Secondly, test structure density measurement target and error range is determined.Can first at the upper specifically created multiple resolution chart 7 of the wafer (being also namely not used in the wafer for subsequent use finally cutting into chip product) of test, also the zones of different on a certain wafer multiple resolution chart 7 can be formed, by this Experimental Design (designofexperimental, and adopt XRR means of testing DOE), determine that the wafer of a certain product type removes totally at the false grid of polycrystalline (destructive SEM or TEM to be for print to test, choose wafer that those polycrystalline silicon dummy gate 3 are completely removed as sample) the density of resolution chart 7, also be standard pattern density, now the thickness of polycrystalline silicon dummy gate 3 should be 0.After measuring the data of multiple batches of wafer multi-disc, obtain the excursion of resolution chart 7 density.Target and error range is measured according to the above results reasonable definition wafer sort density of texture, when such as, on the wafer that DOE and XRR obtains a certain product type, polycrystalline silicon dummy gate 3 is removed completely, the density of test structure is 50%, its excursion is 5%, then judge that polycrystalline silicon dummy gate is removed completely and do not have the standard of over etching to be that test structure 7 density is as 50% ± 5%.Wherein, after DOE experiment purpose finds the false grid of polycrystalline thoroughly to remove exactly, the excursion of wafer sort density of texture.
Then, the polysilicon in polycrystalline silicon dummy gate and test structure is removed and drying.The dry etching that carbon fluorine-based plasma can be adopted to etch removes the polysilicon in polycrystalline silicon dummy gate 3 and test structure 7, also the etching liquid wet etchings such as KOH, TAMH can be adopted to remove polycrystalline silicon dummy gate 3, can also be the mixing etchings of these dry method, wet etching.The choose reasonable etching flow of raw material or concentration, air pressure etc. parameter control etching speed, and the polysilicon within preset time polycrystalline silicon dummy gate 3 and test structure 7 is etched substantially completely.Dry run can be put into insulating box to toast, or uses the inert gas such as nitrogen, argon gas to dry up.
Then, use XRR device measuring test structure 7 density, judge whether polysilicon removes completely.If the density of test structure 7 is (range of tolerable variance is determined by the 2nd step) in error range, erosion removal is clean can to think the false grid 3 of polycrystalline.If the density of many test structures 7 is not in error range, then thinks that the false grid 3 of polycrystalline are not removed clean completely, need reprocessing again, also send processing line back to by this batch sample and carry out secondarily etched.
Above embodiments of the invention by experiment property design obtain polycrystalline silicon dummy gate remove completely after variable density scope, then by the test structure density of X ray reflection testing of equipment actual product, thus judge whether polycrystalline silicon dummy gate 3 is completely removed.This test and rear grid etching remove the method for polycrystalline silicon dummy gate, avoid destructive testing mass product all being adopted to SEM or TEM, improve testing efficiency and provide cost savings.
embodiment 2
Similar to Example 1, the method that the rear grid technique according to an alternative embodiment of the invention removes polycrystalline silicon dummy gate comprises the following steps:
First, polycrystalline silicon dummy gate structure and test structure is formed at crystal column surface.As shown in Figure 1, crystal column surface is formed with polycrystalline silicon dummy gate structure, also namely forms insulating barrier 2, polycrystalline silicon dummy gate pole 3, gate lateral wall 4, interlayer dielectric layer (IDL) 5 successively on substrate 1, then removes polycrystalline silicon dummy gate pole 3, forms gate openings 6.Meanwhile, as shown in Figure 3, Figure 4, in same level, the test structure 7 of polysilicon material is formed at crystal column surface by the technique identical with forming polycrystalline silicon dummy gate.Test structure 7 shape is such as rectangle, and example can put to the proof square or rectangular structure, as long as its structure can form specific phase difference for the X ray reflection of special angle.For the square that embodiment is lifted, (long a is multiplied by and widely b) includes but not limited to 20 μm × 20 μm, 30 μm × 30m, 50 μm × 50 μm etc., see Fig. 3 size.The figure of test structure 7 is band side wall polysilicon gate, and unified with making technology, enlarged drawing is shown in Fig. 4, and also namely test structure 7 also comprises substrate 1, insulating barrier 2, gate lateral wall 4, IDL5.The pattern density of test structure 7 is defined as the ratio of width d between polysilicon gate width c and polysilicon gate (being also polysilicon gate spacing d), i.e. c/d, its density range 10%-100%, and example can put to the proof 50%; For the pattern density of 50%, the concrete size of c is as the criterion with the grid width of actual product (gateCD).Test structure 7 position can with saving chip area on the line of cut of inside wafer individual chips unit, or individual chips unit inner with the resolution chart between the different chip of personal settings to adjust for different grid widths.
Secondly, determine that thickness of insulating layer measures target and error range.Can first at the upper specifically created multiple resolution chart 7 of the wafer (being also namely not used in the wafer for subsequent use finally cutting into chip product) of test, also the zones of different on a certain wafer multiple resolution chart 7 can be formed, by this Experimental Design (designofexperimental, and adopt XRR means of testing DOE), determine that the wafer of a certain product type removes totally at the false grid of polycrystalline (destructive SEM or TEM to be for print to test, choose wafer that those polycrystalline silicon dummy gate 3 are completely removed as sample) resolution chart 7 bottom insulating barrier 2 thickness, also be standard thickness of insulating layer, now the thickness of polycrystalline silicon dummy gate 3 should be 0.After measuring the data of multiple batches of wafer multi-disc, obtain the scope of insulating barrier 2 varied in thickness.Target and error range is measured according to the above results reasonable definition wafer thickness of insulating layer, when such as, on the wafer that DOE and XRR obtains a certain product type, polycrystalline silicon dummy gate 3 is removed completely, insulating barrier 2 thickness is 15nm, its excursion is 1nm, then judge polycrystalline silicon dummy gate remove completely and do not have the standard of over etching be on wafer insulating barrier 2 thickness as 15 ± 1nm.
Then, the polysilicon in polycrystalline silicon dummy gate and test structure is removed and drying.The dry etching that carbon fluorine-based plasma can be adopted to etch removes the polysilicon in polycrystalline silicon dummy gate 3 and test structure 7, also the etching liquid wet etchings such as KOH, TAMH can be adopted to remove polycrystalline silicon dummy gate 3, can also be the mixing etchings of these dry method, wet etching.The choose reasonable etching flow of raw material or concentration, air pressure etc. parameter control etching speed, and the polysilicon within preset time polycrystalline silicon dummy gate 3 and test structure 7 is etched substantially completely.
Then, use insulating barrier 2 and polysilicon 3 thickness in XRR device measuring test structure 7, judge whether polysilicon removes completely and/or over etching occurs.If the thickness of polysilicon 3 is 0, and insulating barrier 2 thickness (range of tolerable variance is determined by the 2nd step) in error range, erosion removal is clean can to think the false grid 3 of polycrystalline, and does not have excessive erosion to occur.If polysilicon 3 thickness is 0, insulating barrier 2 thickness exceedes error range, then think generation over etching, and this batch products is scrapped.As polysilicon 3 thickness is not 0 excessively, even if measure insulating barrier 2 thickness in error range, also think that the false grid 3 of polycrystalline are removed clean completely, need reprocessing again, also send processing line back to by this batch sample and carry out secondarily etched.
According to test and the lithographic method of above second embodiment of the invention, owing to measuring insulating barrier and polysilicon thickness simultaneously, not only can convenient and swiftly determine whether accurately to remove polysilicon gate completely, can also determine whether over etching occurs simultaneously, therefore test efficiently convenient, the product yield obtained and reliability have and significantly promote.
According to measurement of the present invention and lithographic method, avoid destructive testing mass product all being adopted to SEM or TEM, improve testing efficiency and provide cost savings.In addition, can also determine whether over etching occurs simultaneously, therefore test efficiently convenient, the product yield obtained and reliability have and significantly promote.
Although the present invention is described with reference to one or more exemplary embodiment, those skilled in the art can know without the need to departing from the scope of the invention and make various suitable change and equivalents to device architecture.In addition, can be made by disclosed instruction and manyly may be suitable for the amendment of particular condition or material and not depart from the scope of the invention.Therefore, object of the present invention does not lie in and is limited to as realizing preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will comprise all embodiments fallen in the scope of the invention.
Claims (14)
1. after, grid technique removes a method for supervising for polycrystalline silicon dummy gate processing procedure, comprises the following steps:
Form polycrystalline silicon dummy gate structure and test structure at crystal column surface, described test structure and polycrystalline silicon dummy gate structure adopt same process to be produced in same horizontal plane simultaneously;
Determine test structure density measurement target and error range;
Remove the polysilicon in polycrystalline silicon dummy gate structure and test structure and drying;
Use the density of XRR device measuring test structure, judge whether polycrystalline silicon dummy gate removes completely.
2. after, grid technique removes a method for supervising for polycrystalline silicon dummy gate processing procedure, comprises the following steps:
Form polycrystalline silicon dummy gate structure and test structure at crystal column surface, described test structure and polycrystalline silicon dummy gate structure adopt same process to be produced in same horizontal plane simultaneously;
Determine that in test structure, thickness of insulating layer measures target and error range;
Remove the polysilicon in polycrystalline silicon dummy gate structure and test structure and drying; And
Use the thickness of XRR device measuring insulating barrier and polysilicon, judge whether polysilicon removes completely and/or over etching occurs.
3. as the method for claim 1 or 2, wherein, test structure and polycrystalline silicon dummy gate adopt same process to be produced in same horizontal plane simultaneously.
4. as the method for claim 1 or 2, wherein, test structure comprises insulating barrier, polysilicon, sidewall, the interlayer dielectric layer on substrate.
5. as the method for claim 1 or 2, wherein, test structure has predetermined pattern density, and this pattern density is defined as the ratio of polysilicon width and polysilicon distance.
6. as the method for claim 1 or 2, wherein, test structure be positioned at inside wafer individual chips unit line of cut on or to be positioned at individual chips unit inner.
7. as the method for claim 1 or 2, wherein, test structure is rectangle or square.
8. method as claimed in claim 7, wherein, test structure is of a size of the one in 20 μm × 20 μm, 30 μm × 30 μm, 50 μm × 50 μm.
9. as the method for claim 1 or 2, wherein, the density range of test structure is 10%-100%.
10. method as claimed in claim 9, wherein, the density range of test structure is 50%.
11. methods as claimed in claim 2, wherein, insulating barrier is high-g value.
12. methods as claimed in claim 2, wherein, insulating barrier is silica or silicon oxynitride.
13. as the method for claim 1 or 2, and wherein, property design (DOE) is in conjunction with XRR means of testing by experiment, obtains the test structure density of the sample wafer that polysilicon is completely removed and/or thickness of insulating layer and error range.
14. as the method for claim 1 or 2, wherein, if test structure density and/or thickness of insulating layer exceed error range, then judges that polysilicon is not removed completely, needs aftertreatment.
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| CN105448759A (en) * | 2014-08-19 | 2016-03-30 | 中国科学院微电子研究所 | Method for monitoring source-drain trench process |
| CN105448758A (en) * | 2014-08-19 | 2016-03-30 | 中国科学院微电子研究所 | Method for monitoring channel-etching process |
| CN105347296A (en) * | 2014-08-19 | 2016-02-24 | 中国科学院微电子研究所 | MEMS lateral etching process monitoring method |
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| CN1349247A (en) * | 2000-10-13 | 2002-05-15 | 海力士半导体有限公司 | Method for forming metallic grid |
| US6713753B1 (en) * | 2001-07-03 | 2004-03-30 | Nanometrics Incorporated | Combination of normal and oblique incidence polarimetry for the characterization of gratings |
| TW200821571A (en) * | 2006-07-27 | 2008-05-16 | Rudolph Technologies Inc | Multiple measurement techniques including focused beam scatterometry for characterization of samples |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1349247A (en) * | 2000-10-13 | 2002-05-15 | 海力士半导体有限公司 | Method for forming metallic grid |
| US6713753B1 (en) * | 2001-07-03 | 2004-03-30 | Nanometrics Incorporated | Combination of normal and oblique incidence polarimetry for the characterization of gratings |
| TW200821571A (en) * | 2006-07-27 | 2008-05-16 | Rudolph Technologies Inc | Multiple measurement techniques including focused beam scatterometry for characterization of samples |
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