CN102799131A

CN102799131A - Ground penetrating radar lower computer control system based on field programmable gate array (FPGA)

Info

Publication number: CN102799131A
Application number: CN201210280937XA
Authority: CN
Inventors: 吴斌; 赵凯; 孙健; 姜涛
Original assignee: Northeast Institute of Geography and Agroecology of CAS
Current assignee: Northeast Institute of Geography and Agroecology of CAS
Priority date: 2012-08-08
Filing date: 2012-08-08
Publication date: 2012-11-28

Abstract

The invention relates to a ground penetrating radar lower computer control system based on a field programmable gate array (FPGA), which relates to the field of the control of a ground penetrating radar. The system adopts the FPGA as a main control unit which is matched with a transmitter pulse control unit, a data sampling control unit, a sampling data receiving unit and a data communication unit to realize the control of functions such as the pulse transmission, data receiving and data transmission of a ultra-narrow pulse ground penetrating radar. The FPGA triggers a transmitter to transmit a narrow pulse through the transmitter pulse control unit; then a sampling control signal is transmitted through the data sampling control unit, and the signal is received and stored through the sampling data receiving unit; and finally after the ground penetrating radar completes once complete detection, the sampling data is transmitted to a superior computer through the data communication unit, and the superior computer conducts the subsequent data processing. The ground penetrating radar system based on the control system can be used for detecting the dielectric property and the soil moisture rate of an underground medium and can be widely applied to the fields of agriculture, geology, geological exploration and the like.

Description

GPR slave computer control system based on FPGA

Technical field

The present invention relates to GPR control field, be specifically related to a kind of GPR slave computer control system based on FPGA.

Background technology

GPR (GPR) is a kind of lossless detection instrument of surveying structure under the face of land or treasure trove.It utilizes the penetration capacity of electromagnetic wave to the face of land, launches the electromagnetic wave of particular form downwards from the face of land, through receiving underground medium scatter echo signal; Parameters such as time delay, shape and spectral characteristic according to echoed signal; The degree of depth of quantitative measurment target, dielectric structure and character, on the basis of data processing, the recovery and the reconstruction technique of Applied Digital image; Underground target is carried out imaging processing, in the hope of reaching to the true of underground target and reproduction intuitively.

Typical shock pulse ground penetrating radar system is made up of host computer and slave computer, and host computer is responsible for data processing and radar imagery, and slave computer is responsible for radar signal and is received and data transmission.Lower computer system is made up of several parts such as main control unit, transmitter, receiver, data transmission units; At present GPR be mostly with processors such as CPU or MCU as main control unit, accomplish functions such as the collection of radar from the transponder pulse to data, transmission.A kind of integrated imaging GPR is disclosed like one Chinese patent application CN99200610.4 (publication number CN2365679); Comprise automobile, emitting antenna, receiving antenna, computing machine, radar host computer, power supply; Wherein radar host computer is made up of emissive source, receiver, amplifier, signal Processing and control circuit, color monitor and input and output socket, it is characterized in that also being provided with satnav receiving trap and range finding wheel.Signal Processing in the radar host computer and control circuit are made up of CPU board, hard disk, I/0 plate, A/D and D/A plate, XY axle measurement range selection plate, VJA plate, keyboard and keyboard decoding device etc.; Be CPU during the radar slave computer uses a computer as core processor, cooperate peripheral hardware to realize the detecting function of GPR.

One Chinese patent application CN201010195736.0 (publication number CN101872018A) discloses a kind of wireless ground penetrating radar system, comprises data acquisition subsystem and GPR front terminal system.Wherein GPR front terminal system comprises battery, power regulator, ethernet controller, ARM controller, digital signal processor, analog to digital converter, digitial controller, sequential system, transmitter, emitting antenna, receiving antenna and receiver; Promptly the ARM controller that is made up of MCU of this GPR slave computer is realized the coordination and the control of radar each several part function as the main control unit of system.

Existing GPR lower computer system adopts processor as system master system device; The course of work through the software program control radar; Programming and debugging are succinct convenient, and the construction cycle is short, but the computation capability of processor is limited; Carry out different instructions under the different situations or respond interruption and can bring extra time overhead, be difficult to realize the synchronous fully and temporal accurate control of sequential.

Summary of the invention

In order to solve the problem that prior art can't realize accurately controlling the GPR work schedule; The present invention proposes a kind of GPR slave computer control system based on FPGA; This system with FPGA as main control unit; Control transmitter, receiver and the co-ordination of data communication each several part, guarantee the synchronous operation of radar system each several part.

The technical scheme that technical solution problem of the present invention is taked is following:

GPR slave computer control system based on FPGA; Comprise data communication units, FPGA main control unit, transmitter pulse control module, data sampling control module and sampled data receiving element; Data communication units is carried out serial communication through the host computer of serial 485 buses and GPR, and links to each other with the IO port of FPGA main control unit through parallel mode; The FPGA main control unit is electrically connected with transmitter pulse control module, data sampling control module, sampled data receiving element respectively through the IO port; The FPGA main control unit is accomplished the emission and the data collection task of radar signal through coordinating the duty of each unit; The transmitter pulse control module links to each other with the transmitter of GPR, and it is responsible for exomonental control signal buffering and passes to transmitter, controls transmitter circuit and produces large power narrow pulse; The data sampling control module links to each other with the sample circuit of GPR, and it is responsible for producing the sampling control signal of different delayed time, and the control sample circuit produces sampling pulse; The sampled data receiving element links to each other with the pre-amplification circuit of the receiver of GPR, and it is responsible for analog signal conversion is digital signal and passes to the FPGA main control unit.

The invention has the beneficial effects as follows: this system is a main control unit with FPGA, and computation capability is strong, can realize the accurate control of radar work schedule; System architecture is simple, is easy to realize that cost is low.This system can be used for surveying the dielectric property, soil moisture content of underground medium etc., but wide range of services is in fields such as agricultural, geographical and geologic prospects.

Description of drawings

Fig. 1 is the one-piece construction block diagram that the present invention is based on the GPR control system of FPGA;

Among the figure: 1, host computer, 2, data communication units, 3, the FPGA main control unit; 4, transmitter pulse control module, 5, the data acquisition control unit, 6, the sampled data receiving element; 7, slow ramp generating circuit, 8, sampled signal produces circuit, 9, fast ramp generating circuit; 10, transmitter, 11, sample circuit, 12, pre-amplification circuit;

Fig. 2 is the FPGA I/O pin configuration circuit theory diagrams among the present invention, and U1 is a fpga chip among the figure;

Fig. 3 is the FPGA mode of operation configuration circuit schematic diagram among the present invention, and U1 is a fpga chip among the figure, U2 be FPGA configuration to use PROM, Y1 be the FPGA external crystal-controlled oscillation, JP1 is a jtag bus configuration file download interface;

Fig. 4 is the data communication units circuit theory diagrams among the present invention, and U3 is the MCU microprocessor among the figure, and U4, U5 are 485 serial interface chips, and P1 is a MCU program download interface, and JP2 is 485 EBIs;

Fig. 5 is the slow ramp generating circuit schematic diagram among the present invention, and U7 is a D/A converter among the figure, and D2 is outside input reference voltage, and U11 is an operational amplifier;

Fig. 6 is the fast ramp generating circuit schematic diagram among the present invention, and U10 is an operational amplifier among the figure;

Fig. 7 is that the sampled signal among the present invention produces circuit theory diagrams, and U8 is a comparer among the figure;

Fig. 8 is the transmitter pulse control unit circuit schematic diagram among the present invention, and U9 is the CMOS phase inverter among the figure;

Fig. 9 is the sampled data receiving element circuit theory diagrams among the present invention, and U6 is an A/D converter among the figure;

Figure 10 is the workflow diagram that the present invention is based on the GPR control system of FPGA.

Embodiment

Below in conjunction with accompanying drawing and embodiment the present invention is explained further details.

As shown in Figure 1, the GPR slave computer control system that the present invention is based on FPGA comprises: data communication units 2, FPGA main control unit 3, transmitter pulse control module 4, data sampling control module 5 and sampled data receiving element 6.Host computer 1 carries out serial communication through serial 485 buses and data communication units 2; 2 of data communication units are connected with the IO port of FPGA main control unit 3 through parallel mode; FPGA main control unit 3 is electrically connected with transmitter pulse control module 4, data sampling control module 5, sampled data receiving element 6 respectively through IO port on the sheet; FPGA main control unit 3 is accomplished the emission and the data collection task of radar signal through coordinating the duty of each unit.Transmitter pulse control module 4 links to each other with transmitter 10, is responsible for exomonental control signal buffering and passes to transmitter 10, controls transmitter circuit and produces large power narrow pulse; Data sampling control module 5 produces circuit 8 by slow ramp generating circuit 7, fast ramp generating circuit 9 and sampled signal to be formed, and is connected with sample circuit 11, is responsible for producing the sampling control signal of different delayed time, control sample circuit 11 generation sampling pulses; Sampled data receiving element 6 is connected with the pre-amplification circuit 12 of receiver, is responsible for analog signal conversion is digital signal and passes to FPGA main control unit 3.

Embodiment 1:

FPGA main control unit 3 is like Fig. 2, shown in Figure 3, and U1 wherein is the fpga core chip, adopts the XC3S250E of Xilinx company, and the core work frequency is set by external crystal-controlled oscillation Y1, and the Y1 frequency is 50MHz; FPGA adopts the mode of operation of configuration automatically that powers on; U2 among Fig. 3 is the PROM of storage FPGA configuration file; The standard configuration chip XCF02SVO20C that adopts the Xilinx FPGA of company to use; PROM is connected with PC through jtag bus JP1, through PC configuration file is downloaded among the PROM and stores.When system initially powered on, FPGA read configuration file automatically from PROM, and self internal hardware is configured, and FPGA got into normal mode of operation automatically after configuration was accomplished, and radar system is started working.

Data communication units 2 is as shown in Figure 4, and U3 is the MCU processor that works alone among the figure, adopts the ATmega8L-8PC single-chip microcomputer, and the core work frequency is provided with by crystal oscillator Y2, and the Y2 frequency is 8MHz, and P1 is a MCU program download port; U4 and U5 constitute 485 EBIs, and single-chip microcomputer U3 communicates with serial mode and host computer (PC) 1 through U4, U5.Adopt parallel mode to be connected between single-chip microcomputer U3 and the FPGA; IO port PB1 ~ PB5 of single-chip microcomputer U3, PD2 ~ PD5, PC0 ~ PC5 are connected with IO port P53 ~ P78 of FPGA respectively; Wherein the IO port PB1 of single-chip microcomputer U3 (P53 that connects FPGA) is used for being the FPGA Global reset; PB2 (P54 that connects FPGA) is as the data transfer request port; PB3 (connect FPGA P57) is used for notifying the data on the single-chip data bus effective as the data latching port of FPGA, PB4 ~ PC5 (connect FPGA P58 ~ P78) 12 IO ports constitute 12 bit data bus, are used for transmitting 12 radar sampled datas.When host computer 1 need carry out data transmission; Send the data transfer request order through serial 485 buses, single-chip microcomputer U3 receives order back enable port PB2, after FPGA accomplishes current one whole data sampling; Detect data transfer request through the P54 pin; Get into the data transmission mode of operation, concurrently the data order is loaded on 12 bit data bus, and in loading data, enables the P57 pin.Single-chip microcomputer sends to host computer 1 through 485 buses with the data order after receiving the data of FPGA.

Data sampling control module 5 produces circuit 8 by slow ramp generating circuit 7, fast ramp generating circuit 9 and sampled signal and forms.Wherein, slow ramp generating circuit 7 is as shown in Figure 5, and U7 is D/A converter MAX532; Digital control input end is connected with P3 ~ P5, the P9 pin of FPGA respectively, and the different comparative level of output under the control of FPGA is simulated VOUTA (pin 3) output of slow ramp signal by MAX532; The slow ramp signal of D/A output inserts U11 (LM124); U11 is an operational amplifier, is connected into the voltage follower form, is used for D/A is isolated and impedance conversion; The output of U11 inserts sampled signal and produces in the comparer in the circuit, and is as shown in Figure 7; Fast ramp generating circuit 9 is as shown in Figure 6, and U10 (OP07) is the low frequency operational amplifier, is connected into the form of follower; Effect is the static working current of isolating Q2 and Q3, and Q2 is positive-negative-positive switching transistor 2N4036, and effect is for on-off circuit electric current to be provided; Q3 is NPN type switching transistor 3DK4, is used for controlling the charge and discharge process of integrating capacitor C26, and fast oblique wave control signal is by the P2 pin output of FPGA; Insert the Q3 base stage through capacitance C13 and current-limiting resistance R20, Q3 conducting during high level, C26 discharge; Q3 ends during low level, and the C26 charging forms fast ramp signal.Fast ramp signal is through capacitance C28, and the comparer U8 that produces in the circuit 8 with sampled signal is connected, and is as shown in Figure 7; It is as shown in Figure 7 that sampled signal produces circuit 8; U8 is comparer LM319; Slowly, fast ramp voltage inserts comparer U8 from

4,5 respectively, when fast ramp voltage surpasses slow ramp voltage, output low level; The control signal upset that switching transistor Q1, Q4 (3DK4) are responsible for that respectively comparer U8 is produced reaches to signal output provides current drives, and sampling control signal is exported through capacitance C24 from the emitter of Q4.

Transmitter pulse control module 4 is as shown in Figure 8, and pulse control signal inserts the pin 1 of COMS phase inverter U9 (74HC04) by the P23 pin output of FPGA, and through after the anti-phase, from pin 2 outputs.Because the input end of transmitter 10 is an inductive load; Direct current input impedance is low; Therefore; The pulse control signal of FPGA output is connected with transmitter 10 through phase inverter U9, and the effect of phase inverter U9 is that the IO port of FPGA and transmitter 10 input ends are isolated, and prevents that the big electric current of transmitter 10 input ends from burning out the IO port of FPGA.

Sampled data receiving element 6 is as shown in Figure 9; The sampled data of radar signal is after the pre-amplification circuit 12 of receiver amplifies; Insert A/D converter U6, U6 is a digital signal with the sampled analog conversion of signals under the sequential control of FPGA, and is received by FPGA through serial mode.Specifically: the digital

control end pin

11,15,18 ~ 20 of 12 A/D converter U6 (AD7866) is connected with P91, P90, the P86 ~ P84 of FPGA respectively; The sampled analog signal inserts the VA1 input end (pin 7) of A/D converter; The mode of operation of A/D converter is elected input voltage range 0 ~ 5V as, uses the A/D internal reference voltage.FPGA reads in FPGA and stores from the pin DoutA of the A/D converter data after with the A/D conversion through serial mode.

The workflow of FPGA control system is shown in figure 10, and the back FPGA that powers on carries out initialization to system, the internal register zero clearing that resets; Promptly get into normal mode of operation afterwards; FPGA has two kinds of mode of operations, is respectively radar detection mode of operation (step 2) and data transmission mode of operation (step 3), and radar start back workflow circulates always and carries out; And switch between two kinds of duties according to host computer instruction, concrete workflow is following:

Step 1, FPGA at first detect the sampled data request that whether has host computer 1 to send: if host computer 1 does not send request of data; Then get into the radar detection mode of operation (in fact; Owing to need preheating and steady-working state after the radar start; Host computer can not send request of data 1 this moment, so promptly get into the radar detection mode of operation after the radar start), promptly get into step 2; If host computer 1 has the request of data of transmission, then get into the data transmission mode of operation, and the sampled result of last radar is sent to host computer 1, promptly get into step 3;

Step 2, master control system are under the radar detection mode of operation, and the first step is at first upgraded the output of D/A converter U7, produces slow oblique wave; Second step, send fast oblique wave trigger pip, produce fast oblique wave, the speed oblique wave promptly produces the sampling control signal of different delayed time through comparer U8; In the 3rd step, radar sends the transmitter pulse control signal, triggers transmitter 10 emission burst pulses; In the 4th step, control A/D converter U6 carries out analog to digital conversion to sampled data; The 5th step, with the radar return data storage of current collection in internal storage; The 6th step; Whether detect according to default the finishing collecting all of the sampled point in all different times time-delays; If not do not gathered then repeated for first to the 5th step, if finishing collecting is then jumped out the detection operations pattern; Turn back to step 1, detect the request of data that whether has host computer 1 to send again;

Step 3, master control system are under the data transmission mode of operation, and the first step is read sampled data according to current sequence of addresses from storer, and sends to host computer 1 through serial mode; In second step, all data that detect whether this sampling have all been sent and have been finished, if sent; Then repeat the first step, after the whole transmissions of the data of all sampled points finished, FPGA jumped out data-transmission mode; Whether turn back to step 1, detecting host computer 1 again has request of data (in fact, because host computer 1 can not send data transfer request continuously; Therefore after radar is accomplished a data transfer, get into the radar detection mode of operation once) to I haven't seen you for ages.

Claims

1. based on the GPR slave computer control system of FPGA; It is characterized in that; This system comprises data communication units (2), FPGA main control unit (3), transmitter pulse control module (4), data sampling control module (5) and sampled data receiving element (6); Data communication units (2) is carried out serial communication through the host computer (1) of serial 485 buses and GPR, and links to each other with the IO port of FPGA main control unit (3) through parallel mode; FPGA main control unit (3) is electrically connected with transmitter pulse control module (4), data sampling control module (5), sampled data receiving element (6) respectively through the IO port; FPGA main control unit (3) is accomplished the emission and the data collection task of radar signal through coordinating the duty of each unit; Transmitter pulse control module (4) links to each other with the transmitter (10) of GPR, and it is responsible for exomonental control signal buffering and passes to transmitter (10), controls transmitter circuit and produces large power narrow pulse; Data sampling control module (5) links to each other with the sample circuit (11) of GPR, and it is responsible for producing the sampling control signal of different delayed time, and control sample circuit (11) produces sampling pulse; Sampled data receiving element (6) links to each other with the pre-amplification circuit (12) of the receiver of GPR, and it is responsible for analog signal conversion is digital signal and passes to FPGA main control unit (3).

2. the GPR slave computer control system based on FPGA as claimed in claim 1; It is characterized in that; Said data sampling control module (5) produces circuit (8) by slow ramp generating circuit (7), fast ramp generating circuit (9) and sampled signal and forms; Slow ramp generating circuit (7), fast ramp generating circuit (9) all produce circuit (8) with sampled signal and link to each other, and slow ramp generating circuit (7) produces slow oblique wave, and fast ramp generating circuit (9) produces fast oblique wave; Sampled signal produces circuit (8) and links to each other with sample circuit (11), and it drives sample circuit (11) and produce sampling pulse through the sampling control signal of relatively exporting different delayed time of slow oblique wave, fast oblique wave.