CN102789521A - Method and system for verifying integrated circuit pipeline design, and model implementation method of integrated circuit pipeline - Google Patents
Method and system for verifying integrated circuit pipeline design, and model implementation method of integrated circuit pipeline Download PDFInfo
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Abstract
The invention discloses a method for verifying the integrated circuit pipeline design by adopting pipeline models. According to the method, the completeness and the correctness of the pipeline models are firstly verified and the integrated circuit pipeline design is verified after the pipeline models pass the verification; in the verifying process of the pipeline models, the verification is carried out by pre-designing each stage of flow state assertion and then detecting a state value output by each stage of flow in real time so as to judge whether violation assertion occurs; and once the design of the pipeline models has a fault, the condition of the violation assertion can be generated, so that each stage of flow and model units, which are related to a model unit in flow with the violation assertion, can be directly verified, i.e. the positions with faults are directly positioned into the model units of a certain stage of specific flow or a plurality of stages of flow without verifying all the units in all the pipeline model, and thus, the error correcting efficiency is improved.
Description
Technical field
The application relates to IC design and checking field, is specifically related to integrated circuit The pipeline design verification method, system and model implementation method thereof.
Background technology
The scale of IC design and complexity are promoting gradually; Find that as early as possible the problem that exists in the design can effectively reduce design cost; Therefore in the Front-end Design of IC design, hardware designs carried out the Modeling and Design of function and performance; To adjust design architecture in advance, the correctness through the correctness of checking Modeling and Design thinking and objective function understanding comes validation integrated circuit to design has become an indispensable step in the large-scale IC design link.
The integrated circuit The pipeline design mainly comprises streamline RTL (register transfer level) design, in the streamline RTL of complicacy design, also can design pipeline control unit usually and manage flowing water at different levels.Pipeline control unit mainly is responsible for multi-cycle instructions, is write the read conflict instruction, the streamline management of interruption and multiple situation such as unusual, and the register of flowing water at different levels unit freezes and refreshes on the pipeline.
Therefore; The checking of adopting modeling pattern to carry out to the RTL design of integrated circuit The pipeline design comprises: set up and the corresponding pipeline model of streamline RTL design; Pipeline model is made up of the flowing water unit; When having the RTL design of pipeline control unit, the also corresponding model that comprises pipeline control unit of this pipeline model.Its verification mode is: guaranteeing that under the correct prerequisite of pipeline model, the RTL of pipeline design simultaneously and pipeline model are imported same excitation, whether the output of comparing both unit at different levels is consistent, explains then that as if inconsistent the RTL design of streamline makes mistakes.
From the above, before the RTL design that utilizes pipeline model validation integrated circuit The pipeline design, need the correctness and the completeness of pipeline model to verify.But must simultaneous verification in the prior art whole unit in the pipeline model make mistakes part and carry out error correction confirming, so error correction efficient is lower.
Summary of the invention
The application provides a kind of method that adopts pipeline model that the integrated circuit The pipeline design is verified; Said pipeline model comprises the water unit of confirming according to the integrated circuit The pipeline design of secondary streams at least; At least comprise a model unit in every grade of flowing water unit, each model unit comprises:
Back end interface is used to receive state value and the logical value that previous stage flowing water unit is exported;
Front-end interface is used for the state value and the logical value of this model unit are outputed to the next stage model unit;
Functional unit, the logical value that is used for that back end interface is sent is carried out power function computing and output logic value;
The internal control unit; Comprise controller and state processing unit; Said controller is selected signal according to back end interface data sent and the steering logic output of itself, said state processing unit according to back end interface data sent and the state processing logic output state value of itself to front-end interface;
Selected cell according to the selection signal of controller output, is selected one and is exported front-end interface in the logical value of reset values, set value and the laststate of the logical value of functional unit output, this model unit;
Said method comprises:
The completeness and the correctness of checking pipeline model;
After the pipeline model checking is passed through, utilize the correctness of this pipeline model checking The pipeline design;
The completeness and the correctness of said checking pipeline model may further comprise the steps:
In the pipeline model state of each model unit and between relation state, and design flowing water states at different levels in advance and assert;
Survey routine generator and produce the checking excitation, and will verify that according to time sequencing excitation sends to pipeline model, said checking excitation comprises logical value and state value;
The first order flowing water of pipeline model receives surveys the checking excitation that routine generator produces, and carries out computing according to the checking excitation, and logical value that output is at the corresponding levels and state value are to second level flowing water;
Second level flowing water carries out computing according to the logical value and the state value of the output of upper level flowing water, exports logical value at the corresponding levels and state value to next stage flowing water; The rest may be inferred;
Detect in real time the state value of flowing water outputs at different levels, assert that according to the flowing water state of design in advance the pipeline model carries out state and asserts and judge whether judgements the phenomenon of asserting to occur violating,, think that pipeline model is through verifying if then send report.
Further, the state value that the flowing water at different levels that detect are in real time exported carries out buffer memory, asserts that according to the flowing water state of design in advance the pipeline model carries out state and asserts that determining step comprises:
Assert the crowd that from the flowing water state of design in advance the reading flow water state is asserted in order;
Read from the state value of the flowing water at different levels output of buffer memory that current flowing water state relates in asserting certain grade or the state value of some grade flowing water are judged;
When judge to occur violating the phenomenon of asserting, then send report, assert and judge that the flowing water state is asserted to read and finished in the flowing water state is asserted the crowd otherwise continue to read next bar flowing water state.
Further, when occurring violating the phenomenon of asserting, then carry out following steps:
Respectively the model unit steering logic and the upper level output unit that produce current flowing water state are verified.
In addition, the application also provides a kind of implementation method of integrated circuit pipeline model, and it comprises:
The analog hardware method of operation is that the boundary divides model unit with the register; With the logical partitioning between one or more levels the register of current register and its front is a model unit; Wherein, Power function computing in the combinational logic puts under in the functional unit of model unit; Selection in the combinational logic and steering logic put under in the selected cell and controller of model unit, and the processing cycle in the sequential logic puts the internal drive unit under;
Design connects into secondary flowing water at least with the flowing water unit according to the integrated circuit pipeline series, constitutes the integrated circuit pipeline model.
Further, above-mentioned implementation method also comprises:
Adopt the drive clock of external drive unit as each flowing water unit of pipeline model; In each set inside internal drive unit, flowing water unit, said internal drive unit is according to the clock period of reception of this flowing water unit and transmission data, the clock signal that the drive clock signal Processing cost flowing water unit that the external drive unit is exported needs.
Simultaneously, the application also provides a kind of integrated circuit The pipeline design verification system, and it comprises: the water unit of secondary streams at least according to the integrated circuit The pipeline design is confirmed, comprise a model unit in every grade of flowing water unit at least, and each model unit comprises:
Back end interface is used to receive state value and the logical value that previous stage flowing water unit is exported;
Front-end interface is used for the state value and the logical value of this model unit are outputed to the next stage model unit;
Functional unit, the logical value that is used for that back end interface is sent carry out multiple power function computing and export a plurality of logical values;
The internal control unit; Comprise controller and state processing unit; Said controller is selected signal according to back end interface data sent and the steering logic output of itself, said state processing unit according to back end interface data sent and the state processing logic output state value of itself to front-end interface; With
Selected cell according to the selection signal of controller output, is selected one and is exported front-end interface in the logical value of reset values, set value and the laststate of a plurality of logical values of functional unit output, this model unit;
Survey routine generator, be used for producing the checking excitation, and will verify that according to time sequencing excitation sends to pipeline model, said checking excitation comprises logical value and state value;
State is asserted the unit, be used for each model unit of pipeline model state and between relation state, and design flowing water states at different levels and assert;
The state judging unit; Be used for detecting in real time the state value of flowing water outputs at different levels; Assert that according to state the state of unit asserts that the pipeline model carries out state and asserts judgement, then send report, think that pipeline model is through checking if the phenomenon of asserting occurs violating.
Further, said system also comprises:
State storage unit is used for the state value that buffer memory flowing water at different levels are exported;
Said state judging unit comprises:
State reads subelement, is used for reading state and asserts that the state of the flowing water at different levels that the unit designs in advance asserts, also is used for certain grade or the state value of some grade flowing water from the state that state storage unit reads current flowing water is asserted, relating to;
The state judgment sub-unit is used for asserting certain grade or the state value of some grade flowing water that relates to according to the state that state reads the state of asserting of the flowing water at different levels that subelement reads, current flowing water, asserts judgement;
Status report subelement: be used for when the state judgment sub-unit judges that the phenomenon of asserting is violated in appearance, then sending report.
Further, said pipeline model also comprises:
Pipeline control unit is used on the overall situation control pipeline model selection of each model unit logical value and state value and exports.
Further, said model unit also comprises:
Buffer unit is used at said functional unit calculating process storage space being provided; The intermediate value that comprises the buffer memory calculating process perhaps according to the processing cycle of model unit, is stored the operation result of intercycle.
Further, said pipeline model also comprises:
The external drive unit is as the drive clock of each flowing water unit of pipeline model;
Said model unit also comprises:
The internal drive unit according to the drive signal of external drive unit, calculates the time that front-end interface and back end interface transmit and receive data in this model unit, drives said front-end interface and back end interface and accomplishes and send and the reception task.
The application's beneficial effect is: at first the completeness and the correctness of pipeline model verify that pipeline model can come the validation integrated circuit The pipeline design after verifying and passing through in the application's validation integrated circuit The pipeline design.And in the checking of this pipeline model, assert through designing flowing water states at different levels in advance, secondly in real time detect state value of flowing water outputs at different levels, and then judge whether to occur violating and assert and verify.Situation about asserting can appear violating in case the design of pipeline model makes mistakes; Like this then can directly verify with violate the flowing water of asserting in relevant flowing water at different levels and the model unit of model unit; The place that promptly directly will make mistakes navigates in the model unit of concrete certain grade or some grade flowing water; Need not verify whole unit of all pipeline models, improve error correction efficient.
Description of drawings
The implementation method process flow diagram of the pipeline model that Fig. 1 provides for embodiment;
The pipeline model structural representation that Fig. 2 provides for embodiment;
The model unit structural representation that Fig. 3 provides for embodiment;
The internal drive unit application synoptic diagram that Fig. 4 provides for embodiment;
The completeness and the correctness process flow diagram of the checking pipeline model that Fig. 5 provides for embodiment;
The completeness of the checking pipeline model that Fig. 6 provides for embodiment and the instance graph of correctness;
Verification environment synoptic diagram and the oscillogram of utilizing pipeline model checking streamline RTL design that Fig. 7 provides for embodiment;
The system schematic of utilizing pipeline model that the integrated circuit The pipeline design is verified that Fig. 8 provides for embodiment.
Embodiment
Combine accompanying drawing that the present invention is done further explain through embodiment below.
Among the application, the pipeline model that is used for the validation integrated circuit The pipeline design comprises multistage flowing water unit, comprises a plurality of model units in every grade of flowing water unit, and present embodiment is at first described the implementation method of this pipeline model, sees also Fig. 1, and this method comprises:
S101: the analog hardware method of operation is that the boundary divides model unit with the register.With the logical partitioning between one or more levels the register of current register and its front is a model unit; Wherein, Power function computing in the combinational logic puts under in the functional unit of model unit; Selection in the combinational logic and steering logic put under in the selected cell and controller of model unit, and the processing cycle in the sequential logic puts the internal drive unit under.
S102: design connects into multistage flowing water with the flowing water unit according to the integrated circuit pipeline series, constitutes the integrated circuit pipeline model.
After accomplishing above basic step, also be included as this pipeline model flowing water at different levels unit drive signal is provided, that is:
S103: adopt the drive clock of external drive unit as each flowing water unit of pipeline model; In each set inside internal drive unit, flowing water unit, the internal drive unit is according to the clock period of reception of this flowing water unit and transmission data, the clock signal that the drive clock signal Processing cost flowing water unit that the external drive unit is exported needs.
Pipeline model in the present embodiment please refer to Fig. 2; Three grades of flowing water have been divided among Fig. 1; At least comprise a model unit in every grade of flowing water unit; Each model unit representes that wherein, model unit 1_A model unit 1_B model unit 1_C is first order pipeline register model (first order flowing water unit) with model unit 1_A to model unit 3_C; Model unit 2_A model unit 2_B is second level pipeline register model (flowing water unit, the second level), and model unit 3_A model unit 3_B model unit 3_C is third level pipeline register model (third level flowing water unit).To the external drive unification of these register models (flowing water unit) by the clock driver element.Simultaneously, Fig. 2 has also preset pipeline control unit control, and this pipeline control unit control can be used for the selection output of each model unit logical value on the overall situation control pipeline model.
Fig. 3 is the structural representation (Fig. 3 shows the reception and distribution path 200 that is used between the model unit receiving with distributing data simultaneously) of model unit 100, and it comprises: back end interface 101, front-end interface 102, internal drive unit 103, internal control unit 104, functional unit 105, selected cell 106 and buffer unit 107.
Back end interface 101 is used to receive state value and the logical value that previous stage flowing water unit is exported.
Front-end interface 102 is used for the state value and the logical value of this model unit are outputed to the next stage model unit.
As shown in Figure 3; Clock driver element 40 is the external drive unit; It provides driving events for model unit 100, can react to the driving events of clock driver element 40 in internal drive unit 103, drives the transmission and the reception of front-end interface 102,101 pairs of data of back end interface according to demand.Such as; The time that is designed to two cycles when this model unit 100 just can be finished computing; And clock driver element 40 is when being normal clock signal; Internal drive unit 103 need carry out frequency division to the external clock drive signal, thereby makes model unit 100 handle each data of receiving, result is sent after two clock period again.
Inner driver element is done further introduction in detail; See also Fig. 4; The functional specification of supposing whole integrated circuit is defined as maximum 900 cycles completion (cycle is represented with cycle among Fig. 4); Set is decomposed to whole integrate circuit function, is divided into function subset and closes that A, function subset close B, function subset closes C, is defined in respectively in preceding 350 cycles in 900 cycles, in middle 100 cycles, in last 450 cycles.Respectively the function subset after dividing is closed and carry out modeling, substitute with model unit, i.e. model unit A, model unit B, model unit C.Phase is exported a clock signal to each model unit weekly in the external drive unit.Model unit is through the output of internal drive unit controls effective value, i.e. effective value of per 350 cycles output of model unit A, effective value of per 100 cycles output of model unit B, per 450 cycles of model unit C are exported an effective value.The modeling of model unit belongs to flowing structure, for example gets into model unit A at the 1st cycle the first stroke valid data, and the first stroke data are exported the 350th cycle after model unit A handles.The 2nd cycle, second valid data got into model unit A, and second data exported the 351st cycle after model unit A handles.Further refinement; With model unit C; Resolve into the more cellular construction of small grain size; Be model unit C_1, model unit C_2, model unit C_3, model unit C_4, model unit C_5, through its internal drive unit separately, regulate its effective value and be output as 200 cycles, 200 cycles, 300 cycles, 100 cycles, 50 cycles respectively.This process model unit A and model unit B do not need to change, and only revising model unit C just can directly operation on original platform.And, can guarantee model unit C_1, model unit C_2, model unit C_3, model unit C_4, the combination of model unit C_5 and the consistance of model unit C function by model unit C model as a reference to the correctness of model unit C thinning process.
Internal control unit 104; Comprise controller 104a and state processing unit 104b; Controller 104a selects signal according to back end interface 101 data sent and the steering logic output of itself, state processing unit 104b according to back end interface 101 data sent and the state processing logic output state value of itself to front-end interface 102.
When model unit 100 outsides were connected to pipeline control unit, outside pipeline control unit was higher than internal control unit 104 on control.As shown in Figure 3; Pipeline control unit 50 is higher than internal control unit 104 on control; Generally with the steering logic of model unit 100 normalities (by normal condition operation) as internal control, with the steering logic of model unit 100 anomalous modes (for example occur anomalous event needs interim interrupt original running status carry out other incidents) as external control (this external control is by pipeline control unit 50 execution).
Functional unit 105, the logical value that is used for that back end interface 101 is sent is carried out power function computing and output logic value.Functional unit 105 disposes a plurality of power functions, and its operation result will be issued selected cell 106 as one of current output logic value option of this model unit.Functional unit 105 shown in Figure 3 comprises n power function, and the data parameter that needs during the power function computing obtains from back end interface 101.In one embodiment, which power function functional unit 105 selects carry out computing, can confirm according to the control signal of controller.In another kind of embodiment, functional unit 105 also can be exported a plurality of logical values to the computing through a plurality of power functions of the parameter that obtains from back end interface 101, is follow-uply selected in a plurality of logical values of output by selected cell 106.
Selected cell 106 is used for the selection signal according to controller 104a output, in the logical value of reset values, set value and the laststate of a plurality of logical values of functional unit 105 outputs, this model unit, selects one and exports front-end interface 102 to.
Buffer unit 107 is used at functional unit 105 calculating processes storage space being provided; The intermediate value that comprises the buffer memory calculating process perhaps according to the processing cycle of model unit 100, is stored the operation result of intercycle.
In addition, Fig. 3 has also comprised reception and distribution path 200, is used to Data Receiving and distribution path between each model unit, and its front and back end interface (102,101) through each correlation model unit of connection forms.
The method that adopts above-mentioned pipeline model that the integrated circuit The pipeline design is verified.
See also Fig. 5, this method comprises: the completeness and the correctness of checking pipeline model; After the pipeline model checking is passed through, utilize the correctness of this pipeline model validation integrated circuit The pipeline design.
The completeness and the correctness of checking pipeline model may further comprise the steps:
S210: in the pipeline model state of each model unit and between relation state, and design flowing water states at different levels in advance and assert.
S220: survey routine generator and produce the checking excitation, and will verify that according to time sequencing excitation sends to pipeline model, said checking excitation comprises logical value and state value.
S230: the first order flowing water of pipeline model receives surveys the checking excitation that routine generator produces, and carries out computing according to the checking excitation, and logical value that output is at the corresponding levels and state value are to second level flowing water.
S240: second level flowing water carries out computing according to the logical value and the state value of the output of upper level flowing water, exports logical value at the corresponding levels and state value to next stage flowing water; The rest may be inferred.
S250: the state value that detects flowing water outputs at different levels in real time; Assert that according to the flowing water state of design in advance the pipeline model carries out state and asserts judgement; Judge whether the phenomenon of asserting to occur violating,, think that pipeline model is not through checking if then send report.
The state value of the flowing water outputs at different levels that also will detect in real time among the above-mentioned steps S250 more specifically, carries out buffer memory.Simultaneously, the flowing water state that designs in advance of above-mentioned basis asserts that the pipeline model carries out state and asserts that the step of judging comprises:
(1) asserts the crowd that from the flowing water state of design in advance the reading flow water state is asserted in order.
(2) read from the state value of the flowing water at different levels output of buffer memory that current flowing water state relates in asserting certain grade or the state value of some grade flowing water are judged.
(3) when judge to occur violating the phenomenon of asserting, then send report, assert and judge that the flowing water state is asserted to read and finished in the flowing water state is asserted the crowd otherwise continue to read next bar flowing water state.
When occurring violating the phenomenon of asserting among the step S250, then carry out following steps:
Respectively the model unit steering logic, the upper level output unit that produce current flowing water state are verified.
Because current flowing water state is by steering logic, the two decision of upper level output unit (for example going up a model unit) of this model unit self; If pipeline model also comprises the words of pipeline control unit; Current flowing water state also comprises by the pipeline control unit three and determining jointly; Therefore only need above the two or three are revised, and checking gets final product again.
Please refer to Fig. 6, shown in Figure 6 is the completeness of checking pipeline model and an instance of correctness.Wherein the clock driver element is clk, and the internal drive unit keeps the driven nature of clock driver element constant, and promptly inner transceive data also is a clock period.Each model unit comprises model units such as ad_i_mem, i_mem_out, pc_creg, IF_reg, ID_reg, EX_reg in the pipeline model.Pipeline control unit comprises if_flush, id_flush etc., and the logical value of its generation can be controlled the state value of ad_i_mem, i_mem_out, pc_creg, IF_reg, ID_reg, EX_reg.For example, when the if_flush logical value is high, can make the state value of IF_reg become 0 state; When the if_flush logical value was low, IF_reg accepted the state value of the state value of upper level model unit input as oneself, spread out of behind the maintenance one-period.When the id_flush logical value is high, can make the state value of ID_reg become 0 state, the state value that ID_reg accepts the input of upper level model unit when low spreads out of behind the maintenance one-period as own state value.Assert that as state the state_assert_branch of unit has asserted the state of EX_reg model unit; If run into the BZ state and redirect taken place; Two states after the BZ are necessary for 0 state so; And the EX_reg model unit is not closelyed follow two 0 states with this understanding in the actual pipeline model, so state asserts that the unit sends the mistake generation that violation is asserted.Can adjust the steering logic of pipeline control unit according to status error this moment, and need not be concerned about the concrete logical value that model unit produces in the pipeline model.
Through state value the part of makeing mistakes of The pipeline design is positioned to after certain concrete unit, just can revises, can continue if necessary to verify as stated above, till no longer makeing mistakes to this unit of makeing mistakes.Then with pipeline model and streamline RTL design compare, relatively in same checking excitation down, whether the logical value of both output consistent, verifies the correctness that streamline RTL designs, i.e. the correctness of validation integrated circuit The pipeline design.
Shown in Figure 7 for utilizing the verification environment synoptic diagram and the oscillogram of pipeline model checking streamline RTL design, wherein the waveform of each model unit is represented with model unit 1_A, model unit 2_B, model unit 3_C respectively in the pipeline model; The waveform of each register of streamline RTL design is represented with Reg_1_A, Reg_2_B, Reg_3_C.When checking pipeline model and pipeline control unit RTL design; Survey routine generator and produce the checking excitation; Be loaded into simultaneously on streamline RTL each register of design and each model unit of pipeline model, each model unit of pipeline model and each register of streamline RTL design are controlled in pipeline control unit and pipeline control unit RTL design respectively.Each model unit of pipeline model and pipeline control unit have been accomplished the state verification among Fig. 6 before; This verification environment is used for contrasting the modeling structure of integrated circuit The pipeline design and the output logic value that RTL designs corresponding unit; The comparison check of completion logic value, thereby the correctness of checking streamline RTL design (comprising pipeline control unit RTL).
The system that adopts above-mentioned pipeline model that the integrated circuit The pipeline design is verified sees also Fig. 8, and this system mainly comprises:
Survey routine generator Z100, be used for producing the checking excitation, and will verify that according to time sequencing excitation sends to pipeline model, said checking excitation comprises logical value and state value.
State is asserted unit Z200, be used for each model unit of pipeline model state and between relation state, and design flowing water states at different levels and assert.
State judging unit Z300; Be used for detecting in real time the state value of flowing water outputs at different levels; Assert that according to state the state of unit asserts that the pipeline model carries out state and asserts judgement, then send report, think that pipeline model is through checking if the phenomenon of asserting occurs violating.
Be the better scheme that realizes present embodiment, said system also comprises:
State storage unit Z400 is used for the state value that buffer memory flowing water at different levels are exported.
State judging unit Z300 is subdivided into a plurality of subelements simultaneously, specifically comprises:
State reads subelement Z310, is used for reading state and asserts that the state of the flowing water at different levels that the unit designs in advance asserts, also is used for certain grade or the state value of some grade flowing water from the state that state storage unit reads current flowing water is asserted, relating to.
State judgment sub-unit Z320 is used for asserting certain grade or the state value of some grade flowing water that relates to according to the state that state reads the state of asserting of the flowing water at different levels that subelement reads, current flowing water, asserts judgement.
Status report subelement Z330: be used for when the state judgment sub-unit judges that the phenomenon of asserting is violated in appearance, then sending report.
Utilize the completeness and the correctness of said system pipeline model to verify, after the checking of pipeline model design itself is passed through, can be used for verifying streamline RTL design, its verification mode is please with reference to above-mentioned description about Fig. 7.
Above content is to combine concrete embodiment to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace.
Claims (10)
1. method that adopts pipeline model that the integrated circuit The pipeline design is verified; Said pipeline model comprises the water unit of confirming according to the integrated circuit The pipeline design of secondary streams at least; At least comprise a model unit in every grade of flowing water unit, each model unit comprises:
Back end interface is used to receive state value and the logical value that previous stage flowing water unit is exported;
Front-end interface is used for the state value and the logical value of this model unit are outputed to the next stage model unit;
Functional unit, the logical value that is used for that back end interface is sent is carried out power function computing and output logic value;
The internal control unit; Comprise controller and state processing unit; Said controller is selected signal according to back end interface data sent and the steering logic output of itself, said state processing unit according to back end interface data sent and the state processing logic output state value of itself to front-end interface;
Selected cell according to the selection signal of controller output, is selected one and is exported front-end interface in the logical value of reset values, set value and the laststate of the logical value of functional unit output, this model unit;
It is characterized in that said method comprises:
The completeness and the correctness of checking pipeline model;
After the pipeline model checking is passed through, utilize the correctness of this pipeline model checking The pipeline design;
The completeness and the correctness of said checking pipeline model may further comprise the steps:
In the pipeline model state of each model unit and between relation state, and design flowing water states at different levels in advance and assert;
Survey routine generator and produce the checking excitation, and will verify that according to time sequencing excitation sends to pipeline model, said checking excitation comprises logical value and state value;
The first order flowing water of pipeline model receives surveys the checking excitation that routine generator produces, and carries out computing according to the checking excitation, and logical value that output is at the corresponding levels and state value are to second level flowing water;
Second level flowing water carries out computing according to the logical value and the state value of the output of upper level flowing water, exports logical value at the corresponding levels and state value to next stage flowing water; The rest may be inferred;
Detect in real time the state value of flowing water outputs at different levels, assert that according to the flowing water state of design in advance the pipeline model carries out state and asserts and judge whether judgements the phenomenon of asserting to occur violating,, think that pipeline model is through verifying if then send report.
2. the method for claim 1 is characterized in that, the state value that the flowing water at different levels that detect are in real time exported carries out buffer memory, asserts that according to the flowing water state of design in advance the pipeline model carries out state and asserts that determining step comprises:
Assert the crowd that from the flowing water state of design in advance the reading flow water state is asserted in order;
Read from the state value of the flowing water at different levels output of buffer memory that current flowing water state relates in asserting certain grade or the state value of some grade flowing water are judged;
When judge to occur violating the phenomenon of asserting, then send report, assert and judge that the flowing water state is asserted to read and finished in the flowing water state is asserted the crowd otherwise continue to read next bar flowing water state.
3. method as claimed in claim 2 is characterized in that, when occurring violating the phenomenon of asserting, then carries out following steps:
Respectively the model unit steering logic and the upper level output unit that produce current flowing water state are verified.
4. the implementation method of an integrated circuit pipeline model is characterized in that, comprising:
The analog hardware method of operation is that the boundary divides model unit with the register; With the logical partitioning between one or more levels the register of current register and its front is a model unit; Wherein, Power function computing in the combinational logic puts under in the functional unit of model unit; Selection in the combinational logic and steering logic put under in the selected cell and controller of model unit, and the processing cycle in the sequential logic puts the internal drive unit under;
Design connects into secondary flowing water at least with the flowing water unit according to the integrated circuit pipeline series, constitutes the integrated circuit pipeline model.
5. implementation method as claimed in claim 4 is characterized in that, also comprises:
Adopt the drive clock of external drive unit as each flowing water unit of pipeline model; In each set inside internal drive unit, flowing water unit, said internal drive unit is according to the clock period of reception of this flowing water unit and transmission data, the clock signal that the drive clock signal Processing cost flowing water unit that the external drive unit is exported needs.
6. integrated circuit The pipeline design verification system is characterized in that comprising:
The water unit of secondary streams at least according to the integrated circuit The pipeline design is confirmed comprises a model unit at least in every grade of flowing water unit, each model unit comprises:
Back end interface is used to receive state value and the logical value that previous stage flowing water unit is exported;
Front-end interface is used for the state value and the logical value of this model unit are outputed to the next stage model unit;
Functional unit, the logical value that is used for that back end interface is sent carry out multiple power function computing and export a plurality of logical values;
The internal control unit; Comprise controller and state processing unit; Said controller is selected signal according to back end interface data sent and the steering logic output of itself, said state processing unit according to back end interface data sent and the state processing logic output state value of itself to front-end interface; With
Selected cell according to the selection signal of controller output, is selected one and is exported front-end interface in the logical value of reset values, set value and the laststate of a plurality of logical values of functional unit output, this model unit;
Survey routine generator, be used for producing the checking excitation, and will verify that according to time sequencing excitation sends to pipeline model, said checking excitation comprises logical value and state value;
State is asserted the unit, be used for each model unit of pipeline model state and between relation state, and design flowing water states at different levels and assert;
The state judging unit; Be used for detecting in real time the state value of flowing water outputs at different levels; Assert that according to state the state of unit asserts that the pipeline model carries out state and asserts judgement, then send report, think that pipeline model is through checking if the phenomenon of asserting occurs violating.
7. system as claimed in claim 6 is characterized in that, also comprises:
State storage unit is used for the state value that buffer memory flowing water at different levels are exported;
Said state judging unit comprises:
State reads subelement, is used for reading state and asserts that the state of the flowing water at different levels that the unit designs in advance asserts, also is used for certain grade or the state value of some grade flowing water from the state that state storage unit reads current flowing water is asserted, relating to;
The state judgment sub-unit is used for asserting certain grade or the state value of some grade flowing water that relates to according to the state that state reads the state of asserting of the flowing water at different levels that subelement reads, current flowing water, asserts judgement;
Status report subelement: be used for when the state judgment sub-unit judges that the phenomenon of asserting is violated in appearance, then sending report.
8. system as claimed in claim 6 is characterized in that, said pipeline model also comprises:
Pipeline control unit is used on the overall situation control pipeline model selection of each model unit logical value and state value and exports.
9. system as claimed in claim 6 is characterized in that, said model unit also comprises:
Buffer unit is used at said functional unit calculating process storage space being provided; The intermediate value that comprises the buffer memory calculating process perhaps according to the processing cycle of model unit, is stored the operation result of intercycle.
10. system as claimed in claim 6 is characterized in that, said pipeline model also comprises:
The external drive unit is as the drive clock of each flowing water unit of pipeline model;
Said model unit also comprises:
The internal drive unit according to the drive signal of external drive unit, calculates the time that front-end interface and back end interface transmit and receive data in this model unit, drives said front-end interface and back end interface and accomplishes and send and the reception task.
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