CN102779782A - Preparation process of dual damascene shallow dummy metal - Google Patents

Preparation process of dual damascene shallow dummy metal Download PDF

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Publication number
CN102779782A
CN102779782A CN2012102931649A CN201210293164A CN102779782A CN 102779782 A CN102779782 A CN 102779782A CN 2012102931649 A CN2012102931649 A CN 2012102931649A CN 201210293164 A CN201210293164 A CN 201210293164A CN 102779782 A CN102779782 A CN 102779782A
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metal
layer
hard mask
redundant
dual damascene
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李磊
梁学文
胡友存
陈玉文
姬峰
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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Abstract

The invention discloses a manufacture process of dual damascene shallow dummy metal. According to the process, a dummy metal pattern is added to a through hole photomask, and a dual damascene structure with shallow dummy metal is formed by adopting a partial groove optimized dual damascene process by taking metal-dielectric layer-metal as a hard mask, so that metallic interconnected parasitic capacitors can be reduced, the chemical mechanical polishing (CMP) process cannot be deteriorated while the interconnected RC (resistor capacitor) delay is improved. The manufacture process is simple, does not increase process steps, and can be completely compatible with hard mask partial groove optimized dual damascene manufacture process.

Description

The shallow redundant metal preparation technology of dual damascene
Technical field
The present invention relates to the semiconductor process techniques field, relate in particular to the shallow redundant metal preparation technology of a kind of dual damascene.
Background technology
Along with the semiconductor integrated circuit characteristic size continue reduce; Back segment interconnection resistance electric capacity (Resistor Capacitor; Abbreviation RC) postpones to appear the trend of remarkable increase; Postpone in order to reduce back segment interconnection RC, introduce low-k (Low-k) material, and the interconnection of copper-connection replacement aluminium becomes main flow technology.Because the manufacture method of copper interconnecting line can not form through etching sheet metal as aluminum interconnecting, so copper Damascus mosaic technology becomes the standard method that copper interconnecting line is made.
Copper Damascus technics processing procedure is: deposit one dielectric layer on planar substrates; In dielectric layer, form through hole and the groove of inlaying through photoetching and etching technics; Depositing metal barrier layer and copper seed layer; Plated metal copper fills up through hole and groove in the dielectric layer; Excess metal on the dielectric layer is removed in cmp (CMP) planarization, forms planar copper interconnect.
In order to improve the CMP process uniformity, reduce metallic copper dish (Dishing) and dielectric material erosion (Erosion) defective that CMP technology causes, redundant metal filled technology is arisen at the historic moment; So-called redundant metal filled, be meant that filling redundant (Dummy) metal at the white space of domain improves the metal layer image density uniformity.Common redundant metal is filled on the metal level mask in metal level mask manufacturing process, and together makes with the layer metal interconnection line.Therefore, final redundant metal thickness and the metal interconnecting wires consistency of thickness that forms of dual damascene process.
Yet the introducing of redundant metal can cause the increase of interconnection line parasitic capacitance, worsen back segment interconnection resistance electric capacity (Resistor Capacitor is called for short RC) and postpone, particularly along with characteristic size to reduce its influence more obvious.Irrespective problem must not become in the influence that reduces redundant metal pair interconnection line parasitic capacitance.
In order to address the above problem, a kind of mode that proposes at present is to reduce the thickness of redundant metal.Yet the making of common shallow redundant metal needs to increase an independent redundancy metallic mask and carries out chemical wet etching, to form shallow redundant metal valley; This can increase processing step, improves production cost.
In addition; Introducing along with low-K material; Particularly in the introducing of 45nm and following processing procedure porous low dielectric constant material (Porous Low-k), in order to reduce the damage of etching technics to Porous Low-k material, the hard preferential dual damascene process of mask part groove becomes main flow technology.And above-mentioned present employing pass through increase an independent redundancy metallic mask make the method for shallow redundant metal can not be compatible with the preferential dual damascene process of metal hard mask part groove.
Therefore, be necessary to propose a kind of simple and shallow redundant metal fabrication methods of the preferential dual damascene process of compatible metal hard mask part groove fully, to reduce the interconnection line parasitic capacitance that redundant metal causes.
Summary of the invention
The object of the present invention is to provide the shallow redundant metal preparation technology of a kind of dual damascene; Reducing the interconnection line parasitic capacitance that redundant metal causes, and the shallow redundant metal fabrication methods of the preferential dual damascene process of compatible metal hard mask part groove fully.
For addressing the above problem, the present invention proposes the shallow redundant metal preparation technology of a kind of dual damascene, comprises the steps:
The semiconductor matrix is provided, wherein, has been formed with N layer metal level on the said semiconductor substrate;
Deposit etching barrier layer, dielectric layer, dielectric protection layer and hard mask layer successively on said N layer metal level, wherein, said hard mask layer comprises first metal hard mask layer, dielectric hard mask layer and second metal hard mask layer from bottom to up successively;
Spin coating photoresist on said hard mask layer, and said photoresist is carried out photoetching through the metal level photomask, in said photoresist, form the metal interconnecting wires groove figure;
With said patterned photoresist is mask, and said hard mask layer is carried out etching, in said hard mask layer, forms the metal interconnecting wires groove figure, and removes remaining photoresist;
The spin coating photoresist, and said photoresist is carried out photoetching through the through hole photomask, wherein said through hole photomask is provided with redundant metallic pattern, in said photoresist, forms via hole image and redundant metallic pattern;
With said patterned photoresist is mask, and said dielectric protection layer is carried out etching, and said dielectric layer is carried out partial etching, in said dielectric layer, forms the partial through holes figure; Simultaneously said second metal hard mask layer is carried out etching, in said second metal hard mask layer, form redundant metallic pattern; And remove remaining photoresist;
With patterned hard mask layer is that mask carries out etching, in said dielectric layer, forms metal interconnected line trenches and redundant metal valley, and opens the etching barrier layer of said partial through holes figure bottom, forms double damask structure;
Said double damask structure is metallized, form N+1 layer metal level with metal interconnecting wires, through-hole interconnection and redundant metal.
Optional, said N layer metal level is the ground floor metal level, said N+1 layer metal level is the second layer metal layer.
Optional, the technology of said deposit etching barrier layer, dielectric layer and dielectric protection layer is CVD method.
Optional, the material of said etching barrier layer is one or more among SiCN, SiN, SiC, the SiCO.
Optional, the material of said dielectric layer is a low-K dielectric material.
Optional, said low-K dielectric material is SiOCH.
Optional, the material of said dielectric protection layer is any among SiO2, SiON, the SIN.
Optional, the technology of said deposit first metal hard mask layer and second metal hard mask layer is the physical vapor deposition method.
Optional, the material of said first metal hard mask layer is one or more among TiN, Ti, TaN, Ta, WN, the W.
Optional, the material of said second metal hard mask layer is one or more among TiN, Ti, TaN, Ta, WN, the W.
Optional, the thickness of said second metal hard mask layer is greater than the twice of the thickness of first metal hard mask layer.
Optional, the thickness of said first metal hard mask layer be
Figure BDA00002021837800031
said second metal hard mask layer thickness greater than
Figure BDA00002021837800032
said dielectric hard mask layer thickness is
Figure BDA00002021837800033
Optional, the technology of said deposit dielectric hard mask layer is CVD method.
Optional, the material of said dielectric hard mask layer is any among SiO2, SiON, the SIN.
Optional, the degree of depth of the said partial through holes figure that in dielectric layer, forms is the 120%-200% of through-hole interconnection height.
Optional, said double damask structure is metallized comprises the steps: to carry out at first successively metal barrier deposit, copper seed layer deposit, plating filling metallic copper; The cmp planarization is removed excess metal to dielectric layer then, forms the N+1 layer metal level with metal interconnecting wires, through-hole interconnection and redundant metal.
Optional, the degree of depth of said redundant metal valley is between dielectric layer height and metal interconnecting wires gash depth that cmp is removed.
Optional, the degree of depth of said redundant metal valley equals the dielectric layer height that cmp is removed.
Compared with prior art; The shallow redundant made technology of dual damascene provided by the invention is through adding redundant metallic pattern on the through hole photomask; Adopt metal-dielectric layer-metal to form the double damask structure that has shallow redundant metal as the preferential dual damascene process of the hard mask part groove of hard mask; Thereby can reduce the metal interconnecting wires parasitic capacitance, improve interconnection RC and postpone can not worsen cmp (CMP) technology simultaneously; And technology is simple, does not increase processing step, can the compatible fully hard preferential copper dual damascene of mask part groove manufacturing process.
Description of drawings
The flow chart of the shallow redundant made technology of dual damascene that Fig. 1 provides for the embodiment of the invention;
Fig. 2 A to Fig. 2 G is the corresponding device architecture sketch map of each step of the shallow redundant made technology of dual damascene that provides of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the shallow redundant made technology of dual damascene that the present invention proposes is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is; Provide a kind of dual damascene shallow redundant made technology; Through on the through hole photomask, adding redundant metallic pattern, adopt metal-dielectric layer-metal to form the double damask structure that has shallow redundant metal, thereby can reduce the metal interconnecting wires parasitic capacitance as the preferential dual damascene process of the part groove of hard mask; Improving interconnection RC postpones can not worsen cmp (CMP) technology simultaneously; And technology is simple, does not increase processing step, can the compatible fully hard preferential copper dual damascene of mask part groove manufacturing process.
Please refer to Fig. 1 and Fig. 2 A to Fig. 2 G; Wherein, The flow chart of the shallow redundant made technology of dual damascene that Fig. 1 provides for the embodiment of the invention; Fig. 2 A to Fig. 2 G is the corresponding device architecture sketch map of each step of the shallow redundant made technology of dual damascene that provides of the embodiment of the invention, and shown in Fig. 1 and Fig. 2 A to Fig. 2 G, the shallow redundant made technology of the dual damascene that the embodiment of the invention provides comprises the steps:
S101, semiconductor matrix 101 is provided, wherein, has been formed with N layer metal level 102 on the said semiconductor substrate 101; In embodiments of the present invention, this N layer metal level 102 is a first metal layer;
S102, on said N layer metal level 102 deposit etching barrier layer 103, dielectric layer 104, dielectric protection layer 105 and hard mask layer successively; Wherein, Said hard mask layer comprises first metal hard mask layer 106, dielectric hard mask layer 107 and second metal hard mask layer 108 from bottom to up successively, shown in Fig. 2 A;
S103, on said hard mask layer spin coating photoresist 109, and said photoresist 109 is carried out photoetching through the metal level photomask, in said photoresist 109, form the metal interconnecting wires groove figure, shown in Fig. 2 B;
S104, be mask, said hard mask layer is carried out etching, in said hard mask layer, form the metal interconnecting wires groove figure, and remove remaining photoresist with said patterned photoresist 109; Remove device architecture figure behind the remaining photoresist shown in Fig. 2 C;
S105, spin coating photoresist 110, and said photoresist 110 is carried out photoetching through the through hole photomask, wherein said through hole photomask is provided with redundant metallic pattern, in said photoresist 110, forms via hole image and redundant metallic pattern, shown in Fig. 2 D;
S106, be mask, said dielectric protection layer 105 carried out etching, and said dielectric layer 104 is carried out partial etching, in said dielectric layer 104, form partial through holes figure 111 with said patterned photoresist 110; Simultaneously said second metal hard mask layer 108 is carried out etching, in said second metal hard mask layer 108, form redundant metallic pattern 112; And remove remaining photoresist; Remove device architecture figure behind the remaining photoresist shown in Fig. 2 E;
S107, be that mask carries out etching with patterned hard mask layer; In said dielectric layer 104, form metal interconnected line trenches 113 and redundant metal valley 115; And open the etching barrier layer 103 of said partial through holes figure bottom; Form through-hole interconnection figure 114, thereby form double damask structure; Device architecture figure after this step is accomplished is shown in Fig. 2 F;
S108, said double damask structure is metallized, form N+1 layer metal level, shown in Fig. 2 G with metal interconnecting wires 116, through-hole interconnection 117 and redundant metal 118; Wherein in embodiments of the present invention, said N+1 layer metal level is second metal level.
Further, the technology of said deposit etching barrier layer 103, dielectric layer 104 and dielectric protection layer 105 is CVD method; Wherein, the material of said etching barrier layer 103 is one or more among SiCN, SiN, SiC, the SiCO; The material of said dielectric layer 104 is a low-K dielectric material, and particularly, said low-K dielectric material is SiOCH; The material of said dielectric protection layer 105 is any among SiO2, SiON, the SIN.
Further, the technology of said deposit first metal hard mask layer 106 and second metal hard mask layer 108 is the physical vapor deposition method; Wherein, the material of said first metal hard mask layer 106 is one or more among TiN, Ti, TaN, Ta, WN, the W, and the material of said second metal hard mask layer 108 is one or more among TiN, Ti, TaN, Ta, WN, the W.
Further, the thickness of said second metal hard mask layer 108 is greater than the twice of the thickness of first metal hard mask layer 106; Preferably, the thickness of said first metal hard mask layer 106 is that the thickness of
Figure BDA00002021837800061
said second metal hard mask layer 108 is greater than
Figure BDA00002021837800062
Further, the technology of said deposit dielectric hard mask layer 107 is CVD method; The material of said dielectric hard mask layer 107 is any among SiO2, SiON, the SIN; The thickness of said dielectric hard mask layer 107 is
Figure BDA00002021837800063
Further, the degree of depth of the said partial through holes figure 111 that in dielectric layer 104, forms is the 120%-200% of through-hole interconnection 117 height, thereby can guarantee that follow-up trench dielectric layer etching both had been unlikely to the insufficient over etching that also do not take place of etching.
Further, said double damask structure is metallized comprises the steps: to carry out at first successively metal barrier deposit, copper seed layer deposit, plating filling metallic copper; The cmp planarization is removed excess metal to dielectric layer then, forms the N+1 layer metal level with metal interconnecting wires, through-hole interconnection and redundant metal.
Further, the degree of depth of said redundant metal valley 115 is between the dielectric layer height and metal interconnected line trenches 113 degree of depth that cmp is removed.
Preferably, the degree of depth of said redundant metal valley 115 equals the dielectric layer height that cmp is removed, thereby can in the CMP process, just in time remove redundant metal fully, eliminates the influence of redundant metal pair interconnection line parasitic capacitance.
Wherein, in a specific embodiment of the present invention, said N layer metal level is the ground floor metal level, and said N+1 layer metal level is the second layer metal layer; Yet should be realized that, repeat above-mentioned steps, can make the metal level that multilayer more has shallow redundant metal; Be that said N layer metal level can also be the second layer metal layer, said N+1 layer metal level can be three-layer metal layer etc.
In sum; The invention provides the shallow redundant made technology of a kind of dual damascene; Through on the through hole photomask, adding redundant metallic pattern, adopt metal-dielectric layer-metal to form the double damask structure that has shallow redundant metal, thereby can reduce the metal interconnecting wires parasitic capacitance as the preferential dual damascene process of the part groove of hard mask; Improving interconnection RC postpones can not worsen cmp (CMP) technology simultaneously; And technology is simple, does not increase processing step, can the compatible fully hard preferential copper dual damascene of mask part groove manufacturing process.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.

Claims (18)

1. the shallow redundant metal preparation technology of dual damascene is characterized in that, comprises the steps:
The semiconductor matrix is provided, wherein, has been formed with N layer metal level on the said semiconductor substrate;
Deposit etching barrier layer, dielectric layer, dielectric protection layer and hard mask layer successively on said N layer metal level, wherein, said hard mask layer comprises first metal hard mask layer, dielectric hard mask layer and second metal hard mask layer from bottom to up successively;
Spin coating photoresist on said hard mask layer, and said photoresist is carried out photoetching through the metal level photomask, in said photoresist, form the metal interconnecting wires groove figure;
With said patterned photoresist is mask, and said hard mask layer is carried out etching, in said hard mask layer, forms the metal interconnecting wires groove figure, and removes remaining photoresist;
The spin coating photoresist, and said photoresist is carried out photoetching through the through hole photomask, wherein said through hole photomask is provided with redundant metallic pattern, in said photoresist, forms via hole image and redundant metallic pattern;
With said patterned photoresist is mask, and said dielectric protection layer is carried out etching, and said dielectric layer is carried out partial etching, in said dielectric layer, forms the partial through holes figure; Simultaneously said second metal hard mask layer is carried out etching, in said second metal hard mask layer, form redundant metallic pattern; And remove remaining photoresist;
With patterned hard mask layer is that mask carries out etching, in said dielectric layer, forms metal interconnected line trenches and redundant metal valley, and opens the etching barrier layer of said partial through holes figure bottom, forms double damask structure;
Said double damask structure is metallized, form N+1 layer metal level with metal interconnecting wires, through-hole interconnection and redundant metal.
2. the shallow redundant metal preparation technology of dual damascene as claimed in claim 1 is characterized in that said N layer metal level is the ground floor metal level, and said N+1 layer metal level is the second layer metal layer.
3. the shallow redundant metal preparation technology of dual damascene as claimed in claim 1 is characterized in that the technology of said deposit etching barrier layer, dielectric layer and dielectric protection layer is CVD method.
4. the shallow redundant metal preparation technology of dual damascene as claimed in claim 3 is characterized in that the material of said etching barrier layer is one or more among SiCN, SiN, SiC, the SiCO.
5. the shallow redundant metal preparation technology of dual damascene as claimed in claim 3 is characterized in that the material of said dielectric layer is a low-K dielectric material.
6. the shallow redundant metal preparation technology of dual damascene as claimed in claim 5 is characterized in that said low-K dielectric material is SiOCH.
7. the shallow redundant metal preparation technology of dual damascene as claimed in claim 3 is characterized in that the material of said dielectric protection layer is any among SiO2, SiON, the SIN.
8. the shallow redundant metal preparation technology of dual damascene as claimed in claim 1 is characterized in that the technology of said deposit first metal hard mask layer and second metal hard mask layer is the physical vapor deposition method.
9. the shallow redundant metal preparation technology of dual damascene as claimed in claim 8 is characterized in that the material of said first metal hard mask layer is one or more among TiN, Ti, TaN, Ta, WN, the W.
10. the shallow redundant metal preparation technology of dual damascene as claimed in claim 8 is characterized in that the material of said second metal hard mask layer is one or more among TiN, Ti, TaN, Ta, WN, the W.
11. the shallow redundant metal preparation technology of dual damascene as claimed in claim 1 is characterized in that the thickness of said second metal hard mask layer is greater than the twice of the thickness of first metal hard mask layer.
12. the shallow redundant metal preparation technology of dual damascene as claimed in claim 11; It is characterized in that, the thickness of said first metal hard mask layer be
Figure FDA00002021837700021
said second metal hard mask layer thickness greater than
Figure FDA00002021837700022
said dielectric hard mask layer thickness is
Figure FDA00002021837700023
13. the shallow redundant metal preparation technology of dual damascene as claimed in claim 1 is characterized in that the technology of said deposit dielectric hard mask layer is CVD method.
14. the shallow redundant metal preparation technology of dual damascene as claimed in claim 13 is characterized in that the material of said dielectric hard mask layer is any among SiO2, SiON, the SIN.
15. the shallow redundant metal preparation technology of dual damascene as claimed in claim 1 is characterized in that the degree of depth of the said partial through holes figure that in dielectric layer, forms is the 120%-200% of through-hole interconnection height.
16. the shallow redundant metal preparation technology of dual damascene as claimed in claim 1; It is characterized in that said double damask structure is metallized comprises the steps: to carry out at first successively metal barrier deposit, copper seed layer deposit, plating filling metallic copper; The cmp planarization is removed excess metal to dielectric layer then, forms the N+1 layer metal level with metal interconnecting wires, through-hole interconnection and redundant metal.
17. the shallow redundant metal preparation technology of dual damascene as claimed in claim 16 is characterized in that, the degree of depth of said redundant metal valley is between dielectric layer height and metal interconnecting wires gash depth that cmp is removed.
18. the shallow redundant metal preparation technology of dual damascene as claimed in claim 17 is characterized in that, the degree of depth of said redundant metal valley equals the dielectric layer height that cmp is removed.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105374746A (en) * 2015-12-03 2016-03-02 上海集成电路研发中心有限公司 Method for improving through-hole layer technical window
CN103515228B (en) * 2012-06-18 2016-03-30 中芯国际集成电路制造(上海)有限公司 A kind of manufacture method of semiconductor device
CN104241193B (en) * 2013-06-17 2017-05-10 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device
CN108962873A (en) * 2018-09-04 2018-12-07 长鑫存储技术有限公司 Compound double damask structure and preparation method thereof
CN112509915A (en) * 2020-11-30 2021-03-16 武汉新芯集成电路制造有限公司 Semiconductor device, manufacturing method thereof and chip bonding structure

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6680252B2 (en) * 2001-05-15 2004-01-20 United Microelectronics Corp. Method for planarizing barc layer in dual damascene process
US6849549B1 (en) * 2003-12-04 2005-02-01 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming dummy structures for improved CMP and reduced capacitance
CN101079392A (en) * 2006-05-26 2007-11-28 海力士半导体有限公司 Method of manufacturing flash memory device
CN102394227A (en) * 2011-11-30 2012-03-28 上海华力微电子有限公司 Manufacturing method of copper interconnection structure capable of reducing square resistance
CN102437104A (en) * 2011-11-28 2012-05-02 上海华力微电子有限公司 Manufacturing method of integrated circuit having a portion of redundant through holes and integrated circuit
CN102522367A (en) * 2011-11-30 2012-06-27 上海华力微电子有限公司 Manufacturing method of integrated circuit with ultra-thick top-layer metal and integrated circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6680252B2 (en) * 2001-05-15 2004-01-20 United Microelectronics Corp. Method for planarizing barc layer in dual damascene process
US6849549B1 (en) * 2003-12-04 2005-02-01 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming dummy structures for improved CMP and reduced capacitance
CN101079392A (en) * 2006-05-26 2007-11-28 海力士半导体有限公司 Method of manufacturing flash memory device
CN102437104A (en) * 2011-11-28 2012-05-02 上海华力微电子有限公司 Manufacturing method of integrated circuit having a portion of redundant through holes and integrated circuit
CN102394227A (en) * 2011-11-30 2012-03-28 上海华力微电子有限公司 Manufacturing method of copper interconnection structure capable of reducing square resistance
CN102522367A (en) * 2011-11-30 2012-06-27 上海华力微电子有限公司 Manufacturing method of integrated circuit with ultra-thick top-layer metal and integrated circuit

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515228B (en) * 2012-06-18 2016-03-30 中芯国际集成电路制造(上海)有限公司 A kind of manufacture method of semiconductor device
CN104241193B (en) * 2013-06-17 2017-05-10 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device
CN105374746A (en) * 2015-12-03 2016-03-02 上海集成电路研发中心有限公司 Method for improving through-hole layer technical window
CN105374746B (en) * 2015-12-03 2018-05-29 上海集成电路研发中心有限公司 A kind of method for promoting via layer process window
CN108962873A (en) * 2018-09-04 2018-12-07 长鑫存储技术有限公司 Compound double damask structure and preparation method thereof
CN108962873B (en) * 2018-09-04 2023-07-04 长鑫存储技术有限公司 Composite dual damascene structure and preparation method thereof
CN112509915A (en) * 2020-11-30 2021-03-16 武汉新芯集成电路制造有限公司 Semiconductor device, manufacturing method thereof and chip bonding structure
CN112509915B (en) * 2020-11-30 2024-02-02 武汉新芯集成电路制造有限公司 Semiconductor device, manufacturing method thereof and chip bonding structure

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Application publication date: 20121114