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Publication numberCN102595101 A
Publication typeApplication
Application numberCN 201210053360
Publication date18 Jul 2012
Filing date3 Mar 2012
Priority date3 Mar 2012
Publication number201210053360.9, CN 102595101 A, CN 102595101A, CN 201210053360, CN-A-102595101, CN102595101 A, CN102595101A, CN201210053360, CN201210053360.9
Inventors孙南, 查长军, 韦穗
Applicant安徽大学
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Front-end acquisition device of contour video monitoring system
CN 102595101 A
Abstract
The invention relates to a front-end acquisition device of a contour video monitoring system. The device comprises a photoelectric sensor group used for acquiring contour information, wherein the output end of the photoelectric sensor group is connected with the input end of a field programmable gate array (FPGA) controller; the input end of the FPGA controller is also connected with the output ends of a crystal oscillator circuit, a configuration downloading circuit and a reset circuit respectively; and the output end of the FPGA controller is connected with a serial port circuit. The contour characteristics of different types of objects are acquired through the photoelectric sensor group, the signal data acquired by the photoelectric sensor group is received by the FPGA controller, the serial port circuit is arranged, the signal data is transmitted into a computer terminal through the serial port circuit to be processed and identified, and finally, video monitoring on the different types of objects is realized. In all, photoelectric sensors and the FPGA controller are adopted in the front-end acquisition device, so the front-end acquisition device is low in cost and simple in structure and can acquire the contours of the different types of objects.
Claims(8)  translated from Chinese
1. 一种轮廓视频监控系统的前端采集装置,其特征在于:包括用于采集轮廓信息的光电传感器组,光电传感器组的输出端与FPGA控制器(3)的输入端相连,FPGA控制器(3)的输入端还分别与晶振电路(4)、下载配置电路(5)、复位电路(6)的输出端相连,FPGA控制器(3)的输出端与串口电路相连。 Front-end collection device for a profile of video surveillance systems, characterized by comprising: a photoelectric sensor group for acquiring profile information, photoelectric sensor group FPGA controller output terminal (3) connected to the input, FPGA controller ( output terminal 3) input terminals respectively and the crystal oscillator circuit (4), download configuration circuit (5), the reset circuit (6) is connected, FPGA controller (3) the output of the circuit is connected to the serial port.
2.根据权利要求I所述的轮廓视频监控系统的前端采集装置,其特征在于:所述的光电传感器组米用反射式光电传感器组(I),反射式光电传感器组(I)的输出端与传感器输入接口电路(2)的输入端相连,传感器输入接口电路(2)的输出端与FPGA控制器(3)的输出端相连;所述的串口电路采用RS232串口电路(7),FPGA控制器(3)的输出端通过RS232 串口电路(7)与计算机主机的串口相连。 The front-end collection means I outline the video surveillance system of claim, wherein: the photoelectric sensor group meters with reflective photoelectric sensor group (I), reflective photoelectric sensor group (I) of the output terminal and sensor input interface circuit (2) connected to the input, the output of the sensor input interface circuit (2) and FPGA controller (3) connected to the output; the serial circuit using RS232 serial circuit (7), FPGA control (3) the output of the circuit through the RS232 serial port (7) is connected to the serial port of the host computer.
3.根据权利要求2所述的轮廓视频监控系统的前端采集装置,其特征在于:装置还包括电源电路,电源电路分别向传感器输入接口电路(2)、FPGA控制器(3)、晶振电路(4)、下载配置电路(5 )、复位电路(6 )、RS232串口电路(7 )供电。 3. The contour of the front end of the video surveillance system collecting apparatus according to claim 2, characterized in that the: apparatus further comprises a power supply circuit, the power supply circuit are input interface circuit (2), FPGA controller (3) to the sensor, the crystal oscillator circuit ( 4) Download the configuration circuit (5), the reset circuit (6), RS232 serial circuit (7) power supply.
4.根据权利要求2所述的轮廓视频监控系统的前端采集装置,其特征在于:所述的FPGA控制器(3)包括芯片U3A、U3B、U3C、U3D ;所述的传感器输入接口电路(2)由排针接口JP1、双排针接口JP2以及排阻RP1、RP2、RP3、RP4组成,双排针接口JP2的5VCC引脚与反射式光电传感器组(I)的正极相连,双排针接口JP2的GND引脚与反射式光电传感器组(I) 的负极相连,排针接口JPl与反射式光电传感器组(I)的信号输出端相连。 The contour of the front-end video surveillance system collecting apparatus according to claim 2, characterized in that: the FPGA controller (3) comprises a chip U3A, U3B, U3C, U3D; said sensor input interface circuit (2 ) from the discharge pin connector JP1, JP2 and double needle hub exclusion RP1, RP2, RP3, RP4 composition, 5VCC pin double pin connector JP2 positive and reflective photoelectric sensor group (I) is connected, double needle hub negative JP2 GND pin and reflective photoelectric sensor group (I) is connected to pin interfaces JPl and reflective photoelectric sensor group (I) connected to the output signal.
5.根据权利要求4所述的轮廓视频监控系统的前端采集装置,其特征在于:所述的复位电路(6)包括电阻Rl,电阻Rl与电阻R2并联后接3. 3VCC,电阻Rl与按钮开关SI串联, 电阻R2与按钮开关S2串联,按钮开关S1、S2并联后接地,二极管D2的阳极接在电阻R2与按钮开关S2之间,二极管D2的阴极接排阻RP2的第7引脚,电阻Rl与按钮开关SI之间引出线与芯片U3C的第92引脚相连,电阻R2与按钮开关S2之间引出线与芯片U3A的第14 引脚相连。 5. The outline of video surveillance system front-end collection apparatus according to claim 4, wherein, wherein: the reset circuit (6) includes a rear resistance Rl, Rl resistance connected in parallel with the resistor R2 3. 3VCC, resistance Rl and buttons SI series switch, resistor R2 in series with the push button switch S2, the button switches S1, S2 after the parallel ground, the anode of diode D2 is connected between the resistor R2 and the button switch S2, the cathode of the diode D2 connected exclusion RP2 seventh pin, Lead and chip resistance Rl between U3C button switches SI and 92 connected to the pin, 14-pin chip lead U3A is connected between the resistor R2 and the push button switch S2.
6.根据权利要求4所述的轮廓视频监控系统的前端采集装置,其特征在于:所述的晶振电路(4)包括芯片Yl,其第2引脚接地,其第3引脚接芯片U3C的第93引脚,其第4引脚分两路,一路接3. 3VCC,另一路通过电容接地;所述的RS232串口电路(7)包括芯片U4,其第12引脚通过电阻R8接芯片U3B的第56引脚,其第11引脚接芯片U3B的第55引脚,其第13引脚与接口J2的第3引脚相连,其第14引脚与接口J2的第2引脚,其第15引脚与接口J2的第5引脚相连。 6. The outline of video surveillance system front-end collection apparatus according to claim 4, wherein: the oscillator circuit (4) including chip Yl, its second pin to ground, its third pin is connected to the chip U3C 93-pin, 4-pin its first two routes, the way then 3. 3VCC, another way to ground through a capacitor; the RS232 serial circuit (7) comprises a chip U4, its first 12-pin chip connected via a resistor R8 U3B The first 56-pin, 11-pin connected to its chip U3B 55th pin, 13-pin interface with its 3rd J2 pin is connected, its first 14-pin interface J2 pin 2, which 15-pin interface J2 fifth pin.
7.根据权利要求4所述的轮廓视频监控系统的前端采集装置,其特征在于:所述的下载配置电路(5)包括配置芯片Al以及JTAG接口JP3、JP4,JTAG接口JP3的第1、3、5、9引脚分别与芯片U3C的第88、90、89、95引脚相连,JTAG接口JP4的第1、5、7、9引脚分别与芯片U3A的第24、14、13、25引脚相连,JTAG接口JP4的第3引脚与芯片U3C的第86引脚相连,配置芯片Al的第1、2、5、6引脚分别与芯片U3A的第12、13、25、24引脚相连,电阻R3、 R4、R9的一端分别与芯片U3A的第22、23、21引脚相连,电阻R3、R4、R9的另一端并联后接地,电阻R10、R11的一端分别与芯片U3C的第87、86引脚相连,电阻R12的一端与芯片U3A 的第14引脚相连,电阻R10、R11、R12的另一端并联后接3. 3VCC0 7. The contour of the front end of the video surveillance system collecting apparatus according to claim 4, wherein: the download configuration circuit (5) including configuration chip and JTAG interfaces Al JP3, JP4, JTAG interfaces first and third JP3 , 5,9 pins are connected to the chip U3C first 88,90,89,95 pin, JTAG interfaces JP4 first 1,5,7,9 pins are chip U3A first 24,14,13,25 pin is connected, JTAG 86-pin connected to pin 3 of the interface chip U3C JP4, the configuration of the first 1,2,5,6 Al chip pin 12,13,25,24, respectively, with the first chip lead U3A pin is connected, the resistor R3, one end of R4, R9 are connected to the first chip U3A pin 22,23,21, respectively, resistors R3, R4, R9 parallel after grounding the other end of the resistor R10, R11, respectively, with one end of the chip U3C 87,86 connected to the first pin, 14-pin connected to one end of the chip resistor R12 U3A, the resistance R10, R11, R12 and the other end connected to the rear in parallel 3. 3VCC0
8.根据权利要求4所述的轮廓视频监控系统的前端采集装置,其特征在于:所述的排阻RP3的第16、15、14、13、12、11、10、9引脚分别与排针接口芯片JPl的第1、2、3、4、5、6、7、8引脚相连,排阻RP4的第16、15、14、13、12、11、10、9引脚分别与排针接口芯片JPl的第9、 10、11、12、13、14、15、16 引脚相连,排阻RPl 的第16、15、14、13、12、11、10、9 引脚分别与排针接口芯片JPl 的第17、18、19、20、21、22、23、24引脚相连,排阻1^2的第16、15、14、13、12、11 引脚分别与排针接口芯片JPl的第25、26、27、28、29、30引脚相连,排阻RP3的第1、2、3、4、5、6引脚分别与芯片U3A的第1、2、3、4、5、6引脚相连,排阻RP3的第7、8引脚分别与芯片U3B的第37,38引脚相连,排阻RP4的第1、2、3、4、5、6、7引脚分别与芯片U3B的第39、40、 41、42、49、50、51引脚相连,排阻RP4的第8引脚与芯片U3C的第73引脚相连,排阻RPl的第1、2、3、4、5引脚分别与芯片U3C的第74、75、76、77、78引脚相连,排阻RPl的第6、7、8引脚分别与芯片U3D的第109、110、111引脚相连,排阻RP2的第1、2、3、4、5、6引脚分别与芯片U3D 的第112、113、127、128、129、130 引脚相连。 8. The outline of the video surveillance system front-end collection apparatus according to claim 4, wherein: the exclusion of RP3 pins respectively ranked first 16,15,14,13,12,11,10,9 pin interface chip JPl first 1,2,3,4,5,6,7, 2.8 pin connected exclusion RP4 first 16,15,14,13,12,11,10,9 pins respectively pin interface chip JPl 9th, 10,11,12,13,14,15,16 pin connected exclusion RPl first 16,15,14,13,12,11,10,9 pins respectively pin interface chip JPl first 17,18,19,20,21,22,23,24 pin connected exclusion first 16,15,14,13,12,11 pins 1 ^ 2, respectively pin interface chip JPl first 25,26,27,28,29,30 pin connected RP3 1,2,3 exclusion of 1,2,3,4, - 5,6 pins are chip U3A's , 4,5,6 pin connected exclusion RP3 first 7-8 Connects pin chip U3B the first 37, 38, respectively, the first 1,2,3,4,5,6 RP4 of exclusion, 7-pin chip U3B respectively of the 39th, 41,42,49,50,51 pin is connected, is connected to the eighth pin 73 pin chip U3C exclusion RP4, the first of exclusion RPl , 2,3,4,5 pins are connected to the chip U3C first 74,75,76,77,78 pin, exclusion RPl first chip U3D 6,7,8 pins are the first 109, 110 111 pin connected exclusion RP2 and first 1,2,3,4,5,6 pins are chip U3D first 112,113,127,128,129,130 pin.
Description  translated from Chinese

一种轮廓视频监控系统的前端采集装置 An outline of the front acquisition device video surveillance system

[0001] [0001]

技术领域 Technical Field

[0002] 本发明涉及视频监控领域,尤其是一种轮廓视频监控系统的前端采集装置。 [0002] The present invention relates to the field of video surveillance, especially in the front end of a collection device profile video surveillance system.

[0003] [0003]

背景技术 Background

[0004]目前的视频监控系统是多媒体技术、视频压缩编码技术、计算机网络和人工智能等技术的综合运用,并向着智能化方向不断发展。 [0004] The current video surveillance system is the multimedia technology, the integrated use of video compression coding technology, computer networks and artificial intelligence technologies, and evolving towards intelligent direction. 从功能上看,视频监控可用于安全防范、 信息获取和指挥调度等方面,可以提供生产流程控制、大型公共设施的安防、医疗监护、远程教育等多种服务。 From a functional point of view aspect, video surveillance can be used for security, access to information and dispatching, etc., can provide the production process control, multi-service large-scale public facilities security, medical care, remote education. 从应用领域上看,视频监控在各行各业都得到了广泛的应用,例如档案室、博物馆、机要部门、交通违章和流量监控、住宅小区、停车场的无人监控等,然而这些监控系统都是安装在有限范围的某一指定区域。 From the applications, video surveillance in all walks of life have been widely used, such as archives, museums, confidential departments, traffic violations and traffic monitoring, residential quarters, unattended parking, etc. However, these monitoring systems They are installed in a limited range of the specified area.

[0005] 对于一个国家而言,边境经常是非法移民、走私者和恐怖分子出入的关键地方,对国家的安全具有很大挑战。 [0005] For a country, the border is often the key to place illegal immigrants, smugglers and terrorists out of the country with great security challenges. 我国与周边国家的陆地边界大约有2. 2万公里长,其中有许多是遥远而无人居住的地方,目前,这些地方实行自动监控相当困难,采用现有的视频监控系统不仅成本难以估量,而且受到高流量的数据限制。 Our land borders with neighboring countries are about 22,000 km long, many of which are remote and uninhabited places, at present, where the implementation of automatic monitoring is difficult, using the existing video surveillance system not only costs are difficult to estimate, but also by limiting high data traffic. 目前,还没有出现根据不同类型物体的外形轮廓特征不同,实现对整个边境监控的监控系统。 Currently, there is no contour according to different characteristics of different types of objects, the realization of the entire border surveillance monitoring system.

[0006] [0006]

发明内容 DISCLOSURE

[0007] 本发明的目的在于提供一种成本低、结构简单、能够实现对不同类型物体轮廓采集的轮廓视频监控系统的前端采集装置。 [0007] The present invention is to provide a low cost, simple structure, enabling front-end collection device for collecting different types of object contours outline of video surveillance systems.

[0008]为实现上述目的,本发明采用了以下技术方案:一种轮廓视频监控系统的前端采集装置,包括用于采集轮廓信息的光电传感器组,光电传感器组的输出端与FPGA控制器的输入端相连,FPGA控制器的输入端还分别与晶振电路、下载配置电路、复位电路的输出端相连,FPGA控制器的输出端与串口电路相连。 [0008] To achieve the above object, the present invention employs the following technical solutions: a front-end acquisition device profile video surveillance system, including the acquisition of inputs photoelectric sensor group contour information, the output of the photoelectric sensor group with FPGA controller end connected to the input of the FPGA controller also with crystal oscillator circuit, download the configuration circuit, the output of the reset circuit is connected to the output of the controller and serial FPGA circuit.

[0009] 由上述技术方案可知,本发明通过光电传感器组采集不同类型物体的外形轮廓特征,由FPGA控制器接收光电传感器采集的信号数据,并设置串口电路,通过串口电路送入计算机终端进行处理、识别,最终实现对不同类型物体的视频监控。 [0009] From the above aspect, the present invention is collected by a photoelectric sensor group contour characteristics of different types of objects, the received signal data collected by the FPGA photoelectric sensor controller, and set the serial circuit, into the computer via the serial port terminal circuit for processing identify, and ultimately for different types of objects video surveillance. 总之,本发明采用光电传感器和FPGA控制器,成本低、结构简单、能够实现对不同类型物体轮廓采集。 In summary, the present invention uses a photoelectric sensor and FPGA controller, low cost, simple structure, it is possible to collect different types of object contours.

[0010] [0010]

附图说明 Brief Description

[0011] 图I为本发明的电路框图; [0011] a circuit block diagram of the I of the present invention;

图2、3、4、5、6、7分别为图I中传感器输入接口电路、FPGA控制器、晶振电路、下载配置电路、复位电路、RS232接口电路的电路原理图。 Figure 2,3,4,5,6,7 are input to the sensor interface circuit in Figure I, FPGA controller, crystal oscillator circuit, download the configuration circuit, reset circuit, a circuit diagram RS232 interface circuit.

[0012] [0012]

具体实施方式 DETAILED DESCRIPTION

[0013] 一种轮廓视频监控系统的前端采集装置,包括用于采集轮廓信息的光电传感器组,光电传感器组的输出端与FPGA控制器3的输入端相连,FPGA控制器3的输入端还分别与晶振电路4、下载配置电路5、复位电路6的输出端相连,FPGA控制器3的输出端与串口电路相连,如图I所示,所述的FPGA控制器3控制光电传感器组进行数据采集以及串口传送数据。 Front-end collection device [0013] An outline of video surveillance systems, including for the acquisition photosensor group contour information, the input of the output of the photosensor group controller 3 is connected with the FPGA, FPGA controller input 3 respectively 4 is connected to the output terminal to download the configuration circuit 5, the reset circuit 6 crystal oscillator circuit, FPGA controller output is connected to the serial interface circuit 3, as shown in Figure I said FPGA controller 3 controls the photoelectric sensor group for data collection and serial transmission of data.

[0014] 如图I所示,所述的光电传感器组采用反射式光电传感器组1,反射式光电传感器组I的输出端与传感器输入接口电路2的输入端相连,传感器输入接口电路2的输出端与FPGA控制器3的输出端相连;所述的串口电路采用RS232串口电路7,FPGA控制器3的输出端通过RS232串口电路7与计算机主机的串口相连。 [0014] As shown in Figure I, said group of photosensor employing a reflective photoelectric sensor group 1, group I reflective photoelectric sensor and the output of the sensor input interface circuit input terminal 2 is connected to the output of the sensor input interface circuit 2 end FPGA controller output 3 is connected; the serial circuit RS232 serial circuit 7, the output of the FPGA controller 3 is connected via RS232 serial port circuit 7 and the host computer. 本装置还包括电源电路,电源电路分别向传感器输入接口电路2、FPGA控制器3、晶振电路4、下载配置电路5、复位电路6、RS232 串口电路7供电。 The device also includes a power supply circuit, the power supply circuit are input interface circuit to the sensor 2, FPGA controller 3, crystal oscillator circuit 4, download the configuration circuit 5, reset circuit 6, RS232 serial port power supply circuit 7.

[0015] 如图3所示,所述的FPGA控制器3包括芯片U3A、U3B、U3C、U3D ;如图2所示,所述的传感器输入接口电路2由排针接口JPl、双排针接口JP2以及排阻RPl、RP2、RP3、RP4组成,双排针接口JP2的5VCC引脚与反射式光电传感器组I的正极相连,双排针接口JP2的GND引脚与反射式光电传感器组I的负极相连,为反射式光电传感器组I提供+5V直流工作电压。 [0015] 3, wherein the FPGA controller 3 includes a chip U3A, U3B, U3C, U3D; shown in Figure 2, the sensor input interface circuit 2 from the discharge pin connector JPl, double needle hub JP2 and exclusion RPl, RP2, RP3, RP4 composition, the positive double-pin connector JP2 of 5VCC pin and reflective photoelectric sensor group I is connected, double-pin connector JP2 GND pin and reflective photoelectric sensor Group I negative terminal for reflective photoelectric sensor group I Supplies + 5V DC voltage. 排针接口JPl与反射式光电传感器组I的信号输出端相连。 Pin Interface JPl and signal outputs reflective photoelectric sensor group I connected.

[0016] 如图6所示,所述的复位电路6包括电阻Rl,电阻Rl与电阻R2并联后接3. 3VCC, 电阻Rl与按钮开关SI串联,电阻R2与按钮开关S2串联,按钮开关SI、S2并联后接地,二极管D2的阳极接在电阻R2与按钮开关S2之间,二极管D2的阴极接排阻RP2的第7引脚, 以备系统升级使用。 [0016] shown in Figure 6, the reset circuit 6 comprises a resistor Rl, Rl resistor connected in parallel with the resistor R2 post 3. 3VCC, resistor Rl in series with the push button switches SI, S2 resistor R2 in series with the push-button switch, push button switch SI , grounded S2 parallel diode D2 connected between the anode of the resistor R2 and the push button switch S2, the cathode of the diode D2 connected exclusion RP2 seventh pin, to prepare for system upgrades. 电阻Rl与按钮开关SI之间引出线与芯片U3C的第92引脚相连,电阻R2与按钮开关S2之间引出线与芯片U3A的第14引脚相连。 Lead and chip resistance Rl between U3C button switches SI and 92 connected to the pin, 14-pin chip lead U3A is connected between the resistor R2 and the push button switch S2. 按钮开关SI作为软件复位,按照用户代码来进行复位;按钮开关S2作为硬件复位,按下按钮开关S2时,标号nCONFIG引线为低电平,此时所有的FPGA代码重新从配置芯片Al里面读到FPGA控制器3中,程序重新开始运行。 SI as a software reset button switch, according to the user code to be reset; button switch S2 as a hardware reset, when you press the button switch S2, label nCONFIG lead to low, then re-read all of the code from the FPGA configuration chip inside Al FPGA controller 3, the program starts running.

[0017] 如图4所示,所述的晶振电路4包括芯片Y1,其第2引脚接地,其第3引脚接芯片U3C的第93引脚,其第4引脚分两路,一路接3. 3VCC,另一路通过电容接地,有源晶振为系统提供20MHz的全局时钟。 [0017] shown in Figure 4, the crystal oscillator circuit 4 includes a chip Y1, its second pin ground pin is connected to its 3-chip U3C 93rd pin, 4-pin its two routes, all the way then 3. 3VCC, another way to ground through a capacitor, an active global 20MHz crystal oscillator to provide clock for the system. 如图7所示,所述的RS232串口电路7包括芯片U4,其第12引脚通过电阻R8接芯片U3B的第56引脚,其第11引脚接芯片U3B的第55引脚,其第13引脚与接口J2的第3引脚相连,其第14引脚与接口J2的第2引脚,其第15引脚与接口J2 的第5引脚相连,将反射式光电传感器组I采集到信息数据传输给计算机终端,计算机终端再根据采集到的数字信号利用压缩传感算法进行处理、识别。 As shown in Figure 7, the RS232 serial circuit 7 includes a chip U4, its first 12-pin chip connected via a resistor R8 U3B 56th pin, 11th pin in its first 55-pin chip U3B, its 13-pin interface J2 pin is connected to the third, its first 14-pin interface J2 pin 2, pin 5 is connected to its 15-pin interface J2 of the reflective photoelectric sensor group I collect the message data is transmitted to the computer terminal, computer terminal and then processed in accordance with the acquired digital signal by a compressed sensing algorithm to identify.

[0018] 如图5所示,所述的下载配置电路5包括配置芯片Al以及JTAG接口JP3、JP4,JTAG 接口JP3的第1、3、5、9引脚分别与芯片U3C的第88、90、89、95引脚相连,JTAG接口JP4的第1、5、7、9引脚分别与芯片U3A的第24、14、13、25引脚相连,JTAG接口JP4的第3引脚与芯片U3C的第86引脚相连,配置芯片Al的第1、2、5、6引脚分别与芯片U3A的第12、13、25、24引脚相连,电阻R3、R4、R9的一端分别与芯片U3A的第22、23、21引脚相连,电阻R3、R4、 R9的另一端并联后接地,电阻RIO、Rll的一端分别与芯片U3C的第87、86引脚相连,电阻R12的一端与芯片U3A的第14引脚相连,电阻R10、R11、R12的另一端并联后接3. 3VCC。 [0018] below, download the configuration circuit 5 includes a chip configuration and JTAG interfaces Al JP3, JP4, JTAG interfaces JP3 first chip U3C 1,3,5,9 pins are shown in Figure 5, 88, 90 , 89,95 connected to the pin, JTAG interfaces JP4 first 1,5,7,9 Connects U3A first chip pin 24,14,13,25 respectively, JTAG interface to pin 3 of the chip U3C JP4 The 86th pin is connected, the first 1,2,5,6 Al configuration chip and chip pin 12,13,25,24 U3A first pin is connected respectively, end of the resistor R3, R4, R9, respectively chip U3A The pin is connected to the first 22,23,21, resistors R3, R4, grounding, resistor RIO, Rll is connected with one end of the first chip U3C pins 87,86 respectively after the other end of the parallel R9, resistor R12 and one end of the chip U3A The first 14-pin connected to the resistor R10, R11, R12 and the other end connected to the rear in parallel 3. 3VCC. 若通过JTAG接口JP3下载程序时,系统掉电后需重新向FPGA控制器3下载,若通过JTAG接口JP4下载程序时,用户程序代码将存储在配置芯片Al中,系统每次上电后,用户程序代码将自动从配置芯片Al中读入FPGA控制器3,然后运行。 If JP3 download via the JTAG interface, power down the system to be re-downloaded to the FPGA controller 3, if the JTAG interface JP4 download the program, the user program code is stored in the configuration Al chip, the system after each power user the code will automatically read FPGA configuration chip controller 3 from Al, and then run.

[0019] 如图2所示,所述的排阻RP3的第16、15、14、13、12、11、10、9引脚分别与排针接口芯片JPl的第1、2、3、4、5、6、7、8引脚相连,排阻RP4的第16、15、14、13、12、11、10、9引脚分别与排针接口芯片JPl的第9、10、11、12、13、14、15、16引脚相连,排阻RPl的第16、15、14、 13、12、11、10、9引脚分别与排针接口芯片JPl的第17、18、19、20、21、22、23、24引脚相连,排阻RP2的第16、15、14、13、12、11引脚分别与排针接口芯片JPl的第25、26、27、28、29、30引脚相连,排阻RP3的第1、2、3、4、5、6引脚分别与芯片U3A的第1、2、3、4、5、6引脚相连,排阻RP3的第7、8引脚分别与芯片U3B的第37,38引脚相连,排阻RP4的第1、2、3、4、5、6、7引脚分别与芯片U3B的第39、40、41、42、49、50、51引脚相连,排阻RP4的第8引脚与芯片U3C的第73引脚相连;排阻RPl的第1、2、3、4、5引脚分别与芯片U3C的第74、75、76、77、78引脚相连,排阻RPl的第6、7、8引脚分别与芯片U3D的第109、110、111引脚相连,从而将反射式光电传感器组I的输出信号送入FPGA控制器3,实现信号采集;排阻RP2的第1、2、3、4、5、 6引脚分别与芯片U3D的第112、113、127、128、129、130引脚相连。 [0019] 2, the exclusion RP3 first 16,15,14,13,12,11,10,9 pin respectively pin interface chip JPl of 1,2,3,4 , 5,6,7,8 pin connected exclusion RP4 first 16,15,14,13,12,11,10,9 pin respectively pin interface chip JPl first 9,10,11,12 , 13,14,15,16 pin connected exclusion RPl first 16,15,14, 13,12,11,10,9 pin respectively pin interface chip JPl section 17,18, 19,20 , 21,22,23,24 pin connected exclusion RP2 first 16,15,14,13,12,11 pin respectively pin interface chip JPl first 25,26,27,28,29,30 pin connected exclusion RP3 first pin is connected to the chip U3A 1,2,3,4,5,6 first pins are 1,2,3,4,5,6, 7 RP3 of exclusion, 8 pins are connected to the first 37 and 38-pin chip U3B, exclusion RP4 first 1,2,3,4,5,6,7 pins are chip U3B first 39,40,41,42, 49,50,51 pin to 73-pin connected to pin 8 of the chip U3C exclusion RP4; the exclusion RPl of 1,2,3,4,5 pins are chip U3C 74th , 75,76,77,78 pin connected exclusion 6,7,8 RPl first pin is connected to the chip U3D the first 109, 110 pins are so reflective photoelectric sensor output signals Group I into the FPGA controller 3, signal acquisition; RP2 exclusion of 1,2,3,4,5, 6-pin chip is connected to the first 112,113,127,128,129,130 U3D pins respectively.

[0020] 总之,本发明低成本、系统简单,便于安装,通过反射式光电传感器组I对前端的人、动物或汽车等物体进行信息的采集,并将信息传递至FPGA控制器3,实现前端视频的采集,FPGA控制器3再通过RS232串口电路7将前端采集到的信息传输至计算机的串口,由后台计算机进一步对人、动物或汽车等外形轮廓图像进行识别,实现监控功能。 [0020] In summary, the present invention is a low cost, the system is simple, easy to install, I on the front of people, animals or cars and other objects collected information through reflective photoelectric sensors, and the information is passed to the FPGA controller 3, to achieve the front video capture, FPGA controller 3 and then transmit the information to a computer via RS232 serial interface circuit 7 front-end collection to the serial port, the background computer further persons, animals or cars, the outline image recognition, realization monitoring.

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Reference
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Classifications
International ClassificationH04N5/225, G05B19/05, H04N7/18
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