CN102569227A - Integrated circuit radiating system and manufacturing method thereof - Google Patents
Integrated circuit radiating system and manufacturing method thereof Download PDFInfo
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- CN102569227A CN102569227A CN2010106066273A CN201010606627A CN102569227A CN 102569227 A CN102569227 A CN 102569227A CN 2010106066273 A CN2010106066273 A CN 2010106066273A CN 201010606627 A CN201010606627 A CN 201010606627A CN 102569227 A CN102569227 A CN 102569227A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
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Abstract
The invention discloses an integrated circuit radiating system, which comprises at least three layers of substrates including an upper layer substrate, an interlayer substrate and a lower layer substrate, wherein a micro channel is formed between adjacent substrates; current conducting channels are formed in the three layers of substrates; the upper layer substrate is electrically connected with an integrated circuit chip through the current conducting channel; adjacent substrates are electrically connected with each other through the current conducting channel by passing through the micro channel; and the lower layer substrate is electrically connected with external power through the current conducting channel. According to the method, the problem that heat cannot be brought out in a three-dimensional integrated encapsulating model is solved, the radiating performance of the chip is improved greatly, the reliability of the chip is enhanced, and the service life of the chip is prolonged; and the integrated circuit radiating system has the characteristics of simple process, low cost, and the like.
Description
Technical field
The present invention relates to microelectronic packaging technology, MEMS technology and three-dimensional integrated technology field specifically are a kind of cooling integrated system and manufacture method.
Background technology
, high density high-speed along with microelectronic chip, high performance development, heat management has become a very important problem in the micro-system encapsulation, so the heat dissipation problem in the integrated circuit is very important in many computer applications.In the high-performance calculation machine, for example server, large-scale computer and super computer, the radiating efficiency of multi-chip module will directly influence the design and the operating characteristics of computer.
The heat of chip is produced by the electric current resistance of flowing through.It is to transmit the process that transmits with power by signal on the chip along metal wire to produce that resistance is given birth to heat, also can be by individual transistor biasing electric current through producing in integrated circuit substrate leakage and the transistor level transfer process.The generation of another kind of heat occur in multi-chip module or and motherboard between carry out on the conductor resistance of signal and power transmission.
Heat radiation in the integrated circuit generally is to transmit to a heat diffuser with high thermal conductivity coefficient through chip, and final fin through high surface area is melt in the convection gas.In order to strengthen radiating effect, convection current possibly be cooled, and wherein integrated circuit carries out the focus that the liquid heat radiation becomes present Chip Packaging system thermal management through fluid line.
Multi-chip module generally is made up of the electrical insulating material of the embedded interference networks of multilayer, and insulating material is pottery normally.The high-performance multi-chip module generally can comprise 80～120 layers of metal and electric insulation layer, 6～8 cm thicks.The conductive coefficient of pottery insulating material is equivalent to 1/30 of silicon, 1/80 of copper.IC chip is typically connected on the electrical connection salient point of chip surface two-dimensional arrangement.
The multi-chip module structure generally comprises substrate connected vertically, with the IC chip that is connected through salient point.The structure that forms thus is commonly called " lamination ".A plurality of " laminations " and single IC chip also can be connected on the salient point; On the multi-chip module surface that traditional two-dimensional is arranged; Only if implement suitable cooling provision, otherwise a plurality of chip-stacked continuous rising that will bring chip temperature owing to heat history.Therefore, high-performance computer system is realizing when multi-chip module provides the interference networks wiring density of necessity, only relying on traditional heat dissipating method of chip, is difficult to reach satisfying of its design performance.
Summary of the invention
One of the object of the invention is to provide a kind of cooling integrated system of good heat dissipation effect.
A kind of cooling integrated system is provided according to an aspect of the present invention, comprises at least three laminar substrates: top substrate layer, interlayer substrate reach laminar substrate down, form the microchannel between adjacent substrate;
Establish conductive path in said three laminar substrates are equal, wherein top substrate layer is electrically connected with IC chip through said conductive path, passes the microchannel through said conductive path between adjacent substrate and is electrically connected, and following laminar substrate is connected with external electric through said conductive path.
Wherein, said top substrate layer is a semiconductor substrate, and the interlayer substrate is a metal substrate, and following laminar substrate is a semiconductor substrate.
Wherein, The conductive path of said top substrate layer comprises the salient point of upper surface to be electrically connected with said IC chip that is arranged at said top substrate layer; And be arranged at the lower surface of said top substrate layer and be arranged in said microchannel that forms with said interlayer substrate and the salient point that is electrically connected with the conductive path of said interlayer substrate, also comprise the electric conductor that is arranged in the said top substrate layer and is electrically connected the salient point of said upper surface and lower surface.
Wherein, the surface of said top substrate layer is provided with insulating barrier, in this insulating barrier network of conductors is set, and this network of conductors is electrically connected said IC chip and said electric conductor as the part of the conductive path of said top substrate layer.
Wherein, The conductive path of said interlayer substrate comprises the upper surface that is arranged at this interlayer substrate and/or the salient point of lower surface; This salient point is arranged in the microchannel of adjacent substrate formation and with the conductive path of said adjacent substrate and is electrically connected, and also comprises the electric conductor that is arranged in the said interlayer substrate and is electrically connected said salient point.
Wherein, the surface of said interlayer substrate is provided with insulating barrier, in this insulating barrier network of conductors is set, and this network of conductors is electrically connected the conductive path of said top substrate layer and the electric conductor of said interlayer substrate as the part of the conductive paths of said interlayer substrate.
Wherein, the conductive path of said down laminar substrate comprises the upper surface and the salient point of lower surface that is arranged at this time laminar substrate, and the electric conductor that is arranged at the salient point of interior said upper surface of electrical connection of said laminar substrate down and lower surface;
Wherein, the said salient point that is arranged at upper surface is arranged in the microchannel of adjacent substrate formation and with the conductive path of said adjacent substrate and is electrically connected; The said salient point that is arranged at lower surface is connected with external electric.
Wherein, the said surface of laminar substrate down is provided with insulating barrier, and network of conductors is set in this insulating barrier, and this network of conductors is electrically connected the conductive path of said interlayer substrate and the electric conductor of this time laminar substrate as the said part of the conductive path of laminar substrate down.
Wherein, said salient point and/or electric conductor form through electrodeposit metals technology or form through electro-deposition multi-element metal technology.
Wherein, said electric conductor is arranged in the formed electrical connection through hole of counterpart substrate, and this electrical connection through hole periphery is provided with insulating barrier and barrier layer.
Wherein, at least one laminar substrate set inside microchannel in said three laminar substrates.
Wherein, also comprise outside heat sink or external fluid radiator structure.
Wherein, this cooling system is isolated through seal and external environment condition.
Wherein, this cooling system is applied to the heat radiation of multi-chip module, and said IC chip is a multi-chip module.
Another aspect of the present invention also provides the manufacture method of interlayer substrate in a kind of cooling integrated system, may further comprise the steps:
Steps A: deposit passivation layer is coated with photosensitive material in passivation layer in substrate layer, under the mask of mask, makes public;
Step B: remove the outer light-sensitive material of said mask masks area;
Step C: the deposition Seed Layer is in the surface of the expose portion of said light-sensitive material and passivation layer;
Step D: depositing metal layers is on Seed Layer;
Step e: the said metal level of attenuate and planarization obtains smooth surface;
Step F: remove the residue light-sensitive material and obtain metal structure;
Step G: make insulating barrier and Seed Layer in the exposed surface of said metal structure and passivation layer;
Step H: depositing metal layers is in Seed Layer described in the last step;
Step I: metal level described in the step obtains smooth surface on attenuate and the planarization, makes passivation layer in this surface;
Step J: remove substrate layer, the back side of the structure that obtains in above-mentioned steps is coated with photosensitive material, and the hole of the metal level that the etching technics through photoetching process and passivation layer obtains to deposit among the said step H of connection is made Seed Layer on the exposed surface of this hole;
Step K: make metal level above the described Seed Layer of step J;
Step L: the metal level among attenuate and the planarization treatment step K obtains smooth surface;
Step M: remaining light-sensitive material obtains bump structure among the removal step J.
Wherein, also comprise after the step M:
Step N: the interlayer substrate to form among the step M is the basis, simultaneously makes the connection salient point at it, and another side is made the insulating barrier that includes built-in conductive network, obtains repetitive;
Several same said repetitive is carried out lamination; Wherein, the insulating barrier of a repetitive is connected with the salient point of another repetitive.
The cooling integrated system and method that the present invention proposes improves cooling integrated efficient.
Description of drawings
Fig. 1 is the cross-sectional schematic of an embodiment of the cooling integrated system of the present invention;
Fig. 2 is the flow chart in the manufacturing process A-H step of middle interlayer metal substrate embodiment illustrated in fig. 1;
Fig. 3 is the hookup 2I-N flow chart in step;
Fig. 4 is the sketch map of another embodiment of the cooling integrated system of the present invention;
Fig. 5 is the sketch map of the 3rd embodiment of the cooling integrated system of the present invention;
Fig. 6 is the sketch map of the 4th embodiment of the cooling integrated system of the present invention.
Embodiment
In order to make the object of the invention, it is more clear that technical scheme and advantage are described, and explains below in conjunction with concrete instance and accompanying drawing.Multi-chip module described in the present invention is different from existing multi-chip module model, and it not only provides an electrical interconnection network, but also the cooling integrated structure that multi-chip module is provided and connects multi-chip module.Multi-chip module model among the present invention is utilized in the compressible fluid that flows in the microchannel, and dispels the heat through the structure control flow rate of fluid.Simultaneously the multi-chip module structure among the present invention is also managed the heat in the package system fluid passage that forms of the material through high heat conductance.In addition, can also dispel the heat to system through externally increasing with the passage of the incompressible fluid of inner flow passage coupling or the type of cooling that add other types.
Method described in the invention in addition, material and manufacture craft also can be applied to the heat radiation in single IC for both and the single chip model.
The present invention is mainly used in highdensity electrical connection network (comprising route integrated circuit and switch integrated circuit), such as the processor and the main memory circuit of multinuclear.
Multi-chip module is to be used for transmitting electronic signal between the integrated circuit die, the signal of telecommunication and earth signal, and the nude film of these integrated circuits mainly is to be used for carrying out particular functionality, such as logic relatively, and addition, memory, the digital signal of switch and route.In normal operation, each integrated circuit all produces certain calorimetric, and these heats mainly are that the resistance by the current path material produces.If heat can not distribute to the external world at a high speed, the temperature of integrated circuit will constantly rise so, and the work of integrated circuit will be adversely affected under some temperature.Therefore heat radiation becomes extremely important for integrated circuit, and the present invention mainly is because this structure can be taken away the heat of as close as possible thermal source for the total system of integrated circuit and multi-chip module provides than higher rate of heat dispation.In current science and technology, in order to reduce thermal resistance, it is very thin that nude film has been subtracted.Main application is to dispel the heat through the mode of thermal conductance at the back of nude film now, generally adopts ceramic substrate or encapsulant in the front of nude film.Heat conduction mainly is to carry out with the metal that is embedded into pottery that is connected with the wiring network through encapsulant, and wherein the cooling duct material thermal conductivity in the conductive coefficient of ceramic substrate material and glass and the ceramic substrate is more approaching.
Microchannel cooling in ceramic substrate material will be difficult to obtain reasonable radiating effect, mainly be because the thermal conductivity of ceramic material itself is very little.Therefore be necessary near transistorized pyrotoxin and heat radiation as far as possible efficiently as much as possible.In order to reach this purpose; The multi-chip module radiator structure has been proposed among the present invention; This radiator structure is as much as possible near the transistor layer of integrated circuit, and has the composite material of high heat conductance and dispel the heat through the mode of directly dispelling the heat in the inside of multi-chip module through employing.
With reference to figure 1, illustrate the cross-sectional schematic of an embodiment of multi-chip module encapsulating structure who comprises the cooling integrated system of the present invention.The multi-chip module encapsulating structure comprises three laminar substrate structures, is respectively top substrate layer 150, interlayer substrate 170 and following laminar substrate 180.In order to set forth more clearly, here the extra play of other above the board structure is left in the basket.And, formed between adjacent substrate and be used to the microchannel 165 that supplies fluid to pass through to dispel the heat.
The material that has comprised two types of different thermal conductivities of these three board structures, top substrate layer 150 is a semiconductor substrate with following laminar substrate 180 uses, what interlayer substrate 170 used is metal substrate.Upper surface at said three substrates all is being distributed with the insulating barrier 120 that includes the built-in metal network of conductors.
Wherein, Lead 132 in the insulating barrier 120 is formed said network of conductors with wire column 130 functions; This network of conductors is also as the part of corresponding conductive path, the common formation of the electric conductor in the electrical connection through hole 140,190 or 155 that is provided with in this part conductive path and the counterpart substrate conductive path corresponding with said substrate.
And for top substrate layer, its conductive path also is included in the salient point 135 between insulating barrier 120 and the substrate 150, and purpose is to realize the electrical connection that is electrically connected electric conductor in the through hole 140 of lead redistributing layer and substrate 150 in the insulating barrier 120.And at the upper surface of insulating barrier 120, just the upper end of the whole conductive path of top substrate layer also is provided with salient point 125, and its effect realizes being electrically connected with integrated circuit die 115 and 105, and wherein integrated circuit 105 also possibly be the integrated circuit 110 that multiple-level stack is arranged.And at the lower surface of substrate 150; The lower end of top substrate layer conductive path just; In microchannel 165, be provided with salient point 145, this salient point 145 provides the space of passage, and the heat conduction approach through the microchannel is provided; Regulate the mean flow rate of fluid, and the electrical connection of passing microchannel 165 also is provided.
In like manner, the microchannel 165 between interlayer substrate and following laminar substrate also is provided with salient point 145, and also is provided with salient point 135 between insulating barrier 120 and the substrate 170, also is provided with salient point 135 between insulating barrier 120 and the substrate 180, and is same as above with effect.
And the lower surface of substrate 180 is provided with salient point 160 to be electrically connected with external connection interface section 185.
So, the conductive path in three laminar substrates and each salient point just realized integrated circuit die 105 and 115 with being electrically connected of external connection interface section 185.And in the microchannel 165 when the fluid, just can take away heat, and the salient point in the microchannel 165 145 played the effect of regulating flow velocity, increased thermal conductivity, improved radiating effect.
Preferably, one deck electrical insulating material that on lead, distributes again, this material has lower thermal conductivity and reasonable electrical insulation capability.
Board structure 150,170 and 180 is to be used for increasing inner conductive coefficient, and the signal and the distribution network of insulating barrier 120 inner conductors and conductive pole part.Board structure 180 has thicker substrate layer, can more intense machinery support is provided and the interface that is electrically connected with substrate stage is provided for whole encapsulating structure.The microchannel 165 that between each layer, forms is the passage that compressible fluid provides circulation, and these fluids generally have low surface tension, low viscosity and high specific heat capacity.
Fig. 2 and Fig. 3 show the manufacturing process A-H and the flow chart in I-N step (wherein, what the A-M step obtained is the situation of one deck, and the N step has then shown multilayer laminated situation) of middle interlayer metal substrate embodiment illustrated in fig. 1 respectively.Mainly the manufacture craft flow process of conductive through hole in the metal substrate structure 170 and conductive wire has been carried out detailed explanation.As shown in Figure 2, mainly set forth the making flow process before forming conductive structure.
Shown in Fig. 2 A step, the application that it has set forth photoetching process utilizes a lithography layout 205 with planar graph, and photoresist or material 210 with light sensitivity are carried out photoetching.Formation one deck includes SiO on substrate layer 220
2Or SiN
1-xPassivation layer 215.Passivation layer mainly be applied to electrochemical mechanical polishing stop layer certainly.Utilize suitable light through to after photoresist layer 210 exposures, utilize photoresist wet etching solution or dry plasma technology to remove the material that exposes, thereby obtain the structure 210 shown in the 2B step.
Shown in Fig. 2 C step, the Seed Layer 225 of deposition layer of metal deposition on the surface of structure 210.Wherein a kind of example of concrete realization is the Seed Layer that copper can be used as the copper Metal Deposition, also can be other Metal Deposition, but will use other corresponding Seed Layer, such as nickel and gold etc.
Shown in Fig. 2 D step, metal level 230 need utilize the certain thickness of specific process deposits, such as Applied Electrochemistry or chemical deposition process method.Metal level 230 need have than high thermal, is better dispelled the heat in the inside of multi-chip module.
Shown in Fig. 2 E step, metal level 230 need be thinned to desired thickness after deposition, forms a more smooth plane, and the reasonable metal level of certain thickness and surface quality can guarantee better to carry out the technology of the semiconductor integrated circuit on upper strata; Step 2E can use the conventional chemical mechanical polishing process and realize, the thickness of attenuate depositing metal layers reaches requirement and can make on the other hand and have an even surface on the one hand.Fig. 2 E step has been described smooth metal level 230 structures, and the thickness of metal level 230 is identical with the thickness of photoresist 210.
Shown in Fig. 2 F step, removal photoresist layer 210 backs just can form desired metal structure according to the character of the photoresist that uses.The technology of concrete removal photoresist layer can be used organic solvent wet etching also possibly use gas chemistry plasma dry etching.
Shown in Fig. 2 G step, in the 230 surface deposition one deck electric insulation layers 225 of the structured metal layer shown in Fig. 2 F step, deposition one deck Seed Layer 223 on insulating barrier 225;
Shown in Fig. 2 H step, deposition layer of metal layer 232 is on Seed Layer, and wherein metal level 230 can be made up of the different metallic material with metal level 232, is insulated layer 225 each other and isolates.
Shown in Fig. 3 I step, metal level 232 attenuates and flatening process reach the surface of insulating barrier 225, the similar passivation layer 216 of deposition one deck and passivation layer 215 on its uppermost surface.
Shown in Fig. 3 J step, remove substrate layer 220 then up near passivation layer 215 and metal level 232.What substrate layer 220 possibly adopt is the combined material of glass material, semi-conducting material, metal material or multiple material.The process of removing substrate 220 includes aqueous solution wet method or plasma dry etching, mechanical lapping and polishing.The removal method can not be destroyed passivation layer 215.Removing the surperficial spin coating one deck photoresist layer 235 of substrate layer 220 backs at passivation layer 215; This layer photoetching glue is similar with photoresist 210; Utilize lithography mask version then and combine to be fit to parameter and carry out photoetching process; And the part of utilizing etchant solution to remove can to remove forms needed figure, removes the parameter that the photoresist that is included in below the passivation layer can suitably be adjusted etching process for better in addition.
Remaining photoresist is used conventional semiconductor fabrication process as mask and is removed a following layer insulating 215.Be formed on the hole 236 of the photoresist above the metal level thereafter;
In order to realize and metal level 232 conductions, in hole 236, fill a kind of conductor material then.Similar with metal deposition process shown in Fig. 2 G, so just obtain the structure shown in Fig. 3 J step, wherein metal seed layer 240 is deposited on the surface of exposure, mainly is on the surface of hole 236 and photoresist 235.
Shown in Fig. 3 K step, can adopt electrochemical deposition process plated metal 233 on Seed Layer 240 then, obtain the result shown in Fig. 3 K step;
Shown in Fig. 3 L step, adopting flatening process then is that metal level 233 has a smooth plane such as the mechanization glossing, obtains the structure shown in Fig. 3 L step;
Shown in Fig. 3 M step, remove the bump structure 260 shown in Fig. 3 M step that photoresist obtains being connected with 232 then, this salient point is made up of metal level 233.
The above manufacture method process of introducing is as shown in Figure 2; The structure that the technical process of A to M obtains; Combination through these technologies and process just can obtain the situation that interlayer substrate among the present invention has only one deck; When said interlayer substrate comprises multilayer when forming the laminated construction of major part multi-chip module structure of the present invention, then can repeat said process with the interlayer metal substrate that obtains range upon range of (embodiment can with reference to figure 3N); It is a kind of laminated construction with heat conduction channel of high-termal conductivity.
Shown in Fig. 3 N step, the multi-chip module laminate portion that has the internal gas passage mainly has been described, also be major part of the present invention.Described part includes structure I, II, III, IV, and structure I is corresponding to Fig. 3 M part shown in Figure 2, and the structure in Fig. 3 I step is connected through other the structure that connects salient point 265 and system.Conducting metal salient point 260 effects as shown in the figure are to increase the mechanical strength of structure and the heat-conductive characteristic that increases through passage 165; Bump structure 260 has formed microchannel 165 in structure I and structure I I; Salient point 260 and 261 also have to be regulated the effect through the heat radiation of multi-chip module, realizes that two kinds of approach are: (1) thus be adjusted in the whole pipe gaseous fluid in the average flow velocity of part through fluid in the passage mobile; (2) have reasonable heat-conductive characteristic through it and be adjusted in ducted heat-conductive characteristic.The Embedded network of conductors of electrical connection and the Embedded wire column of vertical electrical connection of level have been formed in the electrical insulating material on structure I I surface.Structure 255 and 269 has been represented the lead that forms, and structure 250 has then been represented the wire column that forms.Structure III is similar with structure I, realizes being connected of electricity and machinery with salient point 265 with layer IV through salient point 260, and structure III and structure I V have formed microchannel 165 through salient point 260.Wherein structure I V possibly include and have the IC semiconductor wafer of being made up of transistor and plain conductor.
That is to say that the one side of the structure that in step M, forms among the step N is made and connected salient point, another side is made the insulating barrier that includes built-in conductive network, and two identical metal substrate structures that will obtain are then carried out lamination; Wherein the conductive network face of one deck is connected with the salient point surface of another layer, and the salient point surface of this laminated construction is linked to each other with another thicker metal substrate, forms the lamination radiator structure that has three-ply metal and include the fluid passage.
Wherein, I and III are equivalent to the range upon range of of two layer interlayer metal substrates, and it is two repetitives, and II part then is equivalent to insulating barrier, and conductive network (can with reference to the preceding text relevant portion) is set in it, and the IV part then is equivalent to said thicker metal substrate.
Fig. 4 show comprise integrated circuit heat dissipation device of the present invention and another embodiment sketch map of cooling system; Fig. 4 A has explained a kind of cross section of package system, and package system comprises the multi-chip module 330 that has microchannel 165 (fluid passage just) and fluid intake and interface channel 305.Syndeton 305 utilizes hermetically-sealed construction (comprising seal 310,315 and 317) and external environment to isolate.The wherein sealing between seal 310 realization syndetons 305 and the substrate 340, the sealing that seal 315 and 317 is realized between syndetons 305 and the multi-chip module 330.
The fin 320 of two integrated circuit dies 325 is placed on the inside of coupling radiator structure 330 as internal heat dissipation structures, and substrate 340 provides the mechanical support of whole system, and system and the electrical connection of circuit board are through contacting contact 343 and 345 realizations.Fluid is respectively first temperature T 1 at the characteristic parameter at inlet 350 places of syndeton 305; At the first flow velocity V1 and first pressure through microchannel 165; Characteristic parameter at outlet 360 places is respectively second temperature T, 2＞T1, the second flow velocity V2 and second pressure P, 2＞P1.Shown in Fig. 4 B, the cross section of package system and seal member 310,315 and 317 has been described, this cross section is to carry out observable in 370 position shown in Fig. 4 A figure through cutting line A-B.
Fig. 5 show comprise integrated circuit heat dissipation device of the present invention and the 3rd embodiment sketch map of cooling system; Being one and including multi-chip module 330, the fluid passage 467 (also can be described as the microchannel) of the inside of microchannel 165 in the assembly (fluid passage just) and setting and board structure of Fig. 5 A explanation.Fluid in the syndeton 420 is respectively first temperature T 1 at the characteristic parameter at inlet 350 places; And the first flow velocity V1 of the gas in microchannel 165 and 467 and first pressure P 1; Also the characteristic parameter at outlet 450 places is respectively second temperature T, 2＞T1 in addition, and the gas second flow velocity V2 and second pressure P, 2＞P1 in microchannel 165 (fluid passage just) and 467.Its middle outlet 450 and inlet 350 isolation are that the hermetically-sealed construction (comprising seal 319,315 and 317) through standard is realized.Microchannel 467 (fluid passage just) is flowed the uniformity in pipeline of gas/liquid.
The microchannel 415 (fluid passage just) that includes fluid liquid in the external structure 410 of fluid cooling coupled structure 420.Wherein, the heat eliminating medium that flows in the microchannel 415 is a kind of incompressible fluid, and this radiator structure can dispel the heat to circuit chip 325.Contact contact 430 is for providing heat conducting passage between IC chip 325 and the cooling structure 410 in fluid cooling coupled structure 420.IC chip and circuit board pass through syndeton 343 and 345 and the opening 460 in fluid cooling coupled structure 420 realize being electrically connected.Shown in Fig. 5 B, the cross section of package system and seal member 315 and 317 has been described, this cross section is to carry out observable in 470 position shown in Fig. 5 A figure through cutting line A-B.
Fig. 6 show comprise integrated circuit heat dissipation device of the present invention and the 4th embodiment sketch map of cooling system.The elaboration that Fig. 6 A part is detailed the sectional view of this embodiment, comprise the transmission channel (with the similar summary of Fig. 5 embodiment) of multi-chip module 330 and fluid.This view is through watching in 570 position at the cutaway view of Fig. 6 C part along the A-C line, can seeing the coupling radiator structure 420 of its fluid passage and the hermetically-sealed construction 315 between the substrate 340.Realize being electrically connected with circuit board through syndeton 343 and 345, wherein fluid coupling radiator structure 420 communicates with extraneous through opening 460 parts.
Fig. 6 B partly is the cross-sectional view of present embodiment, includes the transmission channel of multi-chip module 330 and fluid equally.Second view is through watching in 570 position at the cutaway view of Fig. 6 C part along the B-C line.
Shown in Fig. 6 C is the horizontal sectional view of present embodiment, can see the hermetically-sealed construction 315 between substrate 340 and the coupling radiator structure 420.Also can see simultaneously the bare chip 325 of integrated circuit, and the space 460 of the opening on substrate 340 is electrically connected through some and realizes and the combining of circuit board.The inlet of refrigerating gas is among the figure shown in 350.
The present invention can be used for the multi-chip module of the vertical or planar interconnect of cooling integrated circuit.The present invention can strengthen the pipeline pyroconductivity.
The present invention can be further used for processor and the outer extension of processor, and level cache nearest on the multi core chip carrier carries out transfer of data.External cache and processor chip carry out high speed data transfer through the wide dedicated bus of multidigit in the multinuclear module.Outside buffer memory can be placed near multi core chip.
The present invention can be further used in the high performance system.Specifically, three-dimensional comprehensive static RAM (SDRAM) of these high performance system configurations or embedded type dynamic random access memory (EDRAM).This memory of two types generally all is integrated among the processor chip of the confined space.Be accompanied by the increase of the quantity of processor, it can be placed near the high-speed cache of urgent need, but outside processor.This strategy need pile up with runner at the enterprising row cache of multi-chip module and cool off.
Invention be also embodied in multi-chip module and cool off the overall rate of heat dispation that improves processor and other IC chips through the pipe interior fluid, in addition, the approach of outside liquid cooling and heat conductivity can help to improve radiating efficiency.
Invention be also embodied in and be used for metal and the semiconductor layer conduction cooling of multi-chip module through interior embedded hole is arranged and improve the processor thermal conductivity.
Multi-chip module improves usefulness through shorter through hole among the present invention.According to structure of the present invention, the integral thickness expectation meeting of multi-chip module is much littler than the ceramic multi-chip module of the metal level with equal number.This can cause stray inductance, electric capacity, resistance to reduce, thereby needs buffer still less to revise clock jitter and distorted signals.The littler through hole that adopts with respect to ceramic multi-chip module the present invention causes shorter propagation delay and memory access latency still less.
In yet another aspect, because the factor of material and structure, it is infeasible that ceramic multi-chip module reaches the wiring density that meets the WeiLai Technology requirement.The wire laying mode that the design of multi-chip module of the present invention and structure are used can be used to realize the high wiring density of integrated circuit through pneumatic cooling pipe.
The foregoing description is a preferred implementation of the present invention; But execution mode of the present invention is not restricted to the described embodiments; Other any do not deviate from change, the modification done under spirit of the present invention and the principle, substitutes, combination, simplify; All should be the substitute mode of equivalence, be included within protection scope of the present invention.
Claims (16)
1. a cooling integrated system is characterized in that, comprises at least three laminar substrates: top substrate layer, interlayer substrate reach laminar substrate down, form the microchannel between adjacent substrate;
Establish conductive path in said three laminar substrates are equal, wherein top substrate layer is electrically connected with IC chip through said conductive path, passes the microchannel through said conductive path between adjacent substrate and is electrically connected, and following laminar substrate is connected with external electric through said conductive path.
2. cooling system according to claim 1 is characterized in that, said top substrate layer is a semiconductor substrate, and the interlayer substrate is a metal substrate, and following laminar substrate is a semiconductor substrate.
3. cooling system according to claim 1; It is characterized in that; The conductive path of said top substrate layer comprises the salient point of upper surface to be electrically connected with said IC chip that is arranged at said top substrate layer; Be arranged at the lower surface of said top substrate layer and be arranged in and said microchannel that said interlayer substrate forms and the salient point that is electrically connected with the conductive path of said interlayer substrate, and it is interior and be electrically connected the electric conductor of the salient point of said upper surface and lower surface to be arranged at said top substrate layer.
4. cooling system according to claim 3; It is characterized in that; The surface of said top substrate layer is provided with insulating barrier, in the said insulating barrier network of conductors is set, and said network of conductors is electrically connected said IC chip and said electric conductor as the part of the conductive path of said top substrate layer.
5. cooling system according to claim 1; It is characterized in that; The conductive path of said interlayer substrate comprises the upper surface that is arranged at this interlayer substrate and/or the salient point of lower surface; Said salient point is arranged in the microchannel that forms with adjacent substrate and is electrically connected with the conductive path of said adjacent substrate, and it is interior and be electrically connected the electric conductor of said salient point to be arranged at said interlayer substrate.
6. cooling system according to claim 5; It is characterized in that; The surface of said interlayer substrate is provided with insulating barrier; In the said insulating barrier network of conductors is set, said network of conductors is electrically connected the conductive path of said top substrate layer and the electric conductor of said interlayer substrate as the part of the conductive paths of said interlayer substrate.
7. cooling system according to claim 1; It is characterized in that; The conductive path of said down laminar substrate comprises the upper surface and the salient point of lower surface that is arranged at said laminar substrate down, and the electric conductor that is arranged at the salient point of the said upper surface of electrical connection and lower surface in the said laminar substrate down;
Wherein, the said salient point that is arranged at upper surface is arranged in the microchannel of adjacent substrate formation and with the conductive path of said adjacent substrate and is electrically connected; The said salient point that is arranged at lower surface is connected with external electric.
8. cooling system according to claim 7; It is characterized in that; The said surface of laminar substrate down is provided with insulating barrier; In this insulating barrier network of conductors is set, said network of conductors is electrically connected the conductive path of said interlayer substrate and the electric conductor of this time laminar substrate as the said part of the conductive path of laminar substrate down.
9. according to each described cooling system in the claim 3 to 8, it is characterized in that said salient point and/or electric conductor form through electrodeposit metals technology or form through electro-deposition multi-element metal technology.
10. according to each described cooling system in the claim 3 to 8, it is characterized in that said electric conductor is arranged in the formed electrical connection through hole of counterpart substrate, said electrical connection through hole periphery is provided with insulating barrier and barrier layer.
11., it is characterized in that at least one laminar substrate set inside microchannel in said three laminar substrates according to each described cooling system in the claim 1 to 8.
12. according to each described cooling system in the claim 1 to 8, it is characterized in that, also comprise outside heat sink or external fluid radiator structure.
13., it is characterized in that this cooling system is isolated through seal and external environment condition according to each described cooling system in the claim 1 to 8.
14. according to each described cooling system in the claim 1 to 8, it is characterized in that this cooling system is applied to the heat radiation of multi-chip module, said IC chip is a multi-chip module.
15. the manufacture method of interlayer substrate in the said cooling integrated system of claim 1 may further comprise the steps:
Steps A: deposit passivation layer is coated with photosensitive material in passivation layer in substrate layer, under the mask of mask, makes public;
Step B: remove the outer light-sensitive material of said mask masks area;
Step C: the deposition Seed Layer is in the surface of the expose portion of said light-sensitive material and passivation layer;
Step D: depositing metal layers is on Seed Layer;
Step e: the said metal level of attenuate and planarization obtains smooth surface;
Step F: remove the residue light-sensitive material and obtain metal structure;
Step G: make insulating barrier and Seed Layer in the exposed surface of said metal structure and passivation layer;
Step H: depositing metal layers is in Seed Layer described in the step G;
Step I: metal level described in the step obtains smooth surface on attenuate and the planarization, makes passivation layer in this surface;
Step J: remove substrate layer, the back side of the structure that obtains in above-mentioned steps is coated with photosensitive material, and the hole of the metal level that the etching technics through photoetching process and passivation layer obtains to deposit among the said step H of connection is made Seed Layer on the exposed surface of this hole;
Step K: make metal level above the described Seed Layer of step J;
Step L: the metal level among attenuate and the planarization treatment step K obtains smooth surface;
Step M: remaining light-sensitive material obtains bump structure among the removal step J.
16. manufacture method according to claim 15 is characterized in that, also comprises after the step M:
Step N: the interlayer substrate to form among the step M is the basis, simultaneously makes the connection salient point at it, and another side is made the insulating barrier that includes built-in conductive network, obtains repetitive;
Several same said repetitive is carried out lamination; Wherein, the insulating barrier of a repetitive is connected with the salient point of another repetitive.
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| CN115084059A (en) * | 2022-08-16 | 2022-09-20 | 杭州飞仕得科技有限公司 | Preparation method of insulating substrate and power device packaging method |
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