CN102456661A - Chip structure with rewired circuit layer and manufacturing method thereof - Google Patents
Chip structure with rewired circuit layer and manufacturing method thereof Download PDFInfo
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- CN102456661A CN102456661A CN201010517475XA CN201010517475A CN102456661A CN 102456661 A CN102456661 A CN 102456661A CN 201010517475X A CN201010517475X A CN 201010517475XA CN 201010517475 A CN201010517475 A CN 201010517475A CN 102456661 A CN102456661 A CN 102456661A
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Abstract
The invention discloses a chip structure with a rewired circuit layer and a manufacturing method thereof, wherein the chip structure with the rewired circuit layer comprises a chip, a first passivating layer, the rewired circuit layer and a second passivating layer; the chip is provided with a plurality of electrode pads; the first passivating layer is arranged on an acting surface of the chip and the electrode pads; the rewired circuit layer is formed on the first passivating layer and is provided with a plurality of circuit units, each circuit unit is provided with an electrical connection pad, a conductive blind hole and a conductive trace for connecting the electric connection pad and the conductive blind hole, and the conductive trace is provided with at least one first through opening which allows part of the first passivating layer to be exposed; the second passivating layer is arranged on the first passivating layer and the rewired circuit layer and is filled in the first through openings of the conductive traces so as to be combined with the first passivating layer to vertically clamp the conductive traces, thus, better combinability can be achieved, and stripping between the conducting traces and the second passivating layer can be prevented.
Description
Technical field
The present invention relates to a kind of chip structure and method for making thereof, particularly relate to a kind of chip structure with rerouting line layer and the method for making thereof that can avoid this rerouting circuit delamination layer with rerouting line layer.
Background technology
Flourish along with electronic industry, electronic product also marches toward multi-functional, high performance R&D direction gradually.Base plate for packaging in order to the bearing semiconductor chip includes routing type base plate for packaging, chip size packages (CSP) substrate and covers brilliant substrate (FCBGA) etc. at present; And be the computing needs in response to microprocessor, chipset and drawing chip, the base plate for packaging that is furnished with circuit also need promote its quality of transmitting chip signal, improve functions such as frequency range, control group, to count the development of packaging part in response to high I/O.
In existing encapsulation technology; Be semiconductor chip electrically to be connect place on the base plate for packaging; Dispose electronic pads (electronic pad) on the surface of this semiconductor integrated circuit (IC) chip; And this base plate for packaging has corresponding electric contact mat, and between this semiconductor chip and base plate for packaging, conductive projection, other conductive adhesive materials or gold thread can be set suitably, and this semiconductor chip is electrically connected on this base plate for packaging.
Again in encapsulation technology now, for reaching demand multi-functional, high operating power, thereby derive the encapsulating structure product that a kind of semiconductor package part piles up mutually.And in order to satisfy the package requirements of the high degree of integration of semiconductor package part (integration) and microminiaturized (miniaturization); Utilize the road layer technological (RDL:Redistribution Layer) that reroutes and have; Make chip area more fully to use, and then promote usefulness.
For example United States Patent (USP) the 7th, 170, promptly discloses a kind of existing chip structure with rerouting line layer No. 160, for chip-stacked, and electrically connects the chip that piles up with the routing mode, uses the reduction packaging height.
See also Figure 1A and Figure 1B, for the vertical view of the chip structure with rerouting line layer of above-mentioned United States Patent (USP) and cover the cross-sectional schematic of passivation layer.As shown in the figure; Be on a surface of a chip 10, to be provided with a plurality of electronic padses 11; And first passivation layer (passivation layer) 12a is arranged at this chip 10 and said electronic pads 11 surface coverage; And be formed with a plurality of first perforate 120a among this first passivation layer 12a, order respectively these electronic pads 11 correspondences exposes to respectively among this first perforate 120a, and on this first passivation layer 12a, forms rerouting line layer 13; And in this first perforate 120a, form conductive blind hole 130 to electrically connect this electronic pads 11; And this rerouting line layer 13 has a plurality of a plurality of electric connection pads 131 and those widened sections 132 that are positioned on this first passivation layer 12a, to improve electrically through this those widened sections 132, on this first passivation layer 12a and rerouting line layer 13, covers the second passivation layer 12b again; And in this second passivation layer 12b, form a plurality of second perforate 120b, order respectively these electric connection pad 131 correspondences exposes to respectively this second perforate 120b.
But the area of the those widened sections 132 of above-mentioned rerouting line layer 13 is big, and this those widened sections 132 is a metal; And this first passivation layer 12a or the second passivation layer 12b are nonmetal; According to properties of materials, this metal and nonmetal between associativity relatively poor, cause the conjugation between this those widened sections 132 and the second passivation layer 12b to reduce; Cause this second passivation layer 12b to be easy to generate the phenomenon of peeling off, and reduce the quality that electrically connects.
Therefore, how a kind of chip structure and method for making thereof with rerouting line layer being provided, can avoiding the those widened sections of rerouting line layer and second passivation layer to produce the phenomenon of peeling off, and reduce the situation that electrically connects quality, is an important topic in fact.
Summary of the invention
Many disadvantages in view of above-mentioned prior art; A purpose of the present invention is to be to provide a kind of chip structure and method for making thereof with rerouting line layer, in order to can produce the problem of peeling off between the those widened sections that solves rerouting line layer in the prior art and second passivation layer.
For reaching above-mentioned and other purposes, the present invention provides a kind of chip structure with rerouting line layer, is to comprise: chip has relative acting surface and non-acting surface, and has a plurality of electronic padses on this acting surface; First passivation layer is located on the acting surface and electronic pads of this chip, and is formed with a plurality of first perforates in this first passivation layer, to expose respectively this electronic pads; The rerouting line layer; Be formed on this first passivation layer; This rerouting line layer has a plurality of line units; Respectively this line unit has electric connection pad, is formed at conductive blind hole in this first perforate, and connects the conductive trace of this electric connection pad and conductive blind hole, and this conductive trace has at least one first and runs through opening, exposes to this with first passivation layer of order part and first runs through opening; And second passivation layer, being formed on this first passivation layer and the rerouting line layer, this second passivation layer also fills in first of this conductive trace and runs through in the opening, and this second passivation layer is formed with a plurality of second perforates, to expose this electric connection pad.
Described chip structure with rerouting line layer, this rerouting line layer is made up of crystal seed layer and metal level in regular turn.
For achieving the above object, the present invention also provides a kind of method for making with chip structure of rerouting line layer, comprising: provide one to have the relative acting surface and the chip of non-acting surface, and have a plurality of electronic padses on this acting surface; On the acting surface of this chip and electronic pads, cover first passivation layer, and make and form a plurality of first perforates in this first passivation layer, to expose respectively this electronic pads; On this first passivation layer, form this rerouting line layer; This rerouting line layer has a plurality of line units; Respectively this line unit has electric connection pad, is formed at conductive blind hole in this first perforate, and connects the conductive trace of this electric connection pad and conductive blind hole; This conductive trace has at least one first and runs through opening, exposes to this with first passivation layer of order part and first runs through opening; And on this first passivation layer and rerouting line layer, covering second passivation layer, this second passivation layer also fills in first of this conductive trace and runs through opening, and in this second passivation layer, forms a plurality of second perforates, to expose respectively this electric connection pad.
In the method for making of described chip structure with rerouting line layer, the method for making of this rerouting line layer is to comprise: on this first passivation layer, the hole wall of first perforate, and first perforate in electronic pads on form crystal seed layer; On this crystal seed layer, form photoresist layer, and in this photoresist layer, form a plurality of photoresist layer openings, expose in the said photoresist layer opening with order crystal seed layer partly; Form metal level on the crystal seed layer in this photoresist layer opening; And the crystal seed layer that removes this photoresist layer and covered.
According to above-mentioned method for making, the material that forms this crystal seed layer in regular turn by titanium (Ti), titanium tungsten (TiW), and gold (Au) form; The material that forms this metal level again is gold (Au).
According to the above chip structure with rerouting line layer and method for making thereof, this first run through opening pass can be polygonal, circle or quincunx.
According to the above chip structure with rerouting line layer and method for making thereof, this conductive trace has those widened sections and connects the neck at these those widened sections two ends again, and this first runs through opening and be formed on this those widened sections.The neck that the step that forms this rerouting line layer again also can be included in this rerouting line layer forms second and runs through opening, wherein, this second run through opening can be at the neck between the neck between this those widened sections and the conductive blind hole or this those widened sections and the electric connection pad.Described second run through opening pass can be polygonal, circle or quincunx.
By on can know; The present invention has the chip structure and the method for making thereof of rerouting line layer; Be to form earlier first passivation layer, on this first passivation layer, form the rerouting line layer afterwards and electrically connect this electronic pads, and the line unit of this rerouting line layer has electric connection pad, is formed at conductive blind hole in this first perforate, and connect the conductive trace of this electric connection pad and conductive blind hole on this surface with chip of a plurality of electronic padses; This conductive trace has at least one first and runs through opening; Expose to this with first passivation layer of order part and first run through opening, last, on this first passivation layer and rerouting line layer, form second passivation layer; And this second passivation layer is also inserted first and is run through in the opening; Combining with this first passivation layer, and this second passivation layer first runs through opening and runs through this conductive trace and be combined on first passivation layer through this, and through this second passivation layer and first passivation layer combine and up and down folder establish this conductive trace; Thereby preferable associativity can be arranged, peel off to prevent to produce between this conductive trace and second passivation layer.
Description of drawings
Figure 1A and Figure 1B are United States Patent (USP) the 7th, 170, the cross-sectional schematic of No. 160 vertical view and covering passivation layer;
Fig. 2 A to Fig. 2 G is the have chip structure of rerouting line layer and the sketch map of method for making thereof of the present invention; Wherein, this Fig. 2 F ' is the vertical view of this 2F figure;
Fig. 3 A and Fig. 3 B are the have chip structure of rerouting line layer and another embodiment vertical view of method for making thereof of the present invention.
The main element symbol description:
10 chips, 11 electronic padses
The 12a first passivation layer 120a first perforate
The 12b second passivation layer 120b second perforate
13 rerouting line layers, 130 conductive blind holes
131 electric connection pads, 132 those widened sections
20 chip 20a acting surfaces
Non-acting surface 21 electronic padses of 20b
The 22a first passivation layer 220a first perforate
The 22b second passivation layer 220b second perforate
23 crystal seed layers, 24 photoresist layers
240 photoresist layer openings, 25 metal levels
26 rerouting line layer 26a line units
260a first runs through opening 260b second and runs through opening
261 conductive blind holes, 262 electric connection pads
263 conductive traces, 2631 those widened sections
2632 necks
Embodiment
Below through particular specific embodiment execution mode of the present invention is described, the technical staff in present technique field can understand other advantages of the present invention and effect easily by the content that this specification disclosed.
Notice; The appended graphic structure that illustrates of this specification, ratio, size etc.; All only in order to cooperating the content that specification disclosed,, be not in order to limit the enforceable qualifications of the present invention for the technical staff's in present technique field understanding and reading; Event is the technical essential meaning of tool not; The adjustment of the modification of any structure, the change of proportionate relationship or size not influencing under effect that the present invention can produce and the purpose that can reach, all should still drop on disclosed technology contents and get in the scope that can contain.
See also Fig. 2 A to Fig. 2 G, be a kind of method for making provided by the present invention with chip structure of rerouting line layer.
Shown in Fig. 2 A, at first, provide one to have relative acting surface 20a and the chip 20 of non-acting surface 20b, on this acting surface 20a, have a plurality of electronic padses 21.
Shown in Fig. 2 B, on the acting surface 20a of this chip 20 and electronic pads 21, cover the first passivation layer 22a, and in this first passivation layer 22a, form a plurality of first perforate 220a, to expose respectively this electronic pads 21.
Shown in Fig. 2 C, on this first passivation layer 22a, the hole wall of the first perforate 220a, and the first perforate 220a in electronic pads 21 on form crystal seed layer 23, the material that forms this crystal seed layer 23 can be made up of titanium, titanium tungsten and gold in regular turn.
Shown in Fig. 2 D, on this crystal seed layer 23, form photoresist layer 24, and in this photoresist layer 24, form a plurality of photoresist layer openings 240, expose in the said photoresist layer opening 240 with order crystal seed layer 23 partly.
Shown in Fig. 2 E, form metal level 25 on the crystal seed layer 23 in this photoresist layer opening 240, the material that forms this metal level 25 can be gold.
Shown in Fig. 2 F and Fig. 2 F '; The crystal seed layer 23 that removes this photoresist layer 24 and covered; On this first passivation layer 22a, to form the rerouting line layer of being formed by this metal level 25 and crystal seed layer 23 26; This rerouting line layer 26 has a plurality of line unit 26a; Respectively this line unit 26a has electric connection pad 262, is formed among this first perforate 220a and the conductive trace 263 that electrically connects the conductive blind hole 261 of this electronic pads 21 and connect this electric connection pad 262 and conductive blind hole 261, and this conductive trace 263 has at least one first and runs through opening 260a, exposes to this with the first passivation layer 22a of order part and first runs through opening 260a.Particularly, this conductive trace 263 has those widened sections 2631 and connects the neck 2632 at these those widened sections 2631 two ends, and this first runs through opening 260a and can be formed on this those widened sections 2631.This those widened sections 2631 has at least one pass and runs through opening 260a for ellipse, polygonal, circle or quincuncial first, exposes to this with the order first passivation layer 22a partly and first runs through opening 260a.
Shown in Fig. 2 G; On this first passivation layer 22a and rerouting line layer 26, cover the second passivation layer 22b; This second passivation layer 22b and fill in this conductive trace 263 those widened sections 2631 first run through opening 260a, to combine with this first passivation layer 22a, this second passivation layer 22b and the first passivation layer 22a are the congeniality material again; So preferable associativity is arranged; And this second passivation layer 22b first runs through opening 260a and runs through this conductive trace 263 and be combined on this first passivation layer 22a through this, thereby preferable associativity can be arranged, and peels off to produce between the those widened sections 2631 that prevents this conductive trace 263 and the second passivation layer 22b.In this second passivation layer 22b, form a plurality of second perforate 220b again, these electric connection pad 262 correspondences expose to respectively this second perforate 220b to make respectively.
See also in another specific embodiment shown in Fig. 3 A and Fig. 3 B, the neck 2632 that the step that forms this rerouting line layer 26 also can be included in this rerouting line layer 26 forms second and runs through opening 260b, and this first runs through opening 260a and can be polygonal.Shown in Fig. 3 A, this second runs through opening 260b on the neck 2632 between this those widened sections 2631 and the electric connection pad 262; Or shown in Fig. 3 B, this second runs through opening 260b on the neck 2632 between this those widened sections 2631 and the conductive blind hole 261.Described second runs through opening 260b can be polygonal, ellipse, circle or quincunx.Thereby can second run through opening 260b and provide this second passivation layer 22b to insert and combine through this, and better associativity can be provided, peel off to produce between the neck 2632 of avoiding this rerouting line layer 26 and the second passivation layer 22b with this first passivation layer 22a.
The present invention also provides a kind of chip structure with rerouting line layer, comprising: chip 20 has relative acting surface 20a and non-acting surface 20b, and has a plurality of electronic padses 21 on this acting surface 20a; The first passivation layer 22a is located on the acting surface 20a and electronic pads 21 of this chip 20, and is formed with a plurality of first perforate 220a among this first passivation layer 22a, to expose respectively this electronic pads 21; Rerouting line layer 26; Be located on this first passivation layer 22a; This rerouting line layer 26 has a plurality of line unit 26a; Respectively this line unit 26a has electric connection pad 262, is formed at conductive blind hole 261 among this first perforate 220a, and connects the conductive trace 263 of this electric connection pad 262 and conductive blind hole 261, and this conductive trace 263 has at least one first and runs through opening 260a, exposes to this with the first passivation layer 22a of order part and first runs through opening 260a; And the second passivation layer 22b; Be located on this first passivation layer 22a and the rerouting line layer 26; This second passivation layer 22b also fills in first of this conductive trace 263 and runs through among the opening 260a, and in this second passivation layer 22b, forms a plurality of second perforate 220b, to expose respectively this electric connection pad 262.
Described chip structure with rerouting line layer, this rerouting line layer 26 is made up of crystal seed layer 23 and metal level 25 in regular turn.
Particularly, this conductive trace 263 has those widened sections 2631 and connects the neck 2632 at these those widened sections 2631 two ends, and this first runs through opening 260a and be formed at this those widened sections 2631.Run through opening 260a according to above-mentioned first and can be polygonal, ellipse, circle or quincunx.In addition, the chip structure with rerouting line layer of the present invention can comprise that also second runs through opening 260b, is formed at neck 2632.And this second runs through opening 260b and can be polygonal, ellipse, circle or quincunx.Moreover this second runs through the neck 2632 of opening 260b between the neck 2632 between this those widened sections 2631 and the electronic pads 21 or this those widened sections 2631 and electric connection pad 262.
The present invention has the chip structure and the method for making thereof of rerouting line layer, is to form first passivation layer earlier on this surface with chip of a plurality of electronic padses, and forms a plurality of first perforates in this first passivation layer; This electronic pads correspondence exposes to respectively this first perforate to make respectively; On this first passivation layer, form the rerouting line layer afterwards, and the corresponding conductive blind hole that forms is electrically connecting this electronic pads in this first perforate respectively, and this rerouting line layer has a plurality of electric connection pads and at least one those widened sections; This those widened sections has at least one first and runs through opening; Expose to this with first passivation layer of order part and first run through opening, last, on this first passivation layer and rerouting line layer, form second passivation layer; And this second passivation layer also fills in first of this those widened sections and runs through in the opening; Combining with this first passivation layer, and this second passivation layer and first passivation layer are the congeniality material, so preferable associativity is arranged; And this second passivation layer first runs through opening and runs through this those widened sections and be combined on first passivation layer through this; And through this second passivation layer and first passivation layer combine and up and down folder establish this those widened sections, thereby preferable associativity can be arranged, peel off to prevent to produce between this those widened sections and second passivation layer.
Moreover; Be provided with second at this rerouting line layer and run through opening; And this second runs through opening on the neck circuit between this those widened sections and the electric connection pad, or on the neck circuit between those widened sections and the electronic pads, inserts and combines with this first passivation layer so that this second passivation layer to be provided; And better associativity can be provided, peel off near producing between the neck of this those widened sections and second passivation layer to avoid this rerouting line layer.
The foregoing description is in order to illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art of the present technique all can make amendment to the foregoing description under spirit of the present invention and category.Therefore rights protection scope of the present invention should be foundation with the scope of claims.
Claims (15)
1. the chip structure with rerouting line layer is characterized in that, comprising:
Chip has relative acting surface and non-acting surface, and has a plurality of electronic padses on this acting surface;
First passivation layer is located on the acting surface and electronic pads of this chip, and is formed with a plurality of first perforates in this first passivation layer, to expose respectively this electronic pads;
The rerouting line layer; Be formed on this first passivation layer; This rerouting line layer has a plurality of line units; Respectively this line unit has electric connection pad, is formed at conductive blind hole in this first perforate, and connects the conductive trace of this electric connection pad and conductive blind hole, and this conductive trace has at least one first and runs through opening, exposes to this with first passivation layer of order part and first runs through opening; And
Second passivation layer is formed on this first passivation layer and the rerouting line layer, and this second passivation layer also fills in first of this conductive trace and runs through in the opening, and this second passivation layer is formed with a plurality of second perforates, to expose this electric connection pad.
2. the chip structure with rerouting line layer according to claim 1 is characterized in that, this rerouting line layer is made up of crystal seed layer and metal level in regular turn.
3. the chip structure with rerouting line layer according to claim 1 is characterized in that, first to run through opening be polygonal, ellipse, circle or quincunx for this.
4. the chip structure with rerouting line layer according to claim 1 is characterized in that, this conductive trace has those widened sections and connects the neck of this those widened sections, electric connection pad and conductive blind hole, and this first runs through opening and be formed on this those widened sections.
5. the chip structure with rerouting line layer according to claim 4 is characterized in that, comprises that also second runs through opening, the neck between the neck between this those widened sections and the conductive blind hole or this those widened sections and electric connection pad.
6. the chip structure with rerouting line layer according to claim 5 is characterized in that, this second run through opening pass be polygonal, ellipse, circle or quincunx.
7. the method for making with chip structure of rerouting line layer is characterized in that, comprising:
Provide one to have the relative acting surface and the chip of non-acting surface, and have a plurality of electronic padses on this acting surface;
On the acting surface of this chip and electronic pads, cover first passivation layer, and make and form a plurality of first perforates in this first passivation layer, to expose respectively this electronic pads;
On this first passivation layer, form this rerouting line layer; This rerouting line layer has a plurality of line units; Respectively this line unit has electric connection pad, is formed at conductive blind hole in this first perforate, and connects the conductive trace of this electric connection pad and conductive blind hole; This conductive trace has at least one first and runs through opening, exposes to this with first passivation layer of order part and first runs through opening; And
On this first passivation layer and rerouting line layer, cover second passivation layer, this second passivation layer also fills in first of this conductive trace and runs through opening, and in this second passivation layer, forms a plurality of second perforates, to expose respectively this electric connection pad.
8. the method for making with chip structure of rerouting line layer according to claim 7 is characterized in that, first to run through opening be polygonal, ellipse, circle or quincunx for this.
9. the method for making with chip structure of rerouting line layer according to claim 7; It is characterized in that; This conductive trace has those widened sections and connects the neck of this those widened sections, electric connection pad and conductive blind hole, and this first runs through opening and be formed on this those widened sections.
10. the method for making with chip structure of rerouting line layer according to claim 9 is characterized in that, the neck that the step that forms this rerouting line layer also is included in this rerouting line layer forms second and runs through opening.
11. the method for making with chip structure of rerouting line layer according to claim 10 is characterized in that, this second runs through the neck of opening between the neck between this those widened sections and the conductive blind hole or this those widened sections and electric connection pad.
12. according to claim 10 or 11 described method for makings, it is characterized in that with chip structure of rerouting line layer, this second run through opening pass be polygonal, ellipse, circle or quincunx.
13. the method for making with chip structure of rerouting line layer according to claim 7, wherein, the manufacturing process of this rerouting line layer comprises:
On this first passivation layer, on the hole wall of first perforate and the electronic pads in first perforate, form crystal seed layer;
On this crystal seed layer, form photoresist layer, and in this photoresist layer, form a plurality of photoresist layer openings, expose in the said photoresist layer opening with order crystal seed layer partly;
Form metal level on the crystal seed layer in this photoresist layer opening; And
The crystal seed layer that removes this photoresist layer and covered.
14. the method for making with chip structure of rerouting line layer according to claim 13 is characterized in that, the material that forms this crystal seed layer is made up of titanium, titanium tungsten and gold in regular turn.
15. the method for making with chip structure of rerouting line layer according to claim 13 is characterized in that, the material that forms this metal level is gold.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010517475XA CN102456661A (en) | 2010-10-19 | 2010-10-19 | Chip structure with rewired circuit layer and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010517475XA CN102456661A (en) | 2010-10-19 | 2010-10-19 | Chip structure with rewired circuit layer and manufacturing method thereof |
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| CN102456661A true CN102456661A (en) | 2012-05-16 |
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| CN201010517475XA Pending CN102456661A (en) | 2010-10-19 | 2010-10-19 | Chip structure with rewired circuit layer and manufacturing method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104078442A (en) * | 2013-03-26 | 2014-10-01 | 南茂科技股份有限公司 | Chip structure and manufacturing method thereof |
| CN109145342A (en) * | 2017-06-16 | 2019-01-04 | 矽品精密工业股份有限公司 | Automatic wiring system and method |
| CN109524377A (en) * | 2018-11-19 | 2019-03-26 | 武汉新芯集成电路制造有限公司 | A kind of rewiring structure of chip |
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| US20020139578A1 (en) * | 2001-03-28 | 2002-10-03 | International Business Machines Corporation | Hyperbga buildup laminate |
| US20080217772A1 (en) * | 2007-03-05 | 2008-09-11 | Oki Electric Industry Co., Ltd. | Semiconductor device manufacturing method and semiconductor device |
| CN101582397A (en) * | 2008-05-16 | 2009-11-18 | 精材科技股份有限公司 | Semiconductor device and manufacturing method thereof |
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- 2010-10-19 CN CN201010517475XA patent/CN102456661A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020139578A1 (en) * | 2001-03-28 | 2002-10-03 | International Business Machines Corporation | Hyperbga buildup laminate |
| US20080217772A1 (en) * | 2007-03-05 | 2008-09-11 | Oki Electric Industry Co., Ltd. | Semiconductor device manufacturing method and semiconductor device |
| CN101582397A (en) * | 2008-05-16 | 2009-11-18 | 精材科技股份有限公司 | Semiconductor device and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104078442A (en) * | 2013-03-26 | 2014-10-01 | 南茂科技股份有限公司 | Chip structure and manufacturing method thereof |
| CN109145342A (en) * | 2017-06-16 | 2019-01-04 | 矽品精密工业股份有限公司 | Automatic wiring system and method |
| CN109524377A (en) * | 2018-11-19 | 2019-03-26 | 武汉新芯集成电路制造有限公司 | A kind of rewiring structure of chip |
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Application publication date: 20120516 |