CN102403239B - 半导体器件及形成用于在Fo‑WLCSP中安装半导体小片的引线上键合互连的方法 - Google Patents

半导体器件及形成用于在Fo‑WLCSP中安装半导体小片的引线上键合互连的方法 Download PDF

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CN102403239B
CN102403239B CN201110278186.3A CN201110278186A CN102403239B CN 102403239 B CN102403239 B CN 102403239B CN 201110278186 A CN201110278186 A CN 201110278186A CN 102403239 B CN102403239 B CN 102403239B
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conductive layer
trace
semiconductor chip
carrier
sealant
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CN102403239A (zh
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R·A·帕盖拉
R·D·彭德斯
具俊谟
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

半导体器件及形成用于在Fo‑WLCSP中安装半导体小片的引线上键合互连的方法。一种半导体小片，具有形成在载体上的包括多个迹线的导电层。导电层包括与迹线在电连续的多个触点焊盘。半导体小片具有多个触点焊盘和形成在触点焊盘上的凸块。多个导电柱可以形成在半导体小片的触点焊盘上方。凸块可以形成在导电柱上。半导体小片以凸块直接键合到迹线的端部的方式安装至导电层，以提供细小间距的互连。密封剂沉积在半导体小片和导电层上。导电层包含可湿性材料，以减少封装期间的小片移动。载体被去除。互连结构形成在密封剂和半导体小片上方。绝缘层可以形成在导电层上。

Description

半导体器件及形成用于在Fo-WLCSP中安装半导体小片的引线 上键合互连的方法
技术领域
本发明一般涉及半导体器件，并且更具体地涉及半导体衬底以及形成用于在外引脚式晶圆级芯片尺寸封装(Fo-WLCAP)中安装半导体小片的引线上键合或迹线上键合互连的方法。
背景技术
半导体器件普遍存在于现代电子产品中。半导体器件在电子元件的数量和密集度上不同。分立半导体器件通常含有一种类型的电子元件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器、以及粉末金属氧化物半导体场效应晶体管(MOSEFT)。集成半导体器件一般包含数百至数百万个电子元件。集成半导体器件的例子包括微控制器、微处理器、电耦合器件(CCD)、太阳能电池、以及数字微镜设备(DMD)。
半导体器件所执行的功能范围广泛，如信号处理、高速计算、发射和接收电磁信号、控制电子设备、将太阳光转化为电力、以及为电视显示器创建视觉投影。半导体器件存在于娱乐、通信、动力转换、网络、计算机以及消费品领域。半导体器件还存在于军事应用、航空、汽车、工业控制器、以及办公设备中。
半导体器件利用半导体材料的电特性。半导体材料的原子结构使得其导电性能够通过电场或基电流的施加、或者通过进行掺杂处理来操纵。掺杂将杂质引入到半导体材料中，从而操纵和控制半导体器件的导电性。
半导体器件包含有源和无源电结构。包括双极型晶体管和场效应晶体管在内的有源结构控制电流的流动。通过改变掺杂的水平、以及对电场或基电流的施加，晶体管促进或限制电流的流动。包括电阻器、电容器、和电感器在内的无源结构建立执行多种电性功能所需的电压和电流之间的关系。无源结构和有源结构被电连接以形成电路，这些电路使得半导体器件能够执行高速计算和其他有用的功能。
通常使用两个复杂的制造过程——即，前端制造和后端制造，两者均可能涉及数百个步骤——来制造半导体器件。前端制造涉及在半导体晶圆的表面上形成多个小片(die)。每个小片一般都是相同的，并且包含通过将有源元件和无源元件电连接而形成的电路。后端制造涉及从已完成的晶圆上剪切(singulate)各个小片、以及封装小片以提供结构支撑和环境隔离。
半导体制造的一个目标是制造较小的半导体器件。较小的器件一般消耗较少的功率，具有较高的性能，并且能够更高效地制造。此外，较小的半导体器件具有较小的占位面积(footprint)，这对于较小的终端产品是理想的。可以通过前端过程的改进从而产生具有较小、较高密集度的有源和无源元件的小片来实现较小的小片尺寸。后端过程可以通过电互连和封装材料的改进而产生具有较小占位面积的半导体器件封装。
在传统的扇出型晶圆级芯片尺寸封装(Fo-WLCSP)中，凸出的半导体小片一般安装于载体并通过密封剂封闭。载体被移除，并且转接(built-up)的互连结构在密封剂和半导体小片之上形成。半导体小片上的凸块一般键合到形成在载体上或互连结构内的凸块焊盘。凸块焊盘增加了互连间距并减小了输入/输出(I/O)计数。
发明内容
存在提供用于Fo-WLCSP中的半导体小片的细间距互连的需要。因此，在一个实施例中，本发明是制造半导体器件的方法，其包括以下步骤：提供载体；在载体之上形成包括多个迹线的导电层；提供具有多个触点焊盘和形成在该触点焊盘之上的第一凸块的半导体小片；将半导体小片以第一凸块直接键合到所述迹线的端部的方式安装到导电层；在半导体小片和导电层之上沉积密封剂；移除载体；以及在密封剂和半导体小片之上形成互连结构。
在另一个实施例中，本发明是制造半导体器件的方法，其包括以下步骤：提供载体；在载体之上形成包括多个迹线的导电层；提供具有多个触点焊盘和形成在该触点焊盘之上的第一凸块的半导体小片；将该半导体小片以第一凸块直接键合到所述迹线的方式安装到导电层；以及在半导体小片和导电层之上沉积密封剂。导电层包括可湿性材料，以减少封装期间半导体小片的移动。所述方法进一步包括去除载体的步骤以及在密封剂和半导体小片上形成互连结构的步骤。
在另一个实施例中，本发明是制造半导体器件的方法，其包括以下步骤：形成包括多个迹线的导电层；提供具有多个触点焊盘和形成在该触点焊盘上的第一凸块的半导体小片；将半导体小片以第一凸块直接键合到所述迹线的方式安装到导电层；以及在半导体小片和导电层上沉积密封剂。
在另一个实施例中，本发明是包括导电层的半导体器件，所述导电层包括多个迹线。半导体小片具有多个触点焊盘和形成在触点焊盘上的第一凸块。半导体小片以第一凸块直接键合到迹线的方式安装到导电层。密封剂沉积在半导体小片和导电层之上。互连结构形成在密封剂和半导体小片之上。
附图说明
图1示出了具有安装于其表面的不同类型的封装的PCB；
图2a-2c示出了安装于PCB的代表性半导体封装的进一步细节；
图3a-3c示出了具有由划片街区(saw street)所分开的多个半导体小片的半导体晶圆；
图4a-4s示出了形成用于在Fo-WLCSP中安装半导体小片的BOL互连的过程；
图5示出了安装于BOL互连的半导体小片；
图6示出了形成在半导体小片的触点焊盘上的导电柱；
图7示出了沉积在BOL互连之上的无流动底部填充材料；以及
图8a-8c示出了安装于具有掩膜层的BOL互连的半导体小片。
具体实施方式
已参照附图将本发明描述在下文的一个或多个实施例中，在附图中，相似的附图标记表示相同或相似的元件。尽管按照用于实现本发明的目的的最佳模式描述了本发明，但本领域普通技术人员将意识到，其意在覆盖可以被包括在如所附权利要求及其等同形式所限定的本发明的精神和范围内的替代、修改和等同形式，权利要求及其等同形式由下面的公开和附图支持。
通常使用两个复杂的制造过程——前端制造和后端制造——来制造半导体器件。前端制造涉及在半导体晶圆的表面上形成多个小片。晶圆上的每个小片均包含有源电子元件和无源电子元件，有源电子元件和无源电子元件被电连接以形成功能性电路。比如晶体管和二极管等有源电子元件具有控制电流的流动的能力。比如电容器、电感器、电阻器和变压器等无源电子元件形成执行电路功能所需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、蚀刻以及平坦化(planarization)的一系列工艺步骤在半导体晶圆的表面上形成无源元件和有源元件。通过诸如离子注入或热扩散的技术，掺杂将杂质引入到半导体材料中。掺杂过程改变了有源器件中半导体材料的导电性，从而将半导体材料转变成绝缘体、导体，或者从而响应于电场或基电流动态地改变半导体材料的导电性。晶体管含有具有各不相同的掺杂类型和程度的区域，所述掺杂类型和程度是按照必需使晶体管能够在施加电场或基电流时促进或限制电流的流动来设置的。
有源元件和无源元件由具有不同电特性的材料的层形成。这些层可以通过多种沉积技术形成，这些沉积技术部分地由被沉积的材料的类型所决定。例如，薄膜沉积可以涉及化学气相沉积(CVD)、物理气相沉积(PVD)、电镀、以及无电敷镀(electroless plating)工艺。每个层通常被图案化，以形成部分有源元件、无源元件、或元件之间的电连接。
这些层可以利用光刻被图案化，光刻涉及光敏材料(如光刻胶)在要被图案化的层上的沉积。使用光将图案从光掩膜转印到光刻胶。利用溶剂去除光刻胶图案的受光部分，从而暴露出下面的要被图案化的层的部分。光刻胶的剩余部分被去除，从而在其后留下图案化的层。可替代地，利用诸如无电敷镀或电镀的技术，通过将材料直接沉积到由先前的沉积/蚀刻工艺形成的区域或空隙中而将一些类型的材料图案化。
在已有的图案上沉积材料的薄膜能够扩大在下面的图案，并形成非均匀平坦的表面。需要非均匀平坦的表面以制造更小且更密集封装的有源元件和无源元件。可使用平坦化将材料从晶圆的表面去除而产生均匀平坦的表面。平坦化涉及利用抛光垫抛光晶圆的表面。研磨材料和腐蚀性的化学制品在抛光期间被添加到晶圆的表面。研磨的机械作用和化学制品的腐蚀作用的结合将消除任何不规则的构形，从而产生均匀平坦的表面。
后端制造指的是将完成的晶圆切割或剪切成各个小片，然后封装小片以便结构支撑和环境隔离。为了剪切小片，晶圆被划线并沿着称作划片街区或划痕(scribe)的晶圆的非功能性区域断开。利用激光切割工具或锯刀剪切晶圆。在剪切之后，各个小片被安装到封装衬底，该封装衬底包括用于与其他系统元件互连的引脚或触点焊盘。形成在半导体小片上的触点焊盘然后被连接至封装内的触点焊盘。可以利用焊料凸块、螺柱凸块(studbump)、导电胶或线键合进行电连接。密封剂或其他成型材料沉积在封装上方，以提供物理支撑和电隔离。完成的封装然后被插入到电系统中并且使半导体器件的功能性对其他系统元件可用。
图1示出了电子器件50，其具有在其上装设有多个半导体封装的芯片载体衬底或印刷电路板(PCB)52。电子器件50可以具有一种类型的半导体封装，或者多种类型的半导体封装，这取决于应用场合。出于示例的目的，在图1中示出了不同类型的半导体封装。
电子器件50可以是独立的系统，其使用半导体封装来执行一种或多种电功能。可替代地，电子器件50可以是较大系统的子部件。例如，电子器件50可以是蜂窝电话、个人数字助理(PDA)、数字视频摄像机(DVC)、或其他电子通信设备的一部分。可替代地，电子器件50可以是能够插入到计算机中的图形卡、网络接口卡、或者其他信号处理卡。半导体封装可以包括微处理器、存储器、特定用途集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件、或者其他半导体小片或电子元件。这些产品要被市场所接受，小型化和重量减轻是必要的。半导体器件之间的距离必须被减小以实现较高的密集度。
在图1中，PCB 52提供了用于在PCB上所安装的半导体封装的结构支撑和电互连的一般衬底。利用蒸发、电镀、无电敷镀、丝网印刷、或者其他适当的金属沉积工艺将导电信号迹线54形成在PCB 52的表面上或层内。信号迹线54提供半导体封装、所安装的元件、以及其他外部系统元件中的每一个之间的电通信。迹线54还对半导体封装中的每一个提供电源和接地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是以机械和电性方式将半导体小片附接于中间载体的技术。第二级封装涉及以机械和电性方式将中间载体附接于PCB。在其他实施例中，半导体器件可以仅具有第一级封装，在这种情况下，小片被以机械和电性方式直接安装于PCB。
出于示例的目的，在PCB 52上示出了若干类型的第一级封装，包括线键合封装56和倒装芯片58。另外，若干类型的第二级封装示出为安装在PCB 52上，包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插式封装(DIP)64、小岛栅格阵列(land grid array，LGA)66、多芯片模块(MCM)68、四侧无引脚扁平封装(QFN)70、以及四侧扁平封装72。根据系统的要求，以第一和第二级封装方式的任何相组合所配置的半导体封装的任何组合，以及其他电子元件都可以连接于PCB 52。在一些实施例中，电子器件50包括单个附接的半导体封装，而其他实施例需要多个相互连接的封装。通过在单个衬底上将一个或多个半导体封装相组合，制造商能够将预制的元件结合到电子设备和系统中。由于半导体封装包括精密复杂的功能，所以电子器件能够利用较低廉的元件和最新的制造工艺来制造。由此产生的器件不太可能出现故障并且制造起来不那么昂贵从而对消费者而言产生较低成本。
图2a-2c示出了示例性的半导体封装。图2a示出了安装在PCB 52上的DIP 64的进一步的细节。半导体小片74包括含有模拟或数字电路的作用区域(active region)，这些模拟或数字电路实现为形成在小片内并且根据小片的电设计被相互电连接的有源器件、无源器件、导电层、以及介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体小片74的作用区域内的其他电路元件。触点焊盘76是一个或多个导电材料层，所述导电材料例如为铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)，触点焊盘76与形成在半导体小片74内的电路元件电连接。在DIP 64的组装期间，利用金-硅共晶层或诸如热环氧或环氧树脂的附着材料将半导体小片74安装到中间载体78。封装体包括诸如聚合物或陶瓷的绝缘封装材料。导线80和线键合82提供半导体小片74与PCB 52之间的电性互连。密封剂84沉积在封装上，以通过防止水分和颗粒进入封装及污染小片74或线键合82来进行环境保护。
图2b示出了安装在PCB 52上的BCC 62的进一步的细节。利用底部填充(underfill)或环氧树脂附着材料92将半导体小片88安装在载体90上方。线键合94提供触点焊盘96和98之间的第一级封装互连。成型化合物或密封剂100沉积在半导体小片88和线键合94上，以提供对器件的物理支撑和电隔离。利用如防止氧化的电镀或无电敷镀等适当的金属沉积工艺在PCB 52的表面上方形成触点焊盘102。触点焊盘102电连接于PCB 52中的一个或多个导电信号迹线54。凸块104形成在BCC 62的触点焊盘98与PCB 52的触点焊盘102之间。
在图2c中，以倒装芯片形式的第一级封装将半导体小片58面向下地安装到中间载体106。半导体小片58的作用区域108含有模拟或数字电路，这些模拟或数字电路实现为根据小片的电设计所形成的有源器件、无源器件、导电层、以及介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及作用区域108内的其他电路元件。半导体小片58通过凸块110以电性和机械方式连接于载体106。
利用凸块112以BGA形式的第二级封装将BGA 60以电性及机械方式连接于PCB 52。半导体小片58通过凸块110、信号线114和凸块112电连接于PCB 52中的导电信号迹线54。成型化合物或密封剂116沉积在半导体小片58和载体106上，以提供对器件的物理支撑和电隔离。倒装芯片半导体器件提供从半导体小片58上的有源器件到PCB 52上的导电轨道的短的导电路径，以减少信号传播距离，降低电容，并改善总的电路性能。在另一实施例中，半导体小片58可以在没有中间载体106的情况下利用倒装芯片形式的第一级封装以机械及电性方式直接连接于PCB 52。
图3a示出了具有用于结构支撑的例如为硅、锗、砷化镓、磷化铟或碳化硅的基衬底材料122的半导体晶圆120。多个半导体小片或元件124形成在晶圆120上，晶圆120如上所述被划片街区分开。
图3b示出了半导体晶圆120的一部分的横截面视图。每个半导体小片124具有背表面128和含有模拟或数字电路的作用表面130，这些模拟或数字电路实现为形成在小片内并且根据小片的电设计和功能相互电连接的有源器件、无源器件、导电层、以及介电层。例如，电路可以包括一个或多个晶体管、二极管、以及在作用表面130内形成的其他电路元件，以实现模拟电路或数字电路，如数字信号处理器(DSP)、ASIC、存储器或其他信号处理电路。半导体小片124还可以包含集成的无源器件(IPD)，如电感器、电容器和电阻器，用于RF信号处理。在一个实施例中，半导体小片124是倒装芯片类型的半导体小片。
利用PVD、CVD、电镀、无电敷镀工艺、或者其他适当的金属沉积工艺将导电层132形成在作用表面130上。导电层132可以是一个或多个Al、Cu、Sn、Ni、Au、Ag、或其他适当的导电材料的层。导电层132用作电连接于作用表面130上的电路的触点焊盘。凸块134形成在触点焊盘132上。可替代地，微凸块或螺柱凸块可以形成在触点焊盘132上。
在图3c中，利用锯刀或激光切割工具136通过划片街区126将半导体晶圆120剪切成各个半导体小片124。
图4a-4c关于图1和2a-2c示出了形成用于在Fo-WLCSP中安装的半导体小片的迹线上键合(bond-on-trace，BOT)或引线上键合(bond-on-lead，BOL)互连的过程。在图4a中，衬底或载体140含有用于结构支撑的例如硅、聚合物、氧化铍、或其他适当的低成本刚性材料的临时或牺牲基材料。界面层或双面胶带142形成在载体140上，作为临时附着键合膜或蚀刻停止层。
在图4b中，利用PVD、CVD、电镀、无电敷镀或其他适当的金属沉积工艺将导电层144形成在界面层142和载体140上。导电层144可以是一个或多个Al、Cu、Sn、Ni、Au、Ag或其他适当的导电材料的层。导电层144含有触点焊盘144a和144h以及信号迹线或引线144b、144c、144d、144e、144f和144g。图4c示出了具有触点焊盘144a和144h以及信号迹线144b-144g的界面层142的一部分的俯视图。触点焊盘144a与信号迹线144b是电连续的，并且触点焊盘144h与信号迹线144g是电连续的。在一个实施例中，触点焊盘144a和144h具有150-250微米(μm)的宽度或直径D，并且信号迹线144b-144g具有60-90μm的宽度W。触点焊盘144a和144h以及信号迹线144b-144g紧密地布置在一起并且偏离细小的间距。在一个实施例中，迹线144b-144g的间距P大约为80-110μm。附加的用于导电层144的触点焊盘和迹线可以形成在横向和竖直方向。迹线144b-144g具有终止在指定用于与半导体小片124的凸块134对齐的位置处的端部或端头146。附加的用于导电层144的触点焊盘和迹线可以形成在横向和竖直方向。
在图4d中，通过拾取和放置操作以作用表面130朝向载体140的方式将来自图3a-3c的半导体小片124安装在界面层142之上。特别地，凸块134与信号迹线144b-144g的端头146对齐。小片安装期间，信号迹线144b-144g的端头146提供对齐标记。半导体小片124的凸块134被以冶金方式(metallurgically)及电性方式连接到信号迹线144b-144g的端头146，作为BOT或BOL互连。图4e示出了被以冶金方式和电性方式连接到信号迹线144b-144g的端头146的半导体小片124的凸块134的俯视图。凸块134的直径大于迹线144b-144g的宽度。迹线144b-144g的间距P可被减小，因为凸块134直接键合于迹线，这区别于传统的专用凸块焊盘。
在另一实施例中，利用PVD、CVD、电镀、无电敷镀工艺或者其他适当的金属沉积工艺将导电层148形成在界面层142和载体140之上，如图4f所示。导电层148可以是一个或多个Al、Cu、Sn、Ni、Au、Ag、或其他适当的导电材料的层。导电层148含有信号迹线或引线148a、148b、148c、148d、148e、和148f，以及触点焊盘148g、148h、148i、148j、148k、和1481。图4g示出了具有信号迹线148a-148f和偏离的触点焊盘148g-1481的界面层142的一部分的俯视图。触点焊盘148g-1481分别与信号迹线148a-148f是电连续的。在一个实施例中，信号迹线148a-148f具有60-90μm的宽度W，并且触点焊盘148g-1481具有150-250μm的宽度或直径D。信号迹线148a-148f和触点焊盘148g-1481紧密地布置在一起并且偏离细小的间距。在一个实施例中，迹线148a-148f的间距P大约为80-110μm。迹线148a-148f具有终止在指定用于与半导体小片124的凸块134对齐的位置处的端部或端头150。附加的用于导电层148的触点焊盘和迹线可以形成在横向和竖直方向。
可选的掩膜层151可以形成在信号迹线148a-148f之上，如图4h所示。多个开口153形成在掩膜层151中迹线148a-148f的端头150之上。
在图4i中，使用拾取和放置操作以作用表面130朝载体140定向的方式将来自图3a-3c的半导体小片124安装在界面层142之上。特别地，凸块134与信号迹线148a-148f的端头150对齐。信号迹线148a-148f的端头150提供小片安装期间的对齐标记。半导体小片124的凸块134以冶金方式及电性方式连接到信号迹线148a-148f的端头150，作为BOT或BOL。
图4j示出了以冶金方式及电性方式连接到信号迹线148a-148f的端头150的半导体小片124的凸块134的俯视图。凸块134的直径大于迹线148a-148f的宽度。迹线148a-148f的间距P可被减小，因为凸块134直接键合到迹线，这与传统的专用凸块焊盘相区别。图4k示出了穿过掩膜层151的开口153以冶金方式和电性方式连接于信号迹线148a-148f的端头150的半导体小片124的凸块134。
图4l示出了以冶金方式和电性方式连接于信号迹线148a-148f的中间部分的凸块134的另一实施例。也就是说，信号迹线148a-148f在两个方向都延伸超出凸块134。图4m示出了穿过掩膜层151的开口153以冶金方式和电性方式连接于信号迹线148a-148f的中间部分的半导体小片124的凸块134。
从图4e或4j继续，利用膏剂印刷(paste printing)、压缩成型、转移成型、液体密封剂成型、真空层压、旋转涂覆、或其他适当的涂敷器将密封剂或成型化合物152沉积在半导体小片124、载体140、和导电层144之上，如图4n所示。密封剂152可以是聚合物复合材料，如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或者具有适当的填充物的聚合物。密封剂152是不导电的，并且在环境上保护半导体器件不受外部元件和污染物影响。导电层144是可湿性材料，如焊剂(flux)材料，以安全可靠地将半导体小片124保持在适当的位置，并减少其在封装期间的移动。
在图4o中，载体140和界面层142被通过化学蚀刻、机械剥离、CMP、机械研磨、热烘焙、UV照射、激光扫描、或湿法剥离去除，从而暴露出半导体小片124、导电层144和密封剂152。
在图4p中，焊料掩膜或绝缘层154形成在半导体小片124、导电层144和密封剂152之上。焊料掩膜层154的一部分被通过蚀刻工艺去除，从而暴露出导电层144以便另外的电互连。
在图4q中，利用蒸发、电镀、无电敷镀、球滴落(ball drop)、或丝网印刷工艺将导电凸块材料沉积在导电层144a和144h的暴露部分上。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，具有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用适当的附接或键合工艺将凸块材料键合到导电层144。在一个实施例中，凸块材料通过在其熔点以上被加热而回流，从而形成球形球体或凸块156。在一些应用中，凸块156再次回流，以改善与导电层144的电接触。凸块下金属化(under bumpmetallization，UBM)可以形成在凸块156下。凸块也可以被压缩键合到导电层144。凸块156代表能够形成在导电层144之上的一类互连结构。互连结构也可使用键合线、螺柱凸块、微凸块、或其他电互连。
在另一个实施例中，转接互连结构158形成在半导体小片124、导电层144、和密封剂152上，如图4r所示。转接互连结构158包括利用诸如溅射、电镀和无电敷镀的图案化和金属沉积工艺形成的导电层或重新分布层(RDL)160。导电层160可以是一个或多个Al、Cu、Sn、Ni、Au、Ag或其他适当的导电材料的层。导电层160的一部分电连接于导电层144。导电层160的其他部分可以是电公共的或电隔离的，这取决于半导体小片124的设计和功能。
利用PVD、CVD、印刷、旋转涂覆、喷洒涂覆、烧结或热氧化在导电层160周围形成绝缘或钝化层162，以进行电隔离。绝缘层162含有一个或多个二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化钽(Ta2O5)、氧化铝(Al2O3)、或具有相似的绝缘和结构特性的其他材料的层。绝缘层162的一部分通过蚀刻工艺被去除，从而暴露出导电层160以便另外的电气互连。
在图4s中，导电凸块材料利用蒸发、电镀、无电敷镀、球滴落、或丝网印刷工艺沉积在转接互连结构158之上并电连接于导电层160、144a、和144g的暴露部分。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，具有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用适当的附接或键合工艺将凸块材料键合到导电层144和160。在一个实施例中，凸块材料通过在其熔点以上被加热而回流，以形成球形球体或凸块164。在一些应用中，凸块164再次回流，以改善与导电层144和160的电接触。UBM可以形成在凸块164下。凸块也可以被压缩键合到导电层144和160。凸块164代表能够形成在导电层144和160之上的一类互连结构。互连结构也可使用键合线、螺柱凸块、微凸块或其他电互连。
从图4g或4s继续，利用锯刀或激光切割工具166通过密封剂152和绝缘层154(或转接互连结构158)将半导体小片124剪切成各个Fo-WLCSP 168。图5示出了在剪切之后来自图4q的Fo-WLCSP 168。半导体小片124通过触点焊盘132和凸块134电连接于导电层144和凸块156。凸块134被键合到导电层144b-144g的端头146，作为BOT或BOL，用于细小的互连间距和增加的I/O数。
图6示出了与图5类似的Fo-WLCSP 170的实施例，其具有形成在触点焊盘132之上的导电柱172而晶圆形式可见图3a-3c。导电柱172含有不可压扁(non-collapsible)或不可熔的材料，如Au、Cu、Ni、高铅焊料、或铅-锡合金。诸如Ni的导电层174形成在导电柱172之上。凸块176形成在导电层174之上。凸块174含有可压扁(collapsible)或可熔的材料，如Sn、无铅合金、Sn-Ag合金、Sn-Ag-Cu合金、Sn-Ag-铟(In)合金、共晶焊料、具有Ag、Cu或Pb的其他锡合金、或者其他相对低温熔化焊料。
具有导电柱172和凸块176的半导体小片124通过施加回流温度和压力而被键合到导电层144b-144g。导电柱172不随压力和回流温度的施加而变形或熔化，并且保持其形式和形状。因此，导电柱172的尺寸可以设定为提供半导体小片124的作用表面130和导电层144之间的隔开距离(stand-off)。
图7示出了与图5类似的Fo-WLCSP 180的实施例，其具有在安装半导体小片124之前形成在导电层144之上的绝缘层182。绝缘层182含有一个或多个SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有相似的绝缘和结构特性的其他材料的层。绝缘层182可以是无流动底部填充材料。
从图4c继续，在另一实施例中，掩膜层184形成在载体140、界面层142、触点焊盘144a和144h、以及迹线144b-144g之上，如图8a中所示的。在凸块高度为15μm的情况下，掩膜层184的厚度为大约85μm。在迹线144b-144g的端头146上方，多个开口186形成在掩膜层184中。图8b示出了掩膜层184的横截面图，该掩膜层184形成在载体140之上且具有暴露出端头146的开口186。与图4h类似，半导体小片124被安装到迹线144b-144g，其中凸块134的回流由掩膜层184限定。与图4k类似，密封剂152沉积在半导体小片124和载体140上。载体140被去除，并且绝缘层154形成在半导体小片124和密封剂152上，与图4o-4p类似。绝缘层154的一部分被去除，并且凸块156被形成在触点焊盘144a和144g上，与图4p-4q类似。
图8c示出了具有掩膜层184的Fo-WLCSP 188。在半导体小片124和掩膜层184之间存在间隙190，用于半导体小片的成型底部填充(MUF)。在一个实施例中，间隙190大约为70-100μm。MUF或密封剂材料192通过间隙190沉积在半导体小片124周围，包括沉积在小片之上和之下。MUF 192可以从贮存器泵送到分配针头。MUF 192在压力下从分配针头穿过间隙190被注射到半导体小片124下及凸块134周围。真空辅助可以抽吸MUF 192，以帮助均匀分布。MUF 192可以是聚合物复合材料，如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或者具有适当的填充物的聚合物。MUF 192是不导电的，并且在环境上保护半导体器件不受外部元件和污染物影响。
尽管已经详细示出了本发明的一个或多个实施例，但本领域普通技术人员将注意到，可以在不偏离如以下权利要求所阐释的本发明的范围的情况下对这些实施例进行修改和改动。

Claims (9)

1.一种制造半导体器件的方法，包括：
提供载体；
形成包括多个迹线的导电层，每个所述迹线与所述载体直接接触并包括其宽度与所述迹线的宽度相等的所述迹线的第一端以及其宽度大于所述迹线的宽度的触点焊盘，所述触点焊盘位于与所述迹线的所述第一端相对的所述迹线的一端；
提供包括多个触点焊盘的半导体小片；
在所述半导体小片的触点焊盘上形成多个导电柱；
以与所述导电柱直接接触的形式形成多个第一凸块；
将所述半导体小片沉积在所述导电层上，其中所述第一凸块直接键合到所述迹线的所述第一端，其中在小片沉积期间所述迹线的所述第一端提供对齐标记，且所述迹线能够形成在横向和竖直方向；
在所述半导体小片和导电层上沉积密封剂；
去除所述载体以暴露所述密封剂和导电层；以及
在去除所述载体后通过如下步骤在所述密封剂和导电层上形成互连结构，
（a）形成与所述密封剂和导电层直接接触的第一绝缘层，
（b）在所述第一绝缘层中形成开口以暴露所述导电层，并且
（c）在所述开口中形成第二凸块以直接接触所述导电层。
2.根据权利要求1所述的方法，还包括利用成型底部填充工艺在所述半导体小片下沉积所述密封剂。
3.根据权利要求1所述的方法，还包括在在所述导电层上沉积所述半导体小片之前，在所述导电层和载体上形成第二绝缘层。
4.根据权利要求3所述的方法，其中，所述第二绝缘层包括无流动底部填充材料。
5.一种制造半导体器件的方法，包括：
提供载体；
形成包括多个迹线的导电层，每个所述迹线与所述载体直接接触并包括其宽度与所述迹线的宽度相等的所述迹线的第一端以及其宽度大于所述迹线的宽度的触点焊盘，所述触点焊盘位于与所述迹线的所述第一端相对的所述迹线的一端；
提供包括形成在所述半导体小片的表面上的多个第一凸块的半导体小片；
将所述半导体小片沉积在所述导电层上，其中所述第一凸块直接键合到所述迹线的端部，其中在小片沉积期间所述迹线的所述第一端提供对齐标记；
在所述半导体小片和导电层上沉积密封剂；
去除所述载体以暴露所述密封剂和导电层；以及
在去除所述载体后通过如下步骤在所述密封剂和导电层上形成互连结构，
（a）形成与所述密封剂和导电层直接接触的第一绝缘层，
（b）在所述第一绝缘层中形成开口以暴露所述导电层，并且
（c）在所述开口中形成第二凸块以直接接触所述导电层。
6.根据权利要求5所述的方法，其中，所述第一凸块比所述迹线宽。
7.根据权利要求5所述的方法，还包括：
在所述导电层上形成掩膜层；以及
在所述迹线上形成所述掩膜层中的多个开口。
8.根据权利要求5所述的方法，还包括在在所述导电层上沉积所述半导体小片之前，在所述导电层和载体上形成第二绝缘层。
9.根据权利要求8所述的方法，其中，所述第二绝缘层包括无流动底部填充材料。
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