CN102386113A - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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Publication number
CN102386113A
CN102386113A CN2011102710213A CN201110271021A CN102386113A CN 102386113 A CN102386113 A CN 102386113A CN 2011102710213 A CN2011102710213 A CN 2011102710213A CN 201110271021 A CN201110271021 A CN 201110271021A CN 102386113 A CN102386113 A CN 102386113A
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semiconductor chip
sealant
framework
carrier
insertion framework
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CN102386113B (zh
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R·A·佩盖拉
邹胜源
尹胜煜
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

一种半导体器件具有安装于载体上的第一半导体小片。插入框架具有在插入框架中的开口和形成于插入框架上的多个导电柱。将插入器安装于载体和第一小片上，其中导电柱安置于该小片周围。可在插入框架中形成腔，以包含所述第一小片的一部分。通过在插入框架中的开口在载体和第一小片上沉积密封剂。可替换地，密封剂沉积于载体和第一小片上并将插入框架压靠在密封剂上。过量的密封剂通过在插入框架中的开口引出。移除载体。在密封剂和第一小片上形成互连结构。可在第一小片上或在插入框架上安装第二半导体小片。

Description

一种半导体器件及其制造方法
技术领域
本发明一般涉及半导体器件且更特定而言涉及在半导体小片(die)上形成插入框架以提供竖直电互连的半导体器件和方法。
背景技术
通常在现代电子产品中发现半导体器件。半导体器件在电部件的数量和密度方面不同。离散的半导体器件通常包含一种类型的电部件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器和功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包含数百至数百万电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池和数字微镜器件(DMD)。
半导体器件执行广泛范围的功能，诸如信号处理、高速计算、发射和接收电磁信号、控制电子器件，将太阳光转变成电和形成视觉投影用于电视显示。在娱乐、通信、电力转换、网络、计算机和消费产品的领域中会发现半导体器件。在军事应用、航空、汽车、工业控制器和办公设备中也发现了半导体器件。
半导体器件利用半导体材料的电性质。半导体材料的原子结构允许通过施加电场或基极电流或通过掺杂工艺来操纵其电导率。掺杂将杂质引入到半导体材料内以操纵并控制半导体器件的电导率。
半导体器件包含有源和无源电结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂的程度和施加电场或基极电流，晶体管促进或限制电流的流动。包括电阻器、电容器和电感器的无源结构形成执行多种电功能所需的电压与电流之间的关系。无源结构和有源结构电连接以形成电路，其使得半导体器件能执行高速计算和其它有用的功能。
通常使用两种复杂的制造工艺制造半导体器件，即，前端制造和后端制造，每种都可能涉及数百个步骤。前端制造涉及在半导体晶片的表面上形成多个小片。每个小片通常是相同的且包含由电连接的有源部件和无源部件形成的电路。后端制造涉及从完成的晶片单个化单独的小片且封装该小片以提供结构支撑和环境隔离。
半导体制造的一个目的是生产更小的半导体器件。更小的器件通常消耗更少的电力、具有更高的性能且可更高效地被生产出来。此外，更小的半导体器件具有更小的印迹(footprint)，其对于较小的终端产品是令人期望的。更小的小片尺寸可通过前端工艺的改进而得以实现，从而得到具有更小、更高密度的有源部件和无源部件的小片。后端工艺可通过改进电互连和封装材料而得到具有更小印迹的半导体器件封装。
在常规展开形式晶片级芯片规模封装(Fo-WLCSP)中，密封剂通常包围半导体小片。顶部和底部装配(build-up)互连结构形成于密封剂的相对表面上。再分布层(RDL)和绝缘层通常形成于顶部和底部装配互连结构内。此外，通常形成穿过密封剂的导电柱(pillar)，用于在顶部互连结构与底部互连机构之间的z方向竖直电互连。导电柱和RDL形成公知使用复杂、昂贵和耗时的工艺，涉及光刻、蚀刻和金属沉积。
发明内容
存在提供用于Fo-WLCSP的z方向竖直电互连且同时减小导电柱和RDL形成以降低制造成本的需要。因此，在一个实施例中，本发明为一种制造半导体器件的方法，包括以下步骤：提供载体；将第一半导体小片安装于载体上；提供插入框架，其具有在插入框架中的开口和形成于插入框架上的多个导电柱；将插入器安装于载体和第一半导体小片上，其中导电柱安置于第一半导体小片周围；通过在插入框架中的开口在载体和第一半导体小片上沉积密封剂；移除载体；以及在密封剂和第一半导体小片上形成互连结构。
在另一实施例中，本发明为一种制造半导体器件的方法，包括以下步骤：提供载体；将第一半导体小片安装于载体上；将密封剂沉积于载体和第一半导体小片上；提供插入框架，其具有在插入框架中的开口和形成于插入框架上的多个导电柱；通过将插入框架压靠在密封剂上而将插入器安装于载体和第一半导体小片上；移除载体；以及在密封剂和第一半导体小片上形成互连结构。
在另一实施例中，本发明为一种制造半导体器件的方法，包括以下步骤：提供第一半导体小片；提供插入框架，其具有在插入框架中的开口和形成于插入框架上的多个导电柱；将插入器安装于第一半导体小片上，其中导电柱安置于第一半导体小片周围；将密封剂沉积于第一半导体小片上；以及在密封剂和第一半导体小片上形成互连结构。
在另一实施例中，本发明为一种半导体器件，包括：第一半导体小片和安装于第一半导体小片上的插入框架。插入框架具有在插入框架中的开口和形成于插入框架上的多个导电柱。在第一半导体小片上沉积密封剂。在密封剂和第一半导体小片上形成互连结构。
附图说明
图1示出具有安装于其表面的不同类型的封装的PCB；
图2a至图2c示出安装到PCB的代表性半导体封装的进一步的细节；
图3a至图3c示出具有由锯迹(saw street)分隔的多个半导体小片的半导体晶片；
图4a至图4f示出导电柱形成于插入框架上的预先形成的插入框架；
图5a至图5h示出形成Fo-WLCSP的过程，Fo-WLCSP具有插入框架和导电柱，其提供半导体小片的竖直互连；
图6示出Fo-WLCSP，其具有插入框架和导电柱，其提供半导体小片的竖直互连；
图7示出多个堆叠Fo-WLCSP，每个Fo-WLCSP具有插入框架和导电柱，其提供半导体小片的竖直互连；
图8a至图8g示出将插入框架安装于密封剂浆(slurry)上；
图9示出插入框架安装于密封剂浆上的Fo-WLCSP；
图10a至图10e示出形成具有腔以部分地包含半导体小片的插入框架；
图11示出半导体小片部分地包含于插入框架的腔内的Fo-WLCSP；
图12示出结合线型半导体小片安装于插入框架上的Fo-WLCSP；以及
图13示出ISM安装于半导体小片上的Fo-WLCSP。
具体实施方式
参考附图在下面的描述中的一个或多个实施例中描述了本发明，其中相同的附图标记表示相同或相似的元件。虽然根据实现本发明目的的最佳方式描述了本发明，但是本领域技术人员应了解本发明预期涵盖在由所附权利要求和下文的公开内容和附图所支持的它们的等效物所限定的本发明的精神和范围内的替代、修改和等效物。
通常使用两种复杂制造工艺制造半导体器件：前端制造和后端制造。前端制造涉及在半导体晶片表面上形成多个小片。晶片上的每个小片包含有源电部件和无源电部件，这些电部件电连接以形成功能电路。诸如晶体管和二极管的有源电部件具有控制电流流动的能力。诸如电容器、电感器、电阻器和变压器的无源电部件形成执行电路功能所必需的电压与电流之间的关系。
无源部件和有源部件通过一系列工艺步骤形成于半导体晶片上，所述工艺步骤包括掺杂、沉积、光刻、蚀刻和平坦化。掺杂通过诸如离子注入或热扩散的技术将杂质引入到半导体材料内。掺杂工艺改变在有源器件中的半导体材料的电导率，将半导体材料转变成绝缘体、导体或响应于电场或基极电流来动态地改变半导体材料的传导率。晶体管包含不同类型和掺杂程度的区域，这些区域根据需要布置以使得晶体管在施加电场或基极电流时促进或限制电流流动。
有源和无源部件由具有不同电性质的材料层形成。可部分地根据正在沉积的材料类型所确定的多种沉积技术来形成层。举例而言，薄膜沉积可涉及化学气相沉积(CVD)、物理气相沉积(PVD)、电解电镀和非电解电镀工艺。每个层通常被图案化以形成有源部件、无源部件或部件之间电连接的部分。
可使用光刻来使这些层图案化，其涉及在待图案化的层上沉积光敏材料，例如光刻胶。使用光将图案从光掩膜转移到光刻胶。使用溶剂来移除经受光的光刻胶图案的部分，暴露待图案化的下层的部分。移除光刻胶的残余物，留下图案化的层。可替换地，使用诸如非电解电镀和电解电镀的技术通过直接将材料沉积到由先前沉积/蚀刻工艺所形成的区域或空隙内来图案化某些类型的材料。
在现有图案上沉积材料薄膜可扩大下面的图案且造成不均匀平坦的表面。要求均匀平坦的表面来产生更小且更密集封装的有源和无源部件。平坦化可用于从晶片表面移除材料且产生均匀平坦的表面。平坦化涉及利用抛光垫来抛光晶片表面。在抛光期间向晶片表面添加研磨材料和腐蚀化学品。研磨作用和化学品腐蚀作用的组合机械作用移除任何不规则的形态，得到均匀平坦的表面。
后端制造指将完成的晶片切割或单个化(singulate)为单独的小片且封装小片用于结构支撑和环境隔离。为了单个化小片，沿着被称作锯迹(saw street)或划痕的晶片的非功能性区域刻划且断开晶片。使用激光切割工具或锯条来单个化晶片。在单个化之后，单独的小片被安装到包括引脚或接触垫以与其它系统部件互连的封装衬底上。在半导体小片上形成的接触垫然后连接到封装内的接触垫。可利用焊料凸块、柱状凸块、导电膏或引线结合来做出电连接。密封剂或其它模制材料沉积于封装上以提供物理支撑和电隔离。然后将完成的封装插入到电系统内且使得半导体器件的功能性可供其它系统部件使用。
图1示出电子器件50，电子器件50具有安装在其表面上的多个半导体封装的芯片载体衬底或印刷电路板(PCB)52。取决于应用，电子器件50可具有一种类型的半导体封装或多种类型的半导体封装。在图1中出于说明的目的示出了不同类型的半导体封装。
电子器件50可为独立系统，其使用半导体封装来执行一个或多个电功能。可替换地，电子器件50可为较大系统的子部件。举例而言，电子器件50可为蜂窝式电话、个人数字助理(PDA)、数字摄像机(DVC)或其它电子通信装置的部件。可替换地，电子器件50可为图形卡、网络接口卡或可插入到计算机内的其它信号处理卡。半导体封装可包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、离散器件或其它半导体小片或电部件。小型化和重量减轻对于这些产品为市场所接受是至关重要的。必须减小半导体器件之间的距离以实现更高的密度。
在图1中，PCB 52提供通用衬底，用于安装于PCB上的半导体封装的结构支撑和电互连。使用蒸镀、电解电镀、非电解电镀、丝网印刷或其它合适的金属沉积工艺将导电信号迹线54形成于PCB52的表面上或PCB 52的层内。信号迹线54提供半导体封装中的每一个、安装的部件和其它外部系统部件之间的电通信。迹线54还提供到半导体封装中的每一个半导体封装的电连接和接地连接。
在某些实施例中，半导体器件具有两个封装级别。第一级封装为将半导体小片机械和电附着到中间载体的技术。第二级封装涉及将中间载体机械和电附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中小片直接地机械且电安装到PCB。
出于说明的目的，在PCB 52上示出若干类型的第一级封装，包括引线结合封装56和倒装芯片58。此外，若干类型的第二级封装，包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插式封装(DIP)64、接点栅阵列(LGA)66、多芯片模块(MCM)68、方形扁平无引线封装(QFN)70和方形扁平封装72被示出安装于PCB 52上。取决于系统要求，被配置成具有第一级封装型和第二级封装型的任何组合的半导体封装的任何组合以及其它电子部件可以连接到PCB52。在某些实施例中，电子器件50包括单个附着的半导体封装，而其它实施例要求多个互连的封装。通过在单个衬底上组合一个或多个半导体封装，制造商可将预制的部件合并到电子器件和系统内。由于半导体封装包括成熟的功能性，可使用更廉价的部件和流水线制造工艺来制造电子器件。所得到的器件不太可能出现故障且制造起来不太昂贵，导致消费者更低的成本。
图2a至图2c示出示范性半导体封装。图2a示出安装到PCB 52上的DIP 64的进一步的细节。半导体小片74包括包含模拟或数字电路的有源区域，所述模拟或数字电路被实施作为形成在小片内且根据小片的电设计而电互连的有源器件、无源器件、导电层和电介质层。举例而言，电路可包括形成于半导体小片74的有源区域内的一个或多个晶体管、二极管、电感器、电容器、电阻器和其它电路元件。接触垫76为一个或多个导电材料层，所述导电材料诸如为铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)，并且电连接到形成在半导体小片74内的电路元件。在DIP 64的组装期间，使用金-硅共晶层或诸如热环氧或环氧树脂的粘合材料将半导体小片74安装到中间载体78。封装主体包括诸如聚合物或陶瓷的绝缘封装材料。导体引线80和引线结合82提供半导体小片74与PCB 52之间的电互连。密封剂84沉积于封装上用于环境保护，防止湿气和粒子进入封装且污染小片74或引线结合82。
图2b示出安装到PCB 52上的BCC 62的进一步的细节。使用底层填料或环氧树脂粘合材料92将半导体小片88安装于载体90上。引线结合94提供在接触垫96与98之间的第一级封装互连。模制化合物或密封剂100沉积于半导体小片88和引线结合94上以便为该器件提供物理支撑和电隔离。使用合适的金属沉积工艺将接触垫102形成于PCB 52的表面上以防止氧化，所述金属沉积工艺诸如为电解电镀或非电解电镀。接触垫102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104形成于BCC 62的接触垫98与PCB 52的接触垫102之间。
在图2c中，以倒装芯片型第一级封装将半导体小片58面朝下安装于中间载体106。半导体小片58的有源区域108包含模拟或数字电路，其被实施作为根据小片的电设计形成的有源器件、无源器件、导电层和电介质层。举例而言，电路可包括形成于有源区域108内的一个或多个晶体管、二极管、电感器、电容器、电阻器和其它电路元件。半导体小片58通过凸块110电连接且机械连接到载体106。
使用凸块112以BGA型第二级封装，将BGA 60电连接且机械连接到PCB 52。半导体小片58通过凸块110、信号线114和凸块112而电连接到PCB 52中的导电信号迹线54。模制化合物或密封剂116沉积于半导体小片58和载体106上以为该器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体小片58上的有源器件到PCB 52上的传导印制线的短的导电路径以便减小信号传播距离、降低电容且改进总的电路性能。在另一实施例中，可使用倒装芯片型第一级封装将半导体小片58直接机械连接且电连接到PCB 52，而不需要中间载体106。
图3a示出半导体晶片120，其具有基体衬底材料122，诸如硅、锗、砷化镓、磷化铟或碳化硅用于结构支撑。多个半导体小片或部件124形成于由如上文所述的锯迹126所分隔的晶片120上。
图3b示出半导体晶片120的一部分的截面图。每个半导体小片124包括背表面128和有源表面130，有源表面130包含模拟或数字电路，所述模拟或数字电路被实施作为形成在小片内且根据小片的电设计和功能而电互连的有源器件、无源器件、导电层和电介质层。举例而言，电路可包括形成于有源表面130内的一个或多个晶体管、二极管和其它电路元件以实施模拟电路或数字电路，诸如数字信号处理器(DSP)、ASIC、存储器或其它信号处理电路。半导体小片124也可包含集成无源器件(IPD)、诸如电感器、电容器和电阻器，用于RF信号处理。在一个实施例中，半导体小片124为倒装芯片型半导体小片。
使用PVD、CVD、电解电镀、非电解电镀工艺或其它合适的金属沉积工艺将导电层132形成于有源表面130上。导电层132可为一个或多个Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料的层。导电层132用作电连接到有源表面130上的电路的接触垫。
在图3c中，使用锯条或激光切割工具134通过锯迹126将半导体晶片120单个化为单独的半导体小片124。
图4a至图4f示出具有导电柱的晶片形式的带状插入器的形成。在图4a中，衬底或载体140包含暂时或牺牲性基体材料，诸如硅、聚合物、氧化铍或其它合适的低成本刚性材料用于结构支撑。中间层或双面胶带142形成于载体140上作为暂时粘合结合膜或蚀刻阻止层。半导体晶片或衬底144包含基体材料，诸如硅、锗、砷化镓、磷化铟或碳化硅，用于结构支撑。作为半导体晶片，衬底144可包含嵌入式半导体小片或无源器件。衬底144也可为多层层压件、陶瓷或引线框架。衬底144安装到在载体140上的中间层142。
在图4b中，使用激光钻孔、机械钻孔或深反应性离子蚀刻(DRIE)穿过衬底144形成多个通孔。使用电解电镀、非电解电镀工艺或其它合适的金属沉积工艺用Al、Cu、Sn、Ni、Au、Ag、钛(Ti)、钨(W)、多晶硅或其它合适的导电材料填充通孔以形成z方向竖直互连的导电通孔146。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层148形成于导电通孔146和衬底144的表面上。绝缘层148包含一个或多个二氧化硅(SiO2)，氮化硅(Si3N4)，氮氧化硅(SiON)，五氧化二钽(Ta2O5)、氧化铝(Al2O3)或具有类似绝缘和结构性质的其它材料的层。通过蚀刻工艺移除绝缘层148的一部分以暴露衬底144和导电通孔146。
使用图案化和金属沉积工艺，诸如印刷、PVD、CVD、溅射、电解电镀和非电解电镀，将导电层或RDL 150形成于暴露的衬底144和导电通孔146上。导电层150可为一个或多个Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料的层。导电层150电连接到导电通孔146。
在图4c中，衬底或载体154包含暂时或牺牲性基体材料，诸如硅、聚合物、氧化铍或其它合适的低成本刚性材料用于结构支撑。中间层或双面胶带156形成于载体154上作为暂时粘合结合膜或蚀刻阻止层。以绝缘层148和导电层150在先，衬底144安装到在载体154上的中间层156。通过化学蚀刻、机械剥落、CMP、机械研磨、热焙烧、紫外光、激光扫描或湿法剥离来移除载体140和中间层142以暴露与导电层150相对的导电通孔146和衬底144的表面。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层158形成于衬底144和导电通孔146上。绝缘层158包含一个或多个SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构性质的其它材料的层。通过蚀刻工艺移除绝缘层158的一部分以暴露衬底144和导电通孔146。
使用图案化和金属沉积工艺，诸如印刷、PVD、CVD、溅射、电解电镀和非电解电镀，将导电层或RDL 150形成于暴露的衬底144和导电通孔146上。导电层160可为一个或多个Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料的层。导电层160电连接到导电通孔146。
在另一实施例中，在形成导电层150和/或160之后，穿过衬底144形成导电通孔146。
在图4d中，光刻胶层162形成于绝缘层158和导电层160上。使用图案化和蚀刻工艺穿过在导电层160上的光刻胶层162形成多个通孔。使用电解电镀、非电解电镀工艺或其它合适的金属沉积工艺利用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅或其它合适的导电材料填充通孔。堆叠的凸块和柱状凸块也可形成于通孔中。
在图4e中，移除光刻胶层162，留下在导电层160上的z方向竖直互连的导电柱164。通过化学蚀刻、机械剥落、CMP、机械研磨、热焙烧、紫外光、激光扫描或湿法剥离来移除载体154和中间层156，留下具有导电柱164的预先形成的插入框架166。导电层150和160和导电通孔146构成穿过插入框架166形成的竖直互连。形成穿过插入框架166的一个或多个开口168。图4f示出带有导电柱164和开口168的插入框架166的顶视图。
图5a至图5h示出相对于图1和图2a至图2c形成Fo-WLCSP的过程，Fo-WLCSP具有插入框架和导电柱提供半导体小片的竖直互连。在图5a中，衬底或载体170包含暂时或牺牲性基体材料，诸如硅、聚合物、氧化铍或其它合适的低成本刚性材料用于结构支撑。中间层或双面胶带171形成于载体170上作为暂时粘合结合膜或蚀刻阻止层。
在图5b中，自图3a至图3c的半导体小片124安装于中间层171上。特别地，半导体小片124安装到中间层171上，且有源表面130朝向载体170定向。
在图5c中，预先形成的插入框架166位于载体170之上。插入框架166安装到中间层171，且导电柱164布置于半导体小片124周围，如图5d所示。对准标记173可制于中间层171上以辅助安装插入框架166。钎焊膏也沉积于载体170上以辅助插入框架166对载体的对准和结合。导电柱164的高度大于半导体小片124的厚度。因此，在半导体小片124的背表面128与插入框架166之间留有间隙。
在图5e中，使用膏印刷、压缩模制、传递模塑、液体密封剂模制、真空层压、旋涂或其它合适的涂覆器通过开口168围绕半导体小片124且在插入框架166与小片之间的间隙中注射或沉积密封剂或模制化合物172。密封剂172可为聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或者具有适当填料的聚合物。密封剂172为非导电的且环境地保护该半导体器件避免外部元件和污染物。半导体小片124可安装到形成于载体170上的可湿润的接触垫以减小密封期间的小片移位。
在图5f中，通过化学蚀刻、机械剥落、CMP、机械研磨、热焙烧、紫外光、激光扫描或湿法剥离来移除载体170和中间层171以暴露密封剂172、半导体小片124和导电柱164。
在图5g中，装配互连结构174形成于半导体小片124、导电柱164和密封剂172上。装配互连结构174包括使用诸如溅射、电解电镀和非电解电镀的图案化和金属沉积工艺形成的导电层或RDL176。导电层176可为一个或多个Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料的层。导电层176的一部分电连接到半导体小片124的接触垫132。导电层176的另一部分电连接到导电柱164。取决于半导体小片124的设计和功能，导电层176的其它部分可电共用或电隔离。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层178形成于导电层176周围用于电隔离。绝缘层178包含一个或多个SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似的绝缘和结构性质的其它材料的层。绝缘层178的一部分可通过蚀刻工艺移除以暴露导电层176用于额外的电互连。
在图5h中，使用蒸镀、电解电镀、非电解电镀、球落(ball drop)或丝网印刷工艺将导电凸块材料沉积于装配互连结构174上且电连接到导电层176的暴露部分。凸块材料可为Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和其组合，具有可选的焊剂溶液。举例而言，凸块材料可为共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或结合工艺将凸块材料结合到导电层176。在一个实施例中，通过加热凸块材料高于其熔点而使得凸块材料回流以形成球形的珠或凸块180。在某些应用中，凸块180第二次回流以改进与导电层176的电接触。可在凸块180下方形成凸块下金属化层(UBM)。凸块也可被压缩结合到导电层176。凸块180表示可形成于导电层176上的一种类型的互连结构。互连结构也可使用柱状凸块、微凸块或其它电互连。
利用锯条或激光切割工具182穿过插入框架166、密封剂172和装配互连结构174将半导体小片124单个化成单独的Fo-WLCSP184。图6示出在单个化之后的Fo-WLCSP 184。半导体小片124通过接触垫132和装配互连结构174电连接到导电柱164和插入框架166。预先形成的插入框架166通过取消在密封剂172的至少一个表面上进行RDL图案化的需要或者形成穿过密封剂的导电柱的需要而简化了组装工艺。
图7示出通过插入框架166、装配互连结构174、凸块180和导电通孔164电连接的多个堆叠的Fo-WLCSP 184。
图8a至图8g示出相对于图1和图2a至图2c形成Fo-WLCSP的过程，Fo-WLCSP具有插入框架和导电柱，提供半导体小片的竖直互连。在图8a中，衬底或载体190包含暂时或牺牲性基体材料，诸如硅、聚合物、氧化铍或其它合适的低成本刚性材料用于结构支撑。中间层或双面胶带192形成于载体190上作为暂时粘合结合膜或蚀刻阻止层。
自图3a至图3c的半导体小片124安装于中间层192上。特别地，半导体小片124安装到中间层192上，且有源表面130朝向载体190定向。
在图8b中，密封剂或模制化合物194沉积于载体190和半导体小片124上作为浆。密封剂浆194可为聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或者具有适当填料的聚合物。
在图8c中，图4a至图4f的预先形成的插入框架166位于载体190上。通过以力F将插入框架按压到密封剂浆194上而将插入框架166安装到中间层192。来自力F的压力造成密封剂浆194平坦且完全填充在插入框架166下方的半导体小片124和导电柱164周围的区域。过量的密封剂浆194通过开口168引出。
当被适当地安放时，导电柱164安置于半导体小片124周围且接触中间层192，如图8d所示。密封剂194包围半导体小片124和导电柱164。导电柱164的高度大于半导体小片124的厚度。因此，半导体小片124的背表面128由密封剂194覆盖。半导体小片124可安装到形成于载体190上的可湿润的接触垫以减小密封期间的小片移位。
在图8e中，通过化学蚀刻、机械剥落、CMP、机械研磨、热焙烧、紫外光、激光扫描或湿法剥离来移除载体190和中间层192以暴露密封剂194、半导体小片124和导电柱164。
在图8f中，装配互连结构196形成于半导体小片124、导电柱164和密封剂194上。装配互连结构196包括使用诸如溅射、电解电镀和非电解电镀的图案化和金属沉积工艺形成的导电层或RDL198。导电层198可为一个或多个Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料的层。导电层198的一部分电连接到半导体小片124的接触垫132。导电层198的另一部分电连接到导电柱164。取决于半导体小片124的设计和功能，导电层198的其它部分可电共用或电隔离。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层200形成于导电层198周围用于电隔离。绝缘层200包含一个或多个SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构性质的其它材料的层。绝缘层200的一部分可通过蚀刻工艺移除以暴露导电层198用于额外的电互连。
在图8g中，使用蒸镀、电解电镀、非电解电镀、球落或丝网印刷工艺将导电凸块材料沉积于装配互连结构196上且电连接到导电层198的暴露部分。凸块材料可为Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和其组合，具有可选的焊剂溶液。举例而言，凸块材料可为共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或结合工艺将凸块材料结合到导电层198。在一个实施例中，通过加热凸块材料高于其熔点而使得凸块材料回流以形成球形的珠或凸块202。在某些应用中，凸块202被第二次回流以改进与导电层198的电接触。可在凸块202下方形成UBM。凸块也可被压缩结合到导电层198。凸块202表示可形成于导电层198上的一种类型的互连结构。互连结构也可使用柱状凸块、微凸块或其它电互连。
利用锯条或激光切割工具204穿过插入框架166、密封剂194和装配互连结构196将半导体小片124单个化成单独的Fo-WLCSP206。图9示出在单个化之后的Fo-WLCSP 206。半导体小片124通过接触垫132和装配互连结构196电连接到导电柱164和插入框架166。预先形成的插入框架166通过取消在密封剂194的至少一个表面上RDL进行图案化的需要或者形成穿过密封剂的导电柱的需要而简化了组装工艺。在安装插入框架166之前沉积密封剂浆194且然后将插入框架按压于密封剂浆上提供密封剂围绕半导体小片124和导电柱164的均匀的覆盖。
图10a至图10e示出相对于图1和图2a至图2c形成Fo-WLCSP的过程，Fo-WLCSP具有插入框架和导电柱，提供半导体小片的竖直互连。从图8b继续，预先形成的插入框架210位于载体190上，如图10a所示。在此情况下，插入框架210具有形成在衬底214中在被指明用于与半导体小片124对准的区域中的腔或凹口212。形成穿过衬底214和绝缘层217的导电通孔和层215，类似于图4a至图4f。形成穿过插入框架210的一个或多个开口216。通过以力F将插入框架按压到密封剂浆194上而将插入框架210安装到中间层192。来自力F的压力使得密封剂浆194平坦且完全填充在插入框架210下方且在半导体小片124和导电柱218周围的区域。过量的密封剂浆194通过开口216引出。
当适当安放时，半导体小片124部分地安置于腔212内。导电柱218安置于半导体小片124周围且接触中间层192，如图10b所示。密封剂194包围半导体小片124和导电柱164。半导体小片124可安装到形成于载体190上的可湿润的接触垫以减小密封期间的小片移位。
在图10c中，通过化学蚀刻、机械剥落、CMP、机械研磨、热焙烧、紫外光、激光扫描或湿法剥离来移除载体190和中间层192以暴露密封剂194、半导体小片124和导电柱218。
在图10d中，装配互连结构222形成于半导体小片124、导电柱218和密封剂194上。装配互连结构222包括使用诸如溅射、电解电镀和非电解电镀的图案化和金属沉积工艺形成的导电层或RDL224。导电层224可为一个或多个Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料的层。导电层224的一部分电连接到半导体小片124的接触垫132。导电层224的另一部分电连接到导电柱218。取决于半导体小片124的设计和功能，导电层224的其它部分可电共用或电隔离。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层226形成于导电层226周围用于电隔离。绝缘层226包含一个或多个SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构性质的其它材料的层。绝缘层226的一部分可通过蚀刻工艺移除以暴露导电层224用于额外的电互连。
在图10e中，使用蒸镀、电解电镀、非电解电镀、球落或丝网印刷工艺将导电凸块材料沉积于装配互连结构222上且电连接到导电层224的暴露部分。凸块材料可为Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和其组合，具有可选的焊剂溶液。举例而言，凸块材料可为共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或结合工艺将凸块材料结合到导电层224。在一个实施例中，通过加热凸块材料至高于其熔点而使得凸块材料回流以形成球形的珠或凸块228。在某些应用中，凸块228被第二次回流以改进与导电层224的电接触。可在凸块228下方形成UBM。凸块也可被压缩结合到导电层224。凸块228表示可形成于导电层224上的一种类型的互连结构。互连结构也可使用柱状凸块、微凸块或其它电互连。
利用锯条或激光切割工具230穿过插入框架210、密封剂194和装配互连结构196将半导体小片124单个化成单独的Fo-WLCSP232。图11示出在单个化之后的Fo-WLCSP 232。半导体小片124通过接触垫132和装配互连结构222电连接到导电柱218和插入框架210。预先形成的插入框架210通过取消在密封剂194的至少一个表面上进行RDL图案化的需要或者形成穿过密封剂的导电柱的需要而简化了组装工艺。在安装插入框架210之前沉积密封剂浆194且然后将插入框架按压于密封剂浆上提供了密封剂围绕半导体小片124的均匀的覆盖。腔212减小了Fo-WLCSP 232的高度。
图12示出类似于图6的Fo-WLCSP 240的实施例，其中利用小片附着粘合剂244将半导体小片242安装到插入框架166。半导体小片242具有有源表面248，有源表面248包含模拟或数字电路，所述模拟或数字电路被实施为形成在小片内且根据小片的电设计和功能而电互连的有源器件、无源器件、导电层和电介质层。举例而言，电路可包括形成于有源表面248内的一个或多个晶体管、二极管和其它电路元件以实施模拟电路或数字电路，诸如DSP、ASIC、存储器或其它信号处理电路。半导体小片242也可包含IPD、诸如电感器、电容器和电阻器，用于RF信号处理。在一个实施例中，半导体小片242为引线结合小片。结合线250电连接于在有源表面248上的接触垫252与插入框架166的导电层150之间。
使用膏印刷、压缩模制、传递模塑、液体密封剂模制、真空层压、旋涂或其它合适的涂覆器将密封剂或模制化合物254沉积于半导体小片242和插入框架166上。密封剂254可为聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或者具有适当填料的聚合物。密封剂254为非导电的且从环境方面保护该半导体器件避免外部元件和污染物。
图13示出类似于图6的Fo-WLCSP 260的实施例，其中在安装图5c中的插入框架166之前利用小片附着粘合剂263将内部堆叠模块(ISM)262安装到半导体小片124。内部堆叠模块262包括具用有源表面268的半导体小片264，有源表面268包含模拟或数字电路，所述模拟或数字电路被实施为形成在小片内且根据小片的电设计和功能而电互连的有源器件、无源器件、导电层和电介质层。举例而言，电路可包括形成于有源表面268内的一个或多个晶体管、二极管和其它电路元件以实施模拟电路或数字电路，诸如DSP、ASIC、存储器或其它信号处理电路。半导体小片264也可包含IPD、诸如电感器、电容器和电阻器，用于RF信号处理。利用小片附着粘合剂269将半导体小片264安装到插入框架166上。结合线270电连接于在有源表面268上的接触垫272与插入框架166的导电层160之间。
使用膏印刷、压缩模制、传递模塑、液体密封剂模制、真空层压、旋涂或其它合适的涂覆器将密封剂或模制化合物274沉积于半导体小片264和插入框架166上。密封剂274可为聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或者具有适当填料的聚合物。密封剂274为非导电的且从环境方面保护该半导体器件避免外部元件和污染物。
虽然已经详细地描述了本发明的一个或多个实施例，本领域技术人员应了解在不偏离如下面的权利要求所陈述的本发明的范围的情况下可对这些实施例做出修改和改动。

Claims (25)

1.一种制造半导体器件的方法，包括：
提供载体；
将第一半导体小片安装于所述载体上；
提供插入框架，其具有在插入框架中的开口和形成在所述插入框架上的多个导电柱；
将所述插入器安装于所述载体和第一半导体小片上，其中所述导电柱安置于所述第一半导体小片周围；
通过所述插入框架中的开口在所述载体和第一半导体小片上沉积密封剂；
移除所述载体；以及
在所述密封剂和所述第一半导体小片上形成互连结构。
2.根据权利要求1所述的方法，还包括在所述插入框架中形成腔以包含所述第一半导体小片的一部分。
3.根据权利要求1所述的方法，还包括在所述载体上形成对准标记以辅助安装所述插入框架。
4.根据权利要求1所述的方法，还包括在沉积所述密封剂之前，将第二半导体小片安装到所述第一半导体小片上。
5.根据权利要求1所述的方法，还包括将第二半导体小片安装到所述插入框架上。
6.根据权利要求5所述的方法，还包括在所述第二半导体小片与插入框架之间形成结合线。
7.一种制造半导体器件的方法，包括：
提供载体；
将第一半导体小片安装于所述载体上；
将密封剂沉积于所述载体和第一半导体小片上；
提供插入框架，其具有在所述插入框架中的开口和形成于所述插 入框架上的多个导电柱；
通过将所述插入框架压靠在所述密封剂上而将所述插入器安装于所述载体和第一半导体小片上；
移除所述载体；以及
在所述密封剂和所述第一半导体小片上形成互连结构。
8.根据权利要求7所述的方法，其中过量的密封剂通过在所述插入框架中的开口引出。
9.根据权利要求7所述的方法，其中所述导电柱安置于所述第一半导体小片周围。
10.根据权利要求7所述的方法，还包括在所述插入框架中形成腔以包含所述第一半导体小片的一部分。
11.根据权利要求7所述的方法，还包括在沉积所述密封剂之前，将第二半导体小片安装到所述第一半导体小片上。
12.根据权利要求7所述的方法，还包括将第二半导体小片安装到所述插入框架上。
13.根据权利要求12所述的方法，还包括在所述第二半导体小片与插入框架之间形成结合线。
14.一种制造半导体器件的方法，包括：
提供第一半导体小片；
提供插入框架，其具有在所述插入框架中的开口和形成于所述插入框架上的多个导电柱；
将所述插入器安装到所述第一半导体小片上，其中所述导电柱安置于所述第一半导体小片周围；
将密封剂沉积于所述第一半导体小片上；以及
在所述密封剂和所述第一半导体小片上形成互连结构。
15.根据权利要求14所述的方法，还包括：
在安装所述插入框架之前将所述密封剂沉积于所述第一半导体小片上；以及 
将所述插入框架压靠在所述密封剂上。
16.根据权利要求15所述的方法，其中过量的密封剂通过在所述插入框架中的开口引出。
17.根据权利要求14所述的方法，还包括通过所述插入框架中的开口在所述第一半导体小片上沉积密封剂。
18.根据权利要求14所述的方法，还包括在所述插入框架中形成腔以包含所述第一半导体小片的一部分。
19.根据权利要求14所述的方法，还包括在沉积所述密封剂之前，将第二半导体小片安装到所述第一半导体小片上。
20.根据权利要求14所述的方法，还包括将第二半导体小片安装到所述插入框架上。
21.一种半导体器件，包括：
第一半导体小片；
安装于所述第一半导体小片上的插入框架，所述插入框架具有在所述插入框架中的开口和形成于所述插入框架上的多个导电柱；
沉积于所述第一半导体小片上的密封剂；以及
形成于所述密封剂和所述第一半导体小片上的互连结构。
22.根据权利要求21所述的半导体器件，还包括形成在所述插入框架中的腔以包含所述第一半导体小片的一部分。
23.根据权利要求21所述的半导体器件，其中通过在所述插入框架中的开口在所述第一半导体小片上沉积所述密封剂。
24.根据权利要求21所述的半导体器件，还包括安装于所述第一半导体器件上的第二半导体小片。
25.根据权利要求21所述的半导体器件，还包括安装到所述插入框架上的第二半导体小片。 
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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681528A (zh) * 2012-09-10 2014-03-26 矽品精密工业股份有限公司 半导体封装件及其制法与中介板结构
CN103681607A (zh) * 2012-09-17 2014-03-26 新科金朋有限公司 半导体器件及其制作方法
CN103681468A (zh) * 2012-09-14 2014-03-26 新科金朋有限公司 在Fo-WLCSP中形成双面互连结构的半导体器件和方法
CN104253058A (zh) * 2013-06-28 2014-12-31 新科金朋有限公司 在扇出型wlcsp上堆叠半导体小片的方法及半导体装置
CN104733379A (zh) * 2013-12-23 2015-06-24 新科金朋有限公司 在半导体管芯上形成细节距的rdl的半导体器件和方法
CN104969347A (zh) * 2013-01-29 2015-10-07 苹果公司 超薄PoP封装件
CN105405835A (zh) * 2014-09-10 2016-03-16 恒劲科技股份有限公司 中介基板及其制法
CN105702648A (zh) * 2014-12-11 2016-06-22 联发科技股份有限公司 芯片封装结构及其制造方法
CN106449588A (zh) * 2015-08-05 2017-02-22 联发科技股份有限公司 半导体封装、半导体设备及半导体封装的制造方法
CN106558574A (zh) * 2016-11-18 2017-04-05 华为技术有限公司 芯片封装结构和方法
CN107210288A (zh) * 2015-02-13 2017-09-26 高通股份有限公司 并排半导体封装
CN107301978A (zh) * 2016-04-14 2017-10-27 美光科技公司 具有多个共面中介元件的半导体封装
CN107658273A (zh) * 2016-07-26 2018-02-02 艾马克科技公司 半导体装置及制造方法
CN109641738A (zh) * 2016-06-14 2019-04-16 麦斯卓微有限公司 电连接弯曲部件
CN110571158A (zh) * 2016-05-11 2019-12-13 日月光半导体制造股份有限公司 半导体装置封装及其制造方法
CN110970312A (zh) * 2018-09-28 2020-04-07 台湾积体电路制造股份有限公司 封装件及其形成方法
US11164754B2 (en) 2018-09-28 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming the same

Families Citing this family (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8021907B2 (en) 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
USRE48111E1 (en) 2009-08-21 2020-07-21 JCET Semiconductor (Shaoxing) Co. Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US8383457B2 (en) 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US8618654B2 (en) * 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
KR101163222B1 (ko) * 2010-09-13 2012-07-06 에스케이하이닉스 주식회사 반도체 패키지 및 그 제조방법
US8766460B2 (en) * 2012-02-02 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package with interposer frame and method of making the same
TWI637467B (zh) * 2012-05-24 2018-10-01 欣興電子股份有限公司 中介基材及其製作方法
US9282646B2 (en) * 2012-05-24 2016-03-08 Unimicron Technology Corp. Interposed substrate and manufacturing method thereof
US9385006B2 (en) 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package
US9443797B2 (en) 2012-09-14 2016-09-13 STATS ChipPAC Pte. Ltd. Semiconductor device having wire studs as vertical interconnect in FO-WLP
US9818734B2 (en) 2012-09-14 2017-11-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming build-up interconnect structures over a temporary substrate
TWI534965B (zh) * 2012-09-17 2016-05-21 矽品精密工業股份有限公司 半導體封裝件及其製法
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR101366461B1 (ko) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US8970023B2 (en) 2013-02-04 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming same
CN104217967A (zh) * 2013-05-31 2014-12-17 宏启胜精密电子(秦皇岛)有限公司 半导体器件及其制作方法
KR102099878B1 (ko) 2013-07-11 2020-04-10 삼성전자 주식회사 반도체 패키지
US9076724B1 (en) 2013-09-26 2015-07-07 Stats Chippac Ltd. Integrated circuit system with debonding adhesive and method of manufacture thereof
US9184067B1 (en) * 2013-09-27 2015-11-10 Stats Chippac Ltd. Methods of mitigating defects for semiconductor packages
US9653442B2 (en) * 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
US9711485B1 (en) * 2014-02-04 2017-07-18 Amkor Technology, Inc. Thin bonded interposer package
KR20150091932A (ko) 2014-02-04 2015-08-12 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9362161B2 (en) 2014-03-20 2016-06-07 Stats Chippac, Ltd. Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
US9318452B2 (en) * 2014-03-21 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9418974B2 (en) 2014-04-29 2016-08-16 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods
US9412714B2 (en) * 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
JP6317629B2 (ja) * 2014-06-02 2018-04-25 株式会社東芝 半導体装置
US9252127B1 (en) * 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
US9543170B2 (en) 2014-08-22 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
KR102274742B1 (ko) * 2014-10-06 2021-07-07 삼성전자주식회사 패키지 온 패키지와 이를 포함하는 컴퓨팅 장치
US9589936B2 (en) * 2014-11-20 2017-03-07 Apple Inc. 3D integration of fanout wafer level packages
US9947625B2 (en) 2014-12-15 2018-04-17 Bridge Semiconductor Corporation Wiring board with embedded component and integrated stiffener and method of making the same
US10269722B2 (en) 2014-12-15 2019-04-23 Bridge Semiconductor Corp. Wiring board having component integrated with leadframe and method of making the same
US9443799B2 (en) 2014-12-16 2016-09-13 International Business Machines Corporation Interposer with lattice construction and embedded conductive metal structures
WO2016149441A1 (en) * 2015-03-18 2016-09-22 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
KR101731700B1 (ko) 2015-03-18 2017-04-28 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9893017B2 (en) 2015-04-09 2018-02-13 STATS ChipPAC Pte. Ltd. Double-sided semiconductor package and dual-mold method of making same
US10177090B2 (en) 2015-07-28 2019-01-08 Bridge Semiconductor Corporation Package-on-package semiconductor assembly having bottom device confined by dielectric recess
US9913385B2 (en) 2015-07-28 2018-03-06 Bridge Semiconductor Corporation Methods of making stackable wiring board having electronic component in dielectric recess
US10269767B2 (en) 2015-07-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same
US20170098629A1 (en) * 2015-10-05 2017-04-06 Mediatek Inc. Stacked fan-out package structure
US9799636B2 (en) 2015-11-12 2017-10-24 Nxp Usa, Inc. Packaged devices with multiple planes of embedded electronic devices
US10818621B2 (en) * 2016-03-25 2020-10-27 Samsung Electronics Co., Ltd. Fan-out semiconductor package
TWI563602B (en) * 2016-04-15 2016-12-21 Phoenix Pioneer Technology Co Ltd Method of fabricating a package substrate
US9659911B1 (en) * 2016-04-20 2017-05-23 Powertech Technology Inc. Package structure and manufacturing method thereof
US11272618B2 (en) 2016-04-26 2022-03-08 Analog Devices International Unlimited Company Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US20170365567A1 (en) * 2016-06-20 2017-12-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US9761570B1 (en) 2016-06-28 2017-09-12 Nxp Usa, Inc. Electronic component package with multple electronic components
US10269720B2 (en) 2016-11-23 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out packaging
KR102511832B1 (ko) * 2016-08-26 2023-03-20 삼성전자주식회사 반도체 패키지 장치
KR101815785B1 (ko) 2016-08-31 2018-01-05 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR101815784B1 (ko) 2016-08-31 2018-01-05 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
KR101942727B1 (ko) * 2016-09-12 2019-01-28 삼성전기 주식회사 팬-아웃 반도체 패키지
TWI624924B (zh) * 2016-10-14 2018-05-21 鈺橋半導體股份有限公司 具有嵌埋式元件及加強層之線路板及其製法
US10163813B2 (en) * 2016-11-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure including redistribution structure and conductive shielding film
KR101872644B1 (ko) * 2017-06-05 2018-06-28 삼성전기주식회사 팬-아웃 반도체 장치
KR102351676B1 (ko) * 2017-06-07 2022-01-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
TWI630665B (zh) * 2017-06-20 2018-07-21 恆勁科技股份有限公司 製作晶片封裝結構之方法
KR102327548B1 (ko) * 2017-10-17 2021-11-16 삼성전자주식회사 반도체 패키지
EP3478033A1 (en) 2017-10-25 2019-05-01 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Embedding component with pre-connected pillar in component carrier
KR101963292B1 (ko) 2017-10-31 2019-03-28 삼성전기주식회사 팬-아웃 반도체 패키지
US10636715B2 (en) * 2017-11-06 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of fabricating the same
WO2019111873A1 (ja) 2017-12-05 2019-06-13 株式会社村田製作所 モジュール
US10410999B2 (en) 2017-12-19 2019-09-10 Amkor Technology, Inc. Semiconductor device with integrated heat distribution and manufacturing method thereof
CN110277364A (zh) * 2018-03-13 2019-09-24 钰桥半导体股份有限公司 整合元件及导线架的线路板及其制法
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US11251170B2 (en) * 2019-04-29 2022-02-15 Powertech Technology Inc. Package structure and manufacturing method thereof
IT201900006736A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
IT201900006740A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
EP3909078A4 (en) 2019-06-27 2022-12-21 Yangtze Memory Technologies Co., Ltd. MARKING PATTERN IN THREE-DIMENSIONAL MEMORY DEVICE STAIR STRUCTURE FORMING
US11239135B2 (en) * 2019-07-18 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
DE102019121012A1 (de) * 2019-08-02 2021-02-04 Infineon Technologies Ag Verkapseltes Package mit Träger, Laminatkörper und dazwischenliegender Komponente
US11322453B2 (en) * 2019-11-26 2022-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having channels formed between through-insulator-vias
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US11798859B2 (en) * 2021-05-11 2023-10-24 Advanced Semiconductor Engineering, Inc. Electronic device package and method of manufacturing the same
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
EP4152388A1 (en) * 2021-09-21 2023-03-22 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Electronic package with components mounted at two sides of a layer stack
TWI825547B (zh) * 2021-10-08 2023-12-11 南亞科技股份有限公司 具有再填充層的半導體元件及其製備方法
US11646292B2 (en) * 2021-10-08 2023-05-09 Nanya Technology Corporation Method for fabricating semiconductor device with re-fill layer

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1543291A (zh) * 2003-02-18 2004-11-03 ���µ�����ҵ��ʽ���� 电子部件内置模块及其制造方法
CN1779971A (zh) * 2004-10-22 2006-05-31 松下电器产业株式会社 半导体装置及其制造方法
CN1983533A (zh) * 2005-11-30 2007-06-20 飞思卡尔半导体公司 用于封装半导体器件的方法
US20080315375A1 (en) * 2007-06-25 2008-12-25 Epic Technologies, Inc. Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
US20100133665A1 (en) * 2008-11-29 2010-06-03 Jong-Woo Ha Integrated circuit packaging system with lead frame and method of manufacture thereof

Family Cites Families (132)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5543657A (en) 1994-10-07 1996-08-06 International Business Machines Corporation Single layer leadframe design with groundplane capability
US5742100A (en) 1995-03-27 1998-04-21 Motorola, Inc. Structure having flip-chip connected substrates
US5612513A (en) * 1995-09-19 1997-03-18 Micron Communications, Inc. Article and method of manufacturing an enclosed electrical circuit using an encapsulant
KR0179803B1 (ko) 1995-12-29 1999-03-20 문정환 리드노출형 반도체 패키지
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US6297547B1 (en) 1998-02-13 2001-10-02 Micron Technology Inc. Mounting multiple semiconductor dies in a package
JP3939429B2 (ja) 1998-04-02 2007-07-04 沖電気工業株式会社 半導体装置
US6020629A (en) 1998-06-05 2000-02-01 Micron Technology, Inc. Stacked semiconductor package and method of fabrication
KR100426494B1 (ko) 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
JP3772066B2 (ja) 2000-03-09 2006-05-10 沖電気工業株式会社 半導体装置
US6333104B1 (en) 2000-05-30 2001-12-25 International Business Machines Corporation Conductive polymer interconnection configurations
US6417462B1 (en) 2000-06-19 2002-07-09 Intel Corporation Low cost and high speed 3-load printed wiring board bus topology
US6537482B1 (en) 2000-08-08 2003-03-25 Micron Technology, Inc. Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography
US6607937B1 (en) 2000-08-23 2003-08-19 Micron Technology, Inc. Stacked microelectronic dies and methods for stacking microelectronic dies
US6380624B1 (en) 2000-10-10 2002-04-30 Walsin Advanced Electronics Ltd. Stacked integrated circuit structure
US6440753B1 (en) 2001-01-24 2002-08-27 Infineon Technologies North America Corp. Metal hard mask for ILD RIE processing of semiconductor memory devices to prevent oxidation of conductive lines
US7902679B2 (en) 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US6472741B1 (en) 2001-07-14 2002-10-29 Siliconware Precision Industries Co., Ltd. Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same
US6765287B1 (en) 2001-07-27 2004-07-20 Charles W. C. Lin Three-dimensional stacked semiconductor package
JP4023159B2 (ja) 2001-07-31 2007-12-19 ソニー株式会社 半導体装置の製造方法及び積層半導体装置の製造方法
JP4126891B2 (ja) 2001-08-03 2008-07-30 セイコーエプソン株式会社 半導体装置の製造方法
JP3649169B2 (ja) 2001-08-08 2005-05-18 松下電器産業株式会社 半導体装置
US7176506B2 (en) 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
JP2003101222A (ja) 2001-09-21 2003-04-04 Sony Corp 薄膜回路基板装置及びその製造方法
TW523887B (en) 2001-11-15 2003-03-11 Siliconware Precision Industries Co Ltd Semiconductor packaged device and its manufacturing method
KR20030045950A (ko) 2001-12-03 2003-06-12 삼성전자주식회사 방열판을 구비한 멀티 칩 패키지
US7032392B2 (en) 2001-12-19 2006-04-25 Intel Corporation Method and apparatus for cooling an integrated circuit package using a cooling fluid
US20030178719A1 (en) 2002-03-22 2003-09-25 Combs Edward G. Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package
TW544784B (en) 2002-05-27 2003-08-01 Via Tech Inc High density integrated circuit packages and method for the same
US6822326B2 (en) * 2002-09-25 2004-11-23 Ziptronix Wafer bonding hermetic encapsulation
JP2004128219A (ja) 2002-10-02 2004-04-22 Shinko Electric Ind Co Ltd 付加機能を有する半導体装置及びその製造方法
JP2004140037A (ja) * 2002-10-15 2004-05-13 Oki Electric Ind Co Ltd 半導体装置、及びその製造方法
TW567601B (en) 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
US20040089943A1 (en) 2002-11-07 2004-05-13 Masato Kirigaya Electronic control device and method for manufacturing the same
JP4145301B2 (ja) 2003-01-15 2008-09-03 富士通株式会社 半導体装置及び三次元実装半導体装置
TW594962B (en) * 2003-01-30 2004-06-21 Yu-Nung Shen Semiconductor chip package structure and method
US6815254B2 (en) 2003-03-10 2004-11-09 Freescale Semiconductor, Inc. Semiconductor package with multiple sides having package contacts
US7144538B2 (en) 2003-06-26 2006-12-05 Semiconductor Components Industries, Llc Method for making a direct chip attach device and structure
KR20050001159A (ko) 2003-06-27 2005-01-06 삼성전자주식회사 복수개의 플립 칩들을 갖는 멀티칩 패키지 및 그 제조방법
US7074647B2 (en) 2003-07-07 2006-07-11 Freescale Semiconductor, Inc. Semiconductor component comprising leadframe, semiconductor chip and integrated passive component in vertical relationship to each other
DE10334575B4 (de) 2003-07-28 2007-10-04 Infineon Technologies Ag Elektronisches Bauteil und Nutzen sowie Verfahren zur Herstellung derselben
US7180165B2 (en) 2003-09-05 2007-02-20 Sanmina, Sci Corporation Stackable electronic assembly
US7919864B2 (en) 2003-10-13 2011-04-05 Stmicroelectronics S.A. Forming of the last metallization level of an integrated circuit
EP1681717B1 (en) 2003-11-07 2017-03-29 Shinko Electric Industries Co., Ltd. Electronic device
US6930378B1 (en) 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support
DE10360708B4 (de) 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
TWI224849B (en) 2004-01-02 2004-12-01 Advanced Semiconductor Eng Quad flat flip chip package and lead frame
TWI249228B (en) 2004-03-29 2006-02-11 Siliconware Precision Industries Co Ltd Semiconductor package structure for improving electrical performance and method for fabricating the same
EP1775768A1 (en) 2004-06-04 2007-04-18 ZyCube Co., Ltd. Semiconductor device having three-dimensional stack structure and method for manufacturing the same
US7186588B1 (en) 2004-06-18 2007-03-06 National Semiconductor Corporation Method of fabricating a micro-array integrated circuit package
KR100630690B1 (ko) 2004-07-08 2006-10-02 삼성전자주식회사 열 소산 경로를 구비한 멀티 칩 패키지
JP4752369B2 (ja) 2004-08-24 2011-08-17 ソニー株式会社 半導体装置および基板
KR100574223B1 (ko) 2004-10-04 2006-04-27 삼성전자주식회사 멀티칩 패키지 및 그 제조방법
TWI250592B (en) 2004-11-16 2006-03-01 Siliconware Precision Industries Co Ltd Multi-chip semiconductor package and fabrication method thereof
US7745918B1 (en) * 2004-11-24 2010-06-29 Amkor Technology, Inc. Package in package (PiP)
JP2006165252A (ja) * 2004-12-07 2006-06-22 Shinko Electric Ind Co Ltd チップ内蔵基板の製造方法
US7169245B2 (en) 2004-12-13 2007-01-30 3M Innovative Properties Company Methods of using sonication to couple a heat sink to a heat-generating component
JP2006190767A (ja) 2005-01-05 2006-07-20 Shinko Electric Ind Co Ltd 半導体装置
US7528474B2 (en) * 2005-05-31 2009-05-05 Stats Chippac Ltd. Stacked semiconductor package assembly having hollowed substrate
US20060270106A1 (en) * 2005-05-31 2006-11-30 Tz-Cheng Chiu System and method for polymer encapsulated solder lid attach
US7361531B2 (en) 2005-11-01 2008-04-22 Allegro Microsystems, Inc. Methods and apparatus for Flip-Chip-On-Lead semiconductor package
WO2007056253A2 (en) 2005-11-03 2007-05-18 International Rectifier Corporation A semiconductor package that includes stacked semiconductor die
TWI292617B (en) 2006-02-03 2008-01-11 Siliconware Precision Industries Co Ltd Stacked semiconductor structure and fabrication method thereof
US7790504B2 (en) 2006-03-10 2010-09-07 Stats Chippac Ltd. Integrated circuit package system
DE102006012738A1 (de) * 2006-03-17 2007-09-20 Infineon Technologies Ag Nutzen aus einer Verbundplatte mit Halbleiterchips und Kunststoffgehäusemasse sowie Verfahren und Moldform zur Herstellung desselben
US7993972B2 (en) 2008-03-04 2011-08-09 Stats Chippac, Ltd. Wafer level die integration and method therefor
US7569918B2 (en) 2006-05-01 2009-08-04 Texas Instruments Incorporated Semiconductor package-on-package system including integrated passive components
US7569920B2 (en) 2006-05-10 2009-08-04 Infineon Technologies Ag Electronic component having at least one vertical semiconductor power transistor
US7714453B2 (en) 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US7462506B2 (en) 2006-06-15 2008-12-09 International Business Machines Corporation Carbon dioxide gettering method for a chip module assembly
US8581381B2 (en) 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
US7476980B2 (en) 2006-06-27 2009-01-13 Infineon Technologies Ag Die configurations and methods of manufacture
KR100800478B1 (ko) 2006-07-18 2008-02-04 삼성전자주식회사 적층형 반도체 패키지 및 그의 제조방법
KR100809693B1 (ko) 2006-08-01 2008-03-06 삼성전자주식회사 하부 반도체 칩에 대한 신뢰도가 개선된 수직 적층형멀티칩 패키지 및 그 제조방법
TWI317993B (en) 2006-08-18 2009-12-01 Advanced Semiconductor Eng Stackable semiconductor package
KR100891516B1 (ko) 2006-08-31 2009-04-06 주식회사 하이닉스반도체 적층 가능한 에프비지에이 타입 반도체 패키지와 이를이용한 적층 패키지
KR20080022452A (ko) 2006-09-06 2008-03-11 삼성전자주식회사 Ｐｏｐ 패키지 및 그의 제조 방법
US8049313B2 (en) * 2006-09-20 2011-11-01 Freescale Semiconductor, Inc. Heat spreader for semiconductor package
US7816250B2 (en) 2006-09-29 2010-10-19 Intel Corporation Composite solder TIM for electronic package
JP4524698B2 (ja) 2006-10-26 2010-08-18 エルピーダメモリ株式会社 容量素子を有する半導体装置及びその製造方法
US7829380B2 (en) 2006-10-31 2010-11-09 Qimonda Ag Solder pillar bumping and a method of making the same
US8133762B2 (en) 2009-03-17 2012-03-13 Stats Chippac, Ltd. Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
US7550857B1 (en) 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
TW200824067A (en) 2006-11-29 2008-06-01 Advanced Semiconductor Eng Stacked chip package structure and fabricating method thereof
US7728420B2 (en) 2006-12-07 2010-06-01 International Rectifier Corporation High current lead electrode for semiconductor device
US7608921B2 (en) 2006-12-07 2009-10-27 Stats Chippac, Inc. Multi-layer semiconductor package
US7880280B2 (en) 2007-02-16 2011-02-01 Infineon Technologies Ag Electronic component and method for manufacturing an electronic component
JP2008235401A (ja) 2007-03-19 2008-10-02 Spansion Llc 半導体装置及びその製造方法
JP5003260B2 (ja) 2007-04-13 2012-08-15 日本電気株式会社 半導体装置およびその製造方法
US7553752B2 (en) 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
US7999365B2 (en) 2007-08-03 2011-08-16 International Rectifier Corporation Package for monolithic compound semiconductor (CSC) devices for DC to DC converters
US7687899B1 (en) * 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7671452B1 (en) 2007-08-17 2010-03-02 National Semiconductor Corporation Microarray package with plated contact pedestals
US7547630B2 (en) 2007-09-26 2009-06-16 Texas Instruments Incorporated Method for stacking semiconductor chips
US7834464B2 (en) 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
KR20090043898A (ko) * 2007-10-30 2009-05-07 삼성전자주식회사 스택 패키지 및 그 제조 방법, 및 스택 패키지를 포함하는카드 및 시스템
US20090127700A1 (en) 2007-11-20 2009-05-21 Matthew Romig Thermal conductor lids for area array packaged multi-chip modules and methods to dissipate heat from multi-chip modules
US20090170241A1 (en) 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US8247893B2 (en) * 2007-12-27 2012-08-21 Stats Chippac Ltd. Mountable integrated circuit package system with intra-stack encapsulation
US8138024B2 (en) 2008-02-26 2012-03-20 Stats Chippac Ltd. Package system for shielding semiconductor dies from electromagnetic interference
US8247894B2 (en) * 2008-03-24 2012-08-21 Stats Chippac Ltd. Integrated circuit package system with step mold recess
US8178976B2 (en) 2008-05-12 2012-05-15 Texas Instruments Incorporated IC device having low resistance TSV comprising ground connection
US7964450B2 (en) 2008-05-23 2011-06-21 Stats Chippac, Ltd. Wirebondless wafer level package with plated bumps and interconnects
US7791031B2 (en) 2008-06-09 2010-09-07 Honeywell International Inc. Neutron detection structure
US20100019362A1 (en) 2008-07-23 2010-01-28 Manolito Galera Isolated stacked die semiconductor packages
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US8110912B2 (en) 2008-07-31 2012-02-07 Infineon Technologies Ag Semiconductor device
US8102666B2 (en) * 2008-08-19 2012-01-24 Stats Chippac Ltd. Integrated circuit package system
US8008784B2 (en) 2008-10-02 2011-08-30 Advanced Semiconductor Engineering, Inc. Package including a lead frame, a chip and a sealant
US7843052B1 (en) 2008-11-13 2010-11-30 Amkor Technology, Inc. Semiconductor devices and fabrication methods thereof
US7838337B2 (en) 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US20100164078A1 (en) 2008-12-31 2010-07-01 Ruben Madrid Package assembly for semiconductor devices
US20100230792A1 (en) 2009-03-12 2010-09-16 Scott Irving Premolded Substrates with Apertures for Semiconductor Die Packages with Stacked Dice, Said Packages, and Methods of Making the Same
US8018034B2 (en) 2009-05-01 2011-09-13 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structure
US7955942B2 (en) * 2009-05-18 2011-06-07 Stats Chippac, Ltd. Semiconductor device and method of forming a 3D inductor from prefabricated pillar frame
US8110440B2 (en) 2009-05-18 2012-02-07 Stats Chippac, Ltd. Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure
US8263434B2 (en) 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US8039304B2 (en) 2009-08-12 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structures
US8021930B2 (en) 2009-08-12 2011-09-20 Stats Chippac, Ltd. Semiconductor device and method of forming dam material around periphery of die to reduce warpage
US8169058B2 (en) * 2009-08-21 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars
US8383457B2 (en) * 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US8143097B2 (en) * 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US8138014B2 (en) * 2010-01-29 2012-03-20 Stats Chippac, Ltd. Method of forming thin profile WLCSP with vertical interconnect over package footprint
US8624364B2 (en) * 2010-02-26 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with encapsulation connector and method of manufacture thereof
US8039384B2 (en) 2010-03-09 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces
US8558392B2 (en) 2010-05-14 2013-10-15 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant
US8357564B2 (en) 2010-05-17 2013-01-22 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die
US8482115B2 (en) 2010-05-27 2013-07-09 Stats Chippac Ltd. Integrated circuit packaging system with dual side connection and method of manufacture thereof
US8076184B1 (en) 2010-08-16 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die
US8531021B2 (en) 2011-01-27 2013-09-10 Unimicron Technology Corporation Package stack device and fabrication method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1543291A (zh) * 2003-02-18 2004-11-03 ���µ�����ҵ��ʽ���� 电子部件内置模块及其制造方法
CN1779971A (zh) * 2004-10-22 2006-05-31 松下电器产业株式会社 半导体装置及其制造方法
CN1983533A (zh) * 2005-11-30 2007-06-20 飞思卡尔半导体公司 用于封装半导体器件的方法
US20080315375A1 (en) * 2007-06-25 2008-12-25 Epic Technologies, Inc. Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
US20100133665A1 (en) * 2008-11-29 2010-06-03 Jong-Woo Ha Integrated circuit packaging system with lead frame and method of manufacture thereof

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681528B (zh) * 2012-09-10 2016-08-31 矽品精密工业股份有限公司 半导体封装件及其制法与中介板结构
CN103681528A (zh) * 2012-09-10 2014-03-26 矽品精密工业股份有限公司 半导体封装件及其制法与中介板结构
CN103681468B (zh) * 2012-09-14 2019-08-30 新科金朋有限公司 在Fo-WLCSP中形成双面互连结构的半导体器件和方法
CN103681468A (zh) * 2012-09-14 2014-03-26 新科金朋有限公司 在Fo-WLCSP中形成双面互连结构的半导体器件和方法
US11569136B2 (en) 2012-09-14 2023-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual-sided interconnect structures in FO-WLCSP
CN103681607B (zh) * 2012-09-17 2019-01-18 新科金朋有限公司 半导体器件及其制作方法
CN103681607A (zh) * 2012-09-17 2014-03-26 新科金朋有限公司 半导体器件及其制作方法
CN104969347A (zh) * 2013-01-29 2015-10-07 苹果公司 超薄PoP封装件
CN104253058A (zh) * 2013-06-28 2014-12-31 新科金朋有限公司 在扇出型wlcsp上堆叠半导体小片的方法及半导体装置
CN104253058B (zh) * 2013-06-28 2019-08-06 新科金朋有限公司 在扇出型wlcsp上堆叠半导体小片的方法及半导体装置
CN104733379A (zh) * 2013-12-23 2015-06-24 新科金朋有限公司 在半导体管芯上形成细节距的rdl的半导体器件和方法
CN104733379B (zh) * 2013-12-23 2019-03-12 新科金朋有限公司 在半导体管芯上形成细节距的rdl的半导体器件和方法
CN105405835A (zh) * 2014-09-10 2016-03-16 恒劲科技股份有限公司 中介基板及其制法
CN105405835B (zh) * 2014-09-10 2018-12-28 恒劲科技股份有限公司 中介基板及其制法
CN105702648B (zh) * 2014-12-11 2018-12-21 联发科技股份有限公司 芯片封装结构及其制造方法
US10354974B2 (en) 2014-12-11 2019-07-16 Mediatek Inc. Structure and formation method of chip package structure
CN105702648A (zh) * 2014-12-11 2016-06-22 联发科技股份有限公司 芯片封装结构及其制造方法
CN107210288A (zh) * 2015-02-13 2017-09-26 高通股份有限公司 并排半导体封装
CN111883519A (zh) * 2015-02-13 2020-11-03 高通股份有限公司 并排半导体封装
CN106449588A (zh) * 2015-08-05 2017-02-22 联发科技股份有限公司 半导体封装、半导体设备及半导体封装的制造方法
US10312222B2 (en) 2015-08-05 2019-06-04 Mediatek Inc. Semiconductor package and semiconductor device using the same
CN106449588B (zh) * 2015-08-05 2019-04-05 联发科技股份有限公司 半导体封装、半导体设备及半导体封装的制造方法
CN107301978B (zh) * 2016-04-14 2018-08-03 美光科技公司 具有多个共面中介元件的半导体封装
CN107301978A (zh) * 2016-04-14 2017-10-27 美光科技公司 具有多个共面中介元件的半导体封装
US10529689B2 (en) 2016-04-14 2020-01-07 Micron Technology, Inc. Semiconductor package with multiple coplanar interposers
US11469210B2 (en) 2016-04-14 2022-10-11 Micron Technology, Inc. Semiconductor package with multiple coplanar interposers
CN110571158B (zh) * 2016-05-11 2021-12-21 日月光半导体制造股份有限公司 半导体装置封装及其制造方法
CN110571158A (zh) * 2016-05-11 2019-12-13 日月光半导体制造股份有限公司 半导体装置封装及其制造方法
CN109641738A (zh) * 2016-06-14 2019-04-16 麦斯卓微有限公司 电连接弯曲部件
CN109641738B (zh) * 2016-06-14 2024-01-23 麦斯卓微电子(南京)有限公司 电连接弯曲部件
CN107658273A (zh) * 2016-07-26 2018-02-02 艾马克科技公司 半导体装置及制造方法
CN106558574A (zh) * 2016-11-18 2017-04-05 华为技术有限公司 芯片封装结构和方法
CN110970312B (zh) * 2018-09-28 2022-03-04 台湾积体电路制造股份有限公司 封装件及其形成方法
US11164754B2 (en) 2018-09-28 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming the same
CN110970312A (zh) * 2018-09-28 2020-04-07 台湾积体电路制造股份有限公司 封装件及其形成方法

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