CN102376595A - 形成具有导电层和导电通孔的fo-wlcsp的方法和半导体器件 - Google Patents

形成具有导电层和导电通孔的fo-wlcsp的方法和半导体器件 Download PDF

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CN102376595A
CN102376595A CN2011102340979A CN201110234097A CN102376595A CN 102376595 A CN102376595 A CN 102376595A CN 2011102340979 A CN2011102340979 A CN 2011102340979A CN 201110234097 A CN201110234097 A CN 201110234097A CN 102376595 A CN102376595 A CN 102376595A
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conductive
layer
electrically connected
hole
semiconductor element
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CN102376595B (zh
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J.H.区
S.J.李
J.G.金
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及形成具有导电层和导电通孔的FO-WLCSP的方法和半导体器件。Fo-WLCSP具有在半导体管芯周围形成的第一聚合物层。通过第一聚合物层的第一导电通孔在半导体管芯的周界周围形成。第一互连结构在第一聚合物层的第一表面上面形成且电连接到第一导电通孔。第一互连结构具有第二聚合物层和通过第二聚合物层形成的多个第二通孔。第二互连结构在第一聚合物层的第二表面上面形成且电连接到第一导电通孔。第二互连结构具有第三聚合物层和通过第三聚合物层形成的多个第三通孔。半导体封装可以以PoP布置安装到WLCSP。半导体封装通过第一互连结构或第二互连结构而电连接到WLCSP。

Description

形成具有导电层和导电通孔的FO-WLCSP的方法和半导体器件
技术领域
本发明一般涉及半导体器件，且更具体地涉及一种形成具有通过聚合物层分离的导电层和导电通孔的扇出晶片级芯片尺度封装（Fo-WLCSP）的方法以及半导体器件。
背景技术
常常在现代电子产品中发现半导体器件。半导体器件在电部件的数目和密度方面变化。分立的半导体器件一般包含一种类型的电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件典型地包含几百个到数以百万的电部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池以及数字微镜器件（DMD）。
半导体器件执行各种的功能，诸如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将太阳光转变为电力以及产生用于电视显示的视觉投影。在娱乐、通信、功率转换、网络、计算机以及消费产品的领域中发现半导体器件。还在军事应用、航空、汽车、工业控制器和办公设备中发现半导体器件。
半导体器件利用半导体材料的电属性。半导体材料的原子结构允许通过施加电场或基电流（base current）或通过掺杂工艺而操纵其导电性。掺杂向半导体材料引入杂质以操纵和控制半导体器件的导电性。
半导体器件包含有源和无源电结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂水平和施加电场或基电流，晶体管要么促进要么限制电流的流动。包括电阻器、电容器和电感器的无源结构创建为执行各种电功能所必须的电压和电流之间的关系。无源和有源结构电连接以形成电路，这使得半导体器件能够执行高速计算和其他有用功能。
半导体器件一般使用两个复杂的制造工艺来制造，即，前端制造和和后端制造，每一个可能涉及成百个步骤。前端制造涉及在半导体晶片的表面上形成多个管芯。每个管芯典型地是相同的且包含通过电连接有源和无源部件而形成的电路。后端制造涉及从完成的晶片分割（singulate）各个管芯且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目的是生产较小的半导体器件。较小的器件典型地消耗较少的功率、具有较高的性能且可以更高效地生产。另外，较小的半导体器件具有较小的占位面积，这对于较小的终端产品而言是希望的。较小的管芯尺寸可以通过前端工艺中的改进来获得，该前端工艺中的改进导致管芯具有较小、较高密度的有源和无源部件。后端工艺可以通过电互联和封装材料中的改进而导致具有较小占位面积的半导体器件封装。
图1示出常规封装体叠层（PoP）Fo-WLCSP 10，其中半导体管芯12堆叠在半导体管芯14上面且被密封剂16包围。堆积（build-up）互连结构18在堆叠的半导体管芯12-14和密封剂上面形成。半导体管芯12和14使用接合引线20和22而电连接到互连结构18。半导体管芯24被密封剂26包围。堆积互连结构28在半导体管芯24和密封剂26上面形成。半导体管芯24使用接合引线30而电连接到互连结构28。堆积互连结构18使用在半导体管芯24和密封剂26的周界周围形成的凸块32而电连接到堆积互连结构28。
Fo-WLCSP 10的互连能力受在半导体管芯24周围形成的密封剂26的高度需要限制。即，凸块32必须形成为具有足够的尺寸以跨越堆积互连结构18和28之间的空隙。该空隙由密封剂26的高度指示。因此，密封剂26的高度限制了凸块布置选项、凸块节距、凸块大小和输入/输出（I/O）数目。
发明内容
对于提供一种在半导体管芯周围不使用密封剂以减小凸块节距和凸块大小以及增加凸块布置选项和I/O数目的Fo-WLCSP存在需求。因此，在一个实施例中，本发明是一种形成WLCSP的方法，该方法包含步骤：提供第一聚合物层，该第一聚合物层包括在该第一聚合物层内形成的多个接触焊盘；附连第一聚合物层到载体；将半导体管芯安装到第一聚合物层；在半导体管芯和第一聚合物层上面形成第二聚合物层；形成通过第一和第二聚合物层的多个第一导电通孔；以及在第二聚合物层上面形成第一导电层。第一导电层电连接到第一导电通孔和半导体管芯。第一导电通孔电连接到接触焊盘。该方法还包含步骤：在第二聚合物层和第一导电层上面形成第三聚合物层；形成通过第三聚合物层的多个第二导电通孔；在第三聚合物层上面形成第二导电层；以及在第三聚合物层和第二导电层上面形成第一互连结构。第二导电通孔电连接到第一导电层。第二导电层电连接到第二导电通孔。
在另一实施例中，本发明是一种形成WLCSP的方法，该方法包含步骤：提供第一聚合物层，该第一聚合物层包括在该第一聚合物层内形成的多个接触焊盘；附连第一聚合物层到载体；形成通过第一聚合物层的多个第一导电通孔；以及在第一聚合物层上面形成第一导电层。第一导电通孔电连接到接触焊盘。第一导电层电连接到第一导电通孔。该方法还包含步骤：在第一聚合物层上面形成第二聚合物层；将半导体管芯安装到第二聚合物层；在半导体管芯和第二聚合物层上面形成第三聚合物层；形成通过第二和第三聚合物层的多个第二导电通孔；以及在第三聚合物层上面形成第二导电层。第二导电通孔电连接到第一导电层。第二导电层电连接到第二导电通孔和半导体管芯。该方法还包含步骤：在第三聚合物层和第二导电层上面形成第四聚合物层；形成通过第四聚合物层的多个第三导电通孔；在第四聚合物层上面形成第三导电层；以及在第四聚合物层和第三导电层上面形成第一互连结构。第三导电通孔电连接到第二导电层。第三导电层电连接到第三导电通孔。
在另一实施例中，本发明是一种形成WLCSP的方法，该方法包含步骤：提供半导体管芯；在半导体管芯周围形成第一聚合物层；形成通过第一聚合物层的多个第一导电通孔；在第一聚合物层的第一表面上面形成电连接到第一导电通孔的第一互连结构；以及在第一聚合物层的与第一表面相对的第二表面上面形成第二互连结构。第二互连结构电连接到第一导电通孔。
在另一实施例中，本发明是一种WLCSP，其包含半导体管芯和在半导体管芯周围形成的第一聚合物层以及第二聚合物层。多个第一导电通孔通过第一聚合物层而形成。第一互连结构在第一聚合物层的第一表面上面形成，电连接到第一导电通孔的。第二互连结构在第一聚合物层的与第一表面相对的第二表面上面形成。第二互连结构电连接到第一导电通孔。
附图说明
图1说明具有被密封剂包围的半导体管芯的常规PoP Fo-WLCSP；
图2说明具有安装到其表面的不同类型的封装的PCB；
图3a-3c说明安装到PCB的代表性半导体封装的进一步细节；
图4a-4c说明包含多个半导体管芯的半导体晶片；
图5a-5m说明形成具有通过聚合物层分离的导电层和导电通孔的Fo-WLCSP的工艺；
图6a-6b说明具有通过聚合物层分离的导电层和导电通孔的Fo-WLCSP；
图7说明具有通过聚合物层分离的导电层和导电通孔的堆叠的Fo-WLCSP的PoP布置；
图8a-8r说明形成具有通过聚合物层分离的导电层和导电通孔的Fo-WLCSP的另一工艺；
图9说明具有通过聚合物层分离的导电层和导电通孔的Fo-WLCSP；
图10a-10b说明根据图9形成的PoP Fo-WLCSP；以及
图11a-11b说明根据图6a-6b形成的PoP Fo-WLCSP。
具体实施方式
在下面的描述中，参考图以一个或更多实施例描述本发明，在这些图中相似的标号代表相同或类似的元件。尽管就用于实现本发明目的的最佳模式描述本发明，但是本领域技术人员应当理解，其旨在覆盖可以包括在如下面的公开和图支持的所附权利要求及其等价物限定的本发明的精神和范围内的备选、修改和等价物。
半导体器件一般使用两个复杂制造工艺来制造：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电部件，它们电连接以形成功能电路。诸如晶体管和二极管的有源电部件具有控制电流流动的能力。诸如电容器、电感器、电阻器和变压器的无源电部件创建为执行电路功能所必须的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、蚀刻和平坦化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过诸如离子注入或热扩散的技术将杂质引入到半导体材料中。掺杂工艺修改了有源器件中半导体材料的导电性，将半导体材料转变为绝缘体、导体，或者响应于电场或基电流而动态地改变半导体材料的导电性。晶体管包含不同类型和掺杂程度的区域，其按照需要被布置为使得当施加电场或基电流时晶体管能够促进或限制电流的流动。
通过具有不同电属性的材料层形成有源和无源部件。层可以通过部分由被沉积的材料类型确定的各种沉积技术来形成。例如，薄膜沉积可能涉及化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀和化学电镀工艺。每一层一般被图案化以形成有源部件、无源部件或部件之间的电连接的部分。
可以使用光刻对层进行图案化，光刻涉及例如光刻胶的光敏材料在待被图案化的层上的沉积。使用光，图案从光掩模转印到光刻胶。受光影响的光刻胶图案的部分使用溶剂来去除，露出待被图案化的底层的部分。光刻胶的剩余部分被去除，留下图案化层。备选地，一些类型的材料通过使用诸如化学电镀和电解电镀这样的技术来直接向原先沉积/蚀刻工艺形成的区域或空位沉积材料而被图案化。
在现有图案上沉积材料的薄膜可以放大底层图案且形成不均匀的平坦表面。需要均匀的平坦表面来生产更小且更致密堆叠的有源和无源部件。平坦化可以用于从晶片的表面去除材料且产生均匀的平坦表面。平坦化涉及使用抛光垫对晶片的表面进行抛光。研磨材料和腐蚀化学物在抛光期间被添加到晶片的表面。组合的研磨物的机械行为和化学物的腐蚀行为去除任何不规则拓扑，导致均匀的平坦表面。
后端制造指将完成的晶片切割或分割为各个管芯且然后封装管芯以用于结构支撑和环境隔离。为了分割管芯，晶片沿着称为切割线或划线的晶片的非功能区域被划片且折断。使用激光切割工具或锯条来分割晶片。在分割之后，各个芯片被安装到封装基板，该封装基板包括引脚或接触焊盘以用于与其他系统部件互连。在半导体管芯上形成的接触焊盘然后连接到封装内的接触焊盘。电连接可以使用焊料凸块、柱形凸块、导电胶或引线接合来制成。密封剂或其他成型材料沉积在封装上以提供物理支撑和电隔离。完成的封装然后被插入到电系统中且使得半导体器件的功能性对于其他系统部件可用。
图2说明具有芯片载体基板或印刷电路板（PCB）52的电子器件50，该芯片载体基板或印刷电路板（PCB）52具有安装在其表面上的多个半导体封装。取决于应用，电子器件50可以具有一种类型的半导体封装或多种类型的半导体封装。用于说明性目的，在图2中示出了不同类型的半导体封装。
电子器件50可以是使用半导体封装以执行一个或更多电功能的独立系统。备选地，电子器件50可以是较大系统的子部件。例如，电子器件50可以是蜂窝电话、个人数字助理（PDA）、数码摄像机（DVC）或其他电子通信器件的一部分。备选地，电子器件50可以是图形卡、网络接口卡或可以被插入到计算机中的其他信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件或其他半导体管芯或电部件。微型化和重量减小对于这些产品被市场接受是至关重要的。半导体器件之间的距离必须减小以实现更高的密度。
在图2中，PCB 52提供用于安装到PCB上的半导体封装的结构支撑和电互连的一般性基板。使用蒸发、电解电镀、化学电镀、丝网印刷或者其他合适的金属沉积工艺，导电信号迹线54在PCB 52的表面上或其层内形成。信号迹线54提供半导体封装、安装的部件以及其他外部系统部件中的每一个之间的电通信。迹线54还向半导体封装中的每一个提供功率和接地连接。
在一些实施例中，半导体器件具有两个封装级别。第一级封装是用于机械和电附连半导体管芯到中间载体的技术。第二级封装涉及机械和电附连中间载体到PCB。在其他实施例中，半导体器件可以仅具有第一级封装，其中管芯被直接机械和电地安装到PCB。
用于说明目的，在PCB 52上示出包括引线接合封装56和倒装芯片58的若干类型的第一级封装。另外，示出在PCB 52上安装的若干类型的第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（LGA）66、多芯片模块（MCM）68、四方扁平无引脚封装（QFN）70以及方形扁平封装72。取决于系统需求，使用第一和第二级封装类型的任何组合配置的半导体封装以及其他电子部件的任何组合可以连接到PCB 52。在一些实施例中，电子器件50包括单一附连的半导体封装，而其他实施例需要多个互连封装。通过在单个基板上组合一个或更多半导体封装，制造商可以将预制部件结合到电子器件和系统中。因为半导体封装包括复杂的功能性，可以使用较廉价的部件和流水线制造工艺来制造电子器件。所得到的器件较不倾向于发生故障且对于制造而言较不昂贵，导致针对消费者的较少的成本。
图3a-3c示出示例性半导体封装。图3a说明安装在PCB 52上的DIP 64的进一步细节。半导体管芯74包括有源区域，该有源区域包含实现为根据管芯的电设计而在管芯内形成且电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及在半导体管芯74的有源区域内形成的其他电路元件。接触焊盘76是诸如铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）或银（Ag）的一层或多层导电材料，且电连接到半导体管芯74内形成的电路元件。在DIP 64的组装期间，半导体管芯74使用金-硅共熔层或者诸如热环氧物或环氧树脂的粘合剂材料而安装到中间载体78。封装体包括诸如聚合物或陶瓷的绝缘封装材料。导线80和引线接合82提供半导体管芯74和PCB 52之间的电互连。密封剂84沉积在封装上，以通过防止湿气和颗粒进入封装且污染管芯74或引线接合82而进行环境保护。
图3b说明安装在PCB 52上的BCC 62的进一步细节。半导体管芯88使用底层填料或者环氧树脂粘合剂材料92而安装在载体90上。引线接合94提供接触焊盘96和98之间的第一级封装互连。模塑料或密封剂100沉积在半导体管芯88和引线接合94上，从而为器件提供物理支撑和电隔离。接触焊盘102使用诸如电解电镀或化学电镀之类的合适的金属沉积工艺而在PCB 52的表面上形成以防止氧化。接触焊盘102电连接到PCB 52中的一个或更多导电信号迹线54。凸块104在BCC 62的接触焊盘98和PCB 52的接触焊盘102之间形成。
在图3c中，使用倒装芯片类型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区域108包含实现为根据管芯的电设计而形成的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及有源区域108内的其他电路元件。半导体管芯58通过凸块110电和机械连接到载体106。
使用利用凸块112的BGA类型第二级封装，BGA 60电且机械连接到PCB 52。半导体管芯58通过凸块110、信号线114和凸块112电连接到PCB 52中的导电迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电迹线的短导电路径以便减小信号传播距离、降低电容且改善整体电路性能。在另一实施例中，半导体管芯58可以使用倒装芯片类型第一级封装来直接机械和电地连接到PCB 52而不使用中间载体106。
图4a示出具有用于结构支撑的基底基板材料122的半导体晶片120，该基底基板材料诸如是硅、锗、砷化镓、磷化铟或者碳化硅。如上所述，在晶片120上形成通过划片线126分离的多个半导体管芯或组件124。
图4b示出半导体晶片120的一部分的剖面图。每个半导体管芯124具有有源表面130，该有源表面包含实现为在管芯内形成的且根据管芯的电设计和功能而电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多个晶体管、二极管以及在有源表面130内形成的其他电路元件以实现诸如数字信号处理（DSP）、ASIC、存储器或其他信号处理电路之类的模拟电路或数字电路。半导体管芯124还可以包含诸如电感器、电容器和电阻器的IPD以用于RF信号处理。在一个实施例中，半导体管芯124是倒装芯片类型的半导体芯片。
使用PVD、CVD、电解电镀、化学电镀工艺或其他合适的金属沉积工艺而在有源表面130上形成导电层132。导电层132可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料中的一层或更多层。导电层132操作为电连接到有源表面130上的电路的接触焊盘。
在图4c中，使用锯条或激光切割工具136，半导体晶片120通过划片线126分割成各个半导体管芯124。
与图2和图3a-3c相关联，图5a-5m说明形成具有通过聚合物层分离的导电层和导电通孔的FO－WLCSP的工艺。在图5a中，基板或载体140包含诸如硅、聚合物、氧化铍或其他合适的低价刚性材料的临时或牺牲基底材料以用于结构支撑。在一个实施例中，载体140是胶带。
在载体140上形成聚合物层142。聚合物层142可以是氧化物、氮化物或玻璃材料。使用诸如PVD、CVD、溅射、电解电镀以及化学电镀之类的图案化和金属沉积工艺，在聚合物层142内形成导电层144。导电层144可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或更多层。
临时载体或基板146包含诸如硅、聚合物、聚合物复合物、金属、陶瓷、玻璃、玻璃环氧物、氧化铍或其他合适的低成本刚性材料的牺牲基底材料以用于结构支撑。在载体146上面形成作为临时粘合接合膜或蚀刻停止层的界面层或双面胶带148。
在图5b中，以聚合物层142和接触焊盘144为引导，载体140被安装到载体146上面的界面层148。在一个实施例中，聚合物层142堆叠到界面层148。导电层144操作为在管芯附连区域149的周界周围形成的接触焊盘阵列。聚合物层142和接触焊盘144组成互连结构。
在图5c中，通过在箭头150的方向上的机械剥离从聚合物层142去除载体140。聚合物层142和接触焊盘144保持贴到界面层148和载体146。备选地，可以通过化学蚀刻、CMP、机械研磨、热烘焙、UV光、激光扫描或湿法拆模来去除载体140以露出聚合物层142。
在图5d中，使用拾放操作，来自图4a-4c的半导体管芯124被安装到聚合物层142，其中有源表面130远离聚合物层定向。半导体管芯124布置在接触焊盘144的阵列内的管芯附连区域149上面。
在图5e中，在半导体管芯124和聚合物层142上形成聚合物层154。聚合物层154可以是氧化物、氮化物或玻璃材料。聚合物层154的一部分可以通过蚀刻工艺去除以露出接触焊盘132以用于后续电互连。
在图5f中，使用机械钻孔、激光钻孔或深反应离子蚀刻（DRIE），形成通过聚合物层154和142向下延伸到接触焊盘144的多个通孔156。在图5g中，使用电解电镀、化学电镀工艺或其他合适的金属沉积工艺，通孔156被填充有Au、Cu、Sn、Ni、Au、Ag、Ti、钨（W）、多晶硅或其他合适的导电材料以形成z方向的导电柱子或通孔158。导电通孔158电连接到接触焊盘144。
图5h示出在半导体管芯124的周界周围形成通过聚合物层154的导电通孔158沿着图5g的线5h-5h截取的顶视图。
使用图案化和诸如印刷、PVD、CVD、溅射、电解电镀和化学电镀之类的金属沉积工艺而在聚合物层154和导电通孔158上面形成导电层或再分配层（RDL）160。导电层160可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或更多层。导电层160的一个部分电连接到接触焊盘132和导电通孔158。取决于半导体管芯124的设计和功能，导电层160的其他部分可以是电共同的或电隔离的。
在图5i中，在聚合物层154和导电层160上面形成聚合物层162。聚合物层162可以是氧化物、氮化物或玻璃材料。如图5j所示，使用机械钻孔、激光钻孔或DRIE形成通过聚合物层162向下延伸到导电层160的多个通孔164。在图5k中，使用电解电镀、化学电镀工艺或其他合适的金属沉积工艺，通孔164被填充有Au、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅或其他合适的导电材料以形成z方向的导电柱子或通孔166。导电通孔166电连接到导电层160。
使用图案化和诸如印刷、PVD、CVD、溅射、电解电镀和化学电镀之类的金属沉积工艺而在聚合物层162和导电通孔166上面形成导电层或RDL 168。导电层168可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或更多层。导电层168的一个部分电连接到导电通孔166。取决于半导体管芯124的设计和功能，导电层168的其他部分可以是电共同的或电隔离的。
在图5l中，在导电层168上面形成可选凸块下金属化部（UBM）177。在聚合物层162、导电层168和UBM 177上面形成阻焊层170。阻焊层170的一部分通过蚀刻工艺去除以露出导电层168或UBM 177以用于凸块形成或附加的封装互连。备选地，使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化而在聚合物层162、导电层168和UBM 177上面形成绝缘或钝化层。绝缘层包含二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）或具有类似绝缘和结构属性的其他材料中的一层或更多层。聚合物层162、导电通孔166、导电层168、UBM 177和光刻胶层170组成互连结构。
在图5m中，使用锯条或激光切割工具174，半导体管芯124被分割成各个Fo-WLCSP 172。图6a示出在分割之后Fo-WLCSP 172的剖面图。临时载体146和界面层148通过化学蚀刻、机械剥离、CMP、机械研磨、热烘焙、UV光、激光扫描或湿法拆模来去除以露出接触焊盘144。
使用蒸发、电解电镀、化学电镀、球滴或丝网印刷工艺，在UMB 177上面沉积导电凸块材料。凸块材料可以是具有可选助焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸块材料可以是共熔Sn/Pb、高铅焊料或无铅焊料。凸块材料使用合适的附连或接合工艺而接合到UBM 177。在一个实施例中，凸块材料通过加热材料到其熔点之上而进行回流以形成圆球或凸块176。在一些应用中，凸块176被二次回流以改善与UBM 177的电接触。凸块还可以被压缩接合到UBM 177。凸块176代表可以在UBM 177上面形成的一种类型的互连结构。
在Fo-WLCSP 172中，半导体管芯124通过导电层160和168以及导电通孔158和166电连接到凸块176和接触焊盘144以用于外部电互连。在半导体管芯124的周界周围形成接触焊盘144和凸块176的阵列。图6b示出具有接触焊盘144的阵列的Fo-WLCSP 172的顶视图。如图1所描述的，无密封剂或模塑料地形成Fo-WLCSP 172。而是，在半导体管芯124、导电层160和168、导电通孔158和166以及导电焊盘144周围形成聚合物层142、154和162以提供电隔离和结构支撑。聚合物层142、154和162可以形成有比现有技术中发现的密封剂低的高度。因此，聚合物层142、154和162提供柔性凸块布置选项、减小的凸块节距、增加的I/O数量以及减小Fo-WLCSP 172的高度。
Fo-WLCSP 172适于封装体叠层（PoP）应用，诸如图7所示，Fo-WLCSP 178堆叠在Fo-WLCSP 172上面。Fo-WLCSP 178类似于Fo-WLCSP 172那样配置。Fo-WLCSP 172和Fo-WLCSP 178之间的电信号路由通过在半导体管芯124的周界周围形成的凸块176的阵列。因为没有金线接合用于Fo-WLCSP之间的信号传输，所以互连电感和电容减小且信号完整性改善。反射噪声和串扰可以通过匹配半导体管芯124与在聚合物层142、154和162中形成的导电层160和168、导电通孔158和166以及接触焊盘144之间的阻抗而减小。
与图2和3a-3c相关联，图8a-8r说明形成具有通过聚合物层分离的导电层和导电通孔的Fo-WLCSP的另一工艺。在图8a中，基板或载体180包含诸如硅、聚合物、氧化铍或其他合适的低价刚性材料的临时或牺牲基底材料以用于结构支撑。在一个实施例中，载体180是胶带。
在载体180上形成聚合物层182。聚合物层182可以是氧化物、氮化物或玻璃材料。使用图案化和诸如PVD、CVD、溅射、电解电镀以及化学电镀之类的金属沉积工艺而在聚合物层182内形成导电层184。导电层184可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或更多层。
临时载体或基板186包含诸如硅、聚合物、聚合物复合物、金属、陶瓷、玻璃、玻璃环氧物、氧化铍或其他合适的低成本刚性材料之类的牺牲基底材料以用于结构支撑。在载体186上面形成作为临时粘合接合膜或蚀刻停止层的界面层或双面胶带188。
在图8b中，以聚合物层182和接触焊盘184为引导，载体180被安装到载体186上面的界面层188。在一个实施例中，聚合物层182堆叠到界面层188。导电层184操作为在聚合物层182的基本整个表面区域之上均匀布置的接触焊盘阵列。
在图8c中，通过在箭头190的方向上的机械剥离从聚合物层182去除载体180。聚合物层182和接触焊盘184保持贴到界面层188和载体186。备选地，载体180可以通过化学蚀刻、CMP、机械研磨、热烘焙、UV光、激光扫描或湿法拆模来去除以露出聚合物层182。
图8d示出在去除载体182之后的聚合物层182。如图8e所示，使用机械钻孔、激光钻孔或DRIE，形成通过聚合物层132向下延伸到接触焊盘184的多个通孔196。在图8f中，使用电解电镀、化学电镀工艺或其他合适的金属沉积工艺，通孔196被填充有Au、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅或其他合适的导电材料以形成z方向的导电柱子或通孔198。导电通孔198电连接到接触焊盘184。图8g示出在接触焊盘184上面形成的导电通孔198沿着图8f的线8g-8g截取的顶视图。
使用图案化和诸如印刷、PVD、CVD、溅射、电解电镀和化学电镀之类的金属沉积工艺而在聚合物层182和导电通孔198上面形成导电层或者RDL 200。导电层200可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或更多层。导电层200的一个部分电连接到导电通孔198。取决于半导体管芯124的设计和功能，导电层200的其他部分可以是电共同的或电隔离的。
在图8h中，在聚合物层182和导电层200上面形成聚合物层202。聚合物层202可以是氧化物、氮化物或玻璃材料。聚合物层182和202、导电通孔198以及导电层200组成互连结构。
在图8i中，使用拾放操作，来自图4a-4c的半导体管芯124被安装到聚合物层202，其中有源表面130远离聚合物层定向。
在图8j中，在半导体管芯124和聚合物层202上面形成聚合物层204。聚合物层204可以是氧化物、氮化物或玻璃材料。聚合物层204的一部分可以通过蚀刻工艺去除以露出半导体管芯124的接触焊盘132以用于后续的电互连。
在图8k中，使用机械钻孔、激光钻孔或DRIE形成通过聚合物层204和202向下延伸到导电层200的多个通孔206。在半导体管芯124的周界周围形成通孔206。在图8l中，使用电解电镀、化学电镀工艺或其他合适的金属沉积工艺，通孔206被填充有Au、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅或其他合适的导电材料以形成z方向的导电柱子或通孔208。导电通孔208电连接到导电层200。
图8m示出在半导体管芯124周围形成的导电通孔208沿着图8l的8m-8m线截取的顶视图。
使用图案化和诸如印刷、PVD、CVD、溅射、电解电镀和化学电镀之类的金属沉积工艺而在聚合物层204和导电通孔208上面形成导电层或再分配层RDL 210。导电层210可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或更多层。导电层210的一个部分电连接到接触焊盘132和导电通孔208。取决于半导体管芯124的设计和功能，导电层210的其他部分可以是电共同的或电隔离的。
在图8n中，在聚合物层204和导电层210上面形成聚合物层212。聚合物层212可以是氧化物、氮化物或玻璃材料。如图8o所示，使用机械钻孔、激光钻孔或DRIE形成通过聚合物层212向下延伸到导电层210的多个通孔214。
在图8p中，使用电解电镀、化学电镀工艺或其他合适的金属沉积工艺，通孔214被填充有Au、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅或其他合适的导电材料以形成z方向的导电柱子或通孔216。导电通孔216电连接到导电层210。
使用图案化和诸如印刷、PVD、CVD、溅射、电解电镀和化学电镀之类的金属沉积工艺而在聚合物层212和导电通孔216上面形成导电层或RDL 218。导电层218可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或更多层。导电层218的一个部分电连接到导电通孔216。取决于半导体管芯124的设计和功能，导电层218的其他部分可以是电共同的或电隔离的。
在图8q中，在导电层218上面形成可选的UBM 228。在聚合物层212、导电层218和UBM 228上面形成阻焊层220。阻焊层220的一部分通过蚀刻工艺去除以露出导电层218或UBM 228以用于凸块形成或附加的封装互连。备选地，使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化，在聚合物层212、导电层218和UBM 228上面形成绝缘或钝化层。绝缘层包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构属性的其他材料的一层或更多层。聚合物层212、导电通孔216、导电层218、UBM 228以及光刻胶层220组成互连结构。
在图8r中，使用锯条或激光切割工具224，半导体管芯124被分割成各个Fo-WLCSP 222。图9示出在分割之后Fo-WLCSP 222的剖面图。临时载体186和界面层188通过化学蚀刻、机械剥离、CMP、机械研磨、热烘焙、UV光、激光扫描或湿法拆模来去除以露出接触焊盘184。
使用蒸发、电解电镀、化学电镀、球滴或丝网印刷工艺，在UMB 228上面沉积导电凸块材料。凸块材料可以是具有可选助焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸块材料可以是共熔Sn/Pb、高铅焊料或无铅焊料。凸块材料使用合适的附连或接合工艺而接合到UBM 228。在一个实施例中，凸块材料通过加热材料到其熔点之上而进行回流以形成圆球或凸块226。在一些应用中，凸块226被二次回流以改善与UBM 228的电接触。凸块还被压缩接合到UBM 228。凸块226代表可以在UBM 228上面形成的一种类型的互连结构。
在Fo-WLCSP 222中，半导体管芯124通过导电层200、210和218以及导电通孔198、208和216而电连接到凸块226和接触焊盘184以用于外部电互连。接触焊盘184和凸块226的阵列在Fo-WLCSP 222的全部表面区域上面形成。如图1所描述的，无密封剂或模塑料地形成Fo-WLCSP 222。而是，在半导体管芯124、导电层200、210和218、导电通孔198、208和216以及导电焊盘184周围形成聚合物层182、202、204和212以提供电隔离和结构支撑。聚合物层182、202、204和212可以形成为具有比现有技术中发现的密封剂低的高度。因此，聚合物层182、202、204和212提供柔性凸块布置选项、减小的凸块节距、增加的I/O数量以及减小Fo-WLCSP 222的高度。
Fo-WLCSP 222适于PoP应用，如图10a所示，Fo-WLCSP 230堆叠在Fo-WLCSP 222上面。在Fo-WLCSP 230中，使用管芯附连粘合剂234，半导体管芯231被安装到半导体管芯232。半导体管芯231和232均具有有源表面，该有源表面包含实现为在管芯内形成且根据管芯的电设计和功能而电互连的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管和在有源表面内形成的其他电路元件以实现诸如DSP、ASIC、存储器或其他信号处理电路的模拟电路或数字电路。半导体管芯231和232还可以包含诸如电感器、电容器和电阻器之类的IPD以用于RF信号处理。接合引线236和238分别电连接到半导体管芯231和232上的接触焊盘。密封剂240沉积在半导体管芯231和232以及接合引线236和238上面。堆积互连结构242在半导体管芯232和密封剂240上面形成。半导体管芯232使用管芯附连粘合剂235接合到互连结构242。接合引线236和238通过互连结构242电连接到凸块244，其进而电连接到Fo-WLCSP 222的接触焊盘。半导体管芯231和232、密封剂240和互连结构242组成半导体封装。图10b示出接触焊盘184和聚合物层182通过图10a的线10b-10b截取的剖面图。
Fo-WLCSP 222和Fo-WLCSP 230之间的电信号路由通过接触焊盘184和凸块244的阵列。因为没有金线接合用于Fo-WLCSP之间的信号传输，所以互连电感和电容减小且信号完整性改善。反射噪声和串扰可以通过匹配半导体管芯124与在聚合物层182、202、204和212中形成的导电层200、210和218、导电通孔198、208和216以及接触焊盘184之间的阻抗而减小。
类似于图6a，图11a示出另一PoP配置，其中Fo-WLCSP 248堆叠在Fo-WLCSP 250上面。在Fo-WLCSP 248中，使用管芯附连粘合剂256，半导体管芯252被安装到半导体管芯254。半导体管芯252和254均具有有源表面，该有源表面包含实现为在管芯内形成且根据管芯的电设计和功能而电互连的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管和在有源表面内形成的其他电路元件以实现诸如DSP、ASIC、存储器或其他信号处理电路之类的模拟电路或数字电路。半导体管芯252和254还可以包含诸如电感器、电容器和电阻器之类的IPD以用于RF信号处理。接合引线260和262分别电连接到半导体管芯252和254上的接触焊盘。密封剂264沉积在半导体管芯252和254以及接合引线260和262上面。堆积互连结构266在半导体管芯252和254以及密封剂264上面形成。半导体管芯254使用管芯附连粘合剂258接合到互连结构266。接合引线260和262通过互连结构266电连接到凸块268，进而电连接到Fo-WLCSP 250的接触焊盘144。半导体管芯252和254、密封剂264和互连结构266组成半导体封装。图11b示出接触焊盘144和聚合物层142通过图11a的线11b-11b截取的剖面图。
Fo-WLCSP 248和Fo-WLCSP 250之间的电信号路由通过接触焊盘144和凸块268的阵列。因为没有金线接合用于Fo-WLCSP之间的信号传输，所以互连电感和电容减小且信号完整性改善。反射噪声和串扰可以通过匹配半导体管芯124与在聚合物层142、154和162中形成的导电层160和168、导电通孔158和166以及接触焊盘144之间的阻抗而减小。
尽管已经详细说明了本发明的一个或更多实施例，但是本领域技术人员应当意识到，可以在不偏离如随后的权利要求提及的本发明的范围的情况下对那些实施例做出修改和改写。

Claims (25)

1.一种制作晶片级芯片尺度封装（WLCSP）的方法，包含：
提供第一聚合物层，该第一聚合物层包括在该第一聚合物层内形成的多个接触焊盘；
附连第一聚合物层到载体；
将半导体管芯安装到第一聚合物层；
在半导体管芯和第一聚合物层上面形成第二聚合物层；
形成通过第一和第二聚合物层的多个第一导电通孔，该第一导电通孔电连接到接触焊盘；
在第二聚合物层上面形成第一导电层，该第一导电层电连接到第一导电通孔和半导体管芯；
在第二聚合物层和第一导电层上面形成第三聚合物层；
形成通过第三聚合物层的多个第二导电通孔，该第二导电通孔电连接到第一导电层；
在第三聚合物层上面形成第二导电层，该第二导电层电连接到第二导电通孔；以及
在第三聚合物层和第二导电层上面形成第一互连结构。
2.根据权利要求1所述的方法，还包括在半导体管芯的周界周围形成第一导电通孔。
3.根据权利要求1所述的方法，还包括在半导体管芯的周界周围形成接触焊盘。
4.根据权利要求1所述的方法，还包括在半导体管芯下面形成接触焊盘。
5.根据权利要求1所述的方法，其中形成第一互连结构包括：
在第三聚合物层和第二导电层上面形成绝缘层；
去除绝缘层的一部分以露出第二导电层；以及
在露出的第二导电层上面形成多个凸块。
6.根据权利要求1所述的方法，还包括：
提供半导体封装；
将半导体封装安装到WLCSP；以及
通过第一互连结构，电连接半导体封装到WLCSP。
7.根据权利要求1所述的方法，还包括：
去除载体；以及
在第一聚合物层和接触焊盘上面形成第二互连结构。
8.一种制作晶片级芯片尺度封装（WLCSP）的方法，包含：
提供第一聚合物层，该第一聚合物层包括在该第一聚合物层内形成的多个接触焊盘；
附连第一聚合物层到载体；
形成通过第一聚合物层的多个第一导电通孔，该第一导电通孔电连接到接触焊盘；
在第一聚合物层上面形成第一导电层，该第一导电层电连接到第一导电通孔；
在第一聚合物层上面形成第二聚合物层；
将半导体管芯安装到第二聚合物层；
在半导体管芯和第二聚合物层上面形成第三聚合物层；
形成通过第二和第三聚合物层的多个第二导电通孔，该第二导电通孔电连接到第一导电层；
在第三聚合物层上面形成第二导电层，该第二导电层电连接到第二导电通孔和半导体管芯；
在第三聚合物层和第二导电层上面形成第四聚合物层；
形成通过第四聚合物层的多个第三导电通孔，该第三导电通孔电连接到第二导电层；
在第四聚合物层上面形成第三导电层，该第三导电层电连接到第三导电通孔；以及
在第四聚合物层和第三导电层上面形成第一互连结构。
9.根据权利要求8所述的方法，还包括：
在半导体管芯下面形成第一导电通孔；以及
在半导体管芯下面形成接触焊盘。
10.根据权利要求8所述的方法，还包括在半导体管芯的周界周围形成第二导电通孔。
11.根据权利要求8所述的方法，其中形成第一互连结构包括：
在第四聚合物层和第三导电层上面形成绝缘层；
去除绝缘层的一部分以露出第三导电层；以及
在露出的第三导电层上面形成多个凸块。
12.根据权利要求8所述的方法，还包括：
提供半导体封装；
将半导体封装安装到WLCSP；以及
通过第一互连结构，电连接半导体封装到WLCSP。
13.根据权利要求8所述的方法，还包括：
去除载体；以及
在第一聚合物层和接触焊盘上面形成第二互连结构。
14.一种制作晶片级芯片尺度封装（WLCSP）的方法，包含：
提供半导体管芯；
在半导体管芯周围形成第一聚合物层；
形成通过第一聚合物层的多个第一导电通孔；
在第一聚合物层的第一表面上面形成电连接到第一导电通孔的第一互连结构；以及
在第一聚合物层的与第一表面相对的第二表面上面形成第二互连结构，该第二互连结构电连接到第一导电通孔。
15.根据权利要求14所述的方法，其中形成第一互连结构包括：
提供第二聚合物层，该第二聚合物层包括在第二聚合物层内形成的多个接触焊盘；
形成通过第二聚合物层的多个第二导电通孔，该第二导电通孔电连接到接触焊盘；
在第二聚合物层上面形成第一导电层，该第一导电层电连接到第二导电通孔；以及
在第二聚合物层上面形成第三聚合物。
16.根据权利要求15所述的方法，还包括：
在半导体管芯下面形成第二导电通孔；以及
在半导体管芯下面形成接触焊盘。
17.根据权利要求14所述的方法，其中形成第一互连结构包括提供第二聚合物层，该第二聚合物层包括在第二聚合层内形成的多个接触焊盘，第一导电通孔电连接到接触焊盘。
18.根据权利要求14所述的方法，其中形成第二互连结构包括：
在第一聚合物层上面形成第一导电层，该第一导电层电连接到第一导电通孔和半导体管芯；
在第一聚合物层和第一导电层上面形成第二聚合物层；
形成通过第二聚合物层的多个第二导电通孔，该第二导电通孔电连接到第一导电层；以及
在第二聚合物层上面形成第二导电层，该第二导电层电连接到第二导电通孔。
19.根据权利要求14所述的方法，还包括在半导体管芯的周界周围形成第一导电通孔。
20.根据权利要求14所述的方法，还包括：
提供半导体封装；
将半导体封装安装到WLCSP；以及
通过第一互连结构或第二互连结构，电连接半导体封装到WLCSP。
21.一种晶片级芯片尺度封装（WLCSP），包含：
半导体管芯；
在半导体管芯周围形成的第一聚合物层以及第二聚合物层；
通过第一聚合物层形成的多个第一导电通孔；
在第一聚合物层的第一表面上面形成的电连接到第一导电通孔的第一互连结构；以及
在第一聚合物层的与第一表面相对的第二表面上面形成的第二互连结构，该第二互连结构电连接到第一导电通孔。
22.根据权利要求21所述的WLCSP，其中第一互连结构包括：
第二聚合物层，包括在第二聚合物层内形成的多个接触焊盘；
多个第二导电通孔，通过第二聚合物层形成且电连接到接触焊盘；
第一导电层，在第二聚合物层上面形成且电连接到第二导电通孔；以及
第三聚合物层，在第二聚合物层上面形成。
23.根据权利要求21所述的WLCSP，其中第一互连结构包括第二聚合物层，该第二聚合物层包括在第二聚合物层内形成的多个接触焊盘，第一导电通孔电连接到接触焊盘。
24.根据权利要求21所述的WLCSP，其中第二互连结构包括：
第一导电层，在第一聚合物层上面形成且电连接到第一导电通孔和半导体管芯；
第二聚合物层，在第一聚合物层和第一导电层上面形成；
多个第二导电通孔，通过第二聚合物层形成且电连接到第一导电层；以及
第二导电层，在第二聚合物层上面且电连接到第二导电通孔。
25.根据权利要求21所述的WLCSP，还包括半导体封装，该半导体封装安装到WLCSP且通过第一互连结构或第二互连结构而电连接到WLCSP。
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