CN102324845B - Control method for single-inductance double-output DC-DC (direct current) switching power supply and circuit thereof - Google Patents
Control method for single-inductance double-output DC-DC (direct current) switching power supply and circuit thereof Download PDFInfo
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- CN102324845B CN102324845B CN 201110285931 CN201110285931A CN102324845B CN 102324845 B CN102324845 B CN 102324845B CN 201110285931 CN201110285931 CN 201110285931 CN 201110285931 A CN201110285931 A CN 201110285931A CN 102324845 B CN102324845 B CN 102324845B
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Abstract
The invention relates to a control method for a single-inductance double-output DC-DC (direct current) switching power supply and a circuit thereof. Two DC-DC converters are integrated in one chip to generate outputs of two voltages. Two output branches share one inductance. A time sharing multiplex primary and secondary loop control method is adopted. A time sharing conduction switch is arrangedat an output end of each output branch. One clock period is divided into a plurality of units. In each divided unit of the clock period, one path of output is independently controlled. The control method is characterized in that a secondary loop which comprises two comparators and a gating signal generation selection circuit which comprises a digital logic circuit are arranged to control a secondary loop power tube, so that the sizes of load currents of two paths of outputs are random; and in each switching period, control gating signals are sent to the two branches and the two gating signalshave opposite phases, so that two secondary switches are respectively turned on and turned off for once in the ascending and descending stages of an inductive current, and thus, the stable outputs ofthe two branches are realized.
Description
Technical field
The present invention relates to power supply changeover device, particularly at control method and the circuit thereof of a kind of single inductance dual-output DC-DC Switching Power Supply of IC interior, belong to microelectronics technology.
Background technology
In the modern integrated circuits field, keep simultaneously the performance of integrated circuit in order to reduce power consumption, multiple voltage supply becomes main flow trend, can provide two (many) roads of single inductance Voltage-output DC-DC conversion chip of the different voltages of two-way (and multichannel) to arise at the historic moment.The DC-DC transducer of the single inductance two-way Voltage-output of tradition, control method is various, wherein the single inductance dual-output DC-DC of peak electricity flow pattern has higher transformation efficiency and less voltage ripple because of it, thereby become the focus of research, existing control circuit (Fig. 1) is that major loop is traditional peak-current mode that works in continuous current mode (CCM), and the control of inferior loop is still for working in the peak-current mode of continuous current mode (CCM).This control mode has a defective: as shown in Figure 2, owing to only controlling time loop with a comparator, so can only in inductance rise time section, produce a secondary loop control signal, control the loop power tube two times, cause the load current range of two-way output limited.Be embodied in one tunnel load current and must be lower than other one tunnel load current, (being that the load current of the first branch road is less than the load current of the second branch road in example shown in Figure 2) otherwise, single inductance doubleway output DC-DC converter system can produce vibration, causes the output voltage ripple greater than normality.
Summary of the invention
The present invention on the basis of existing technology, a kind of control method and circuit thereof of single inductance dual-output DC-DC switch converters are provided, adopt major loop control model same as the prior art, add and improved inferior loop that consisted of by two comparators and produced by the gating signal that Digital Logical Circuits consists of and selected circuit to control inferior loop power tube, can make the load current size of two-way output arbitrarily, be not subject to the above restrictions, single inductance dual-output DC-DC transducer still keeps stable simultaneously.
Technical scheme of the present invention is: a kind of control method of single inductance dual-output DC-DC Switching Power Supply, integrated two DC-DC converters in chip piece, produce the output of two kinds of voltages, two output branch roads share an inductance, adopt the primary and secondary loop control method of time-sharing multiplex, at each output of exporting branch road the timesharing actuating switch is set, a clock cycle is divided into a plurality of unit, in each clock cycle division unit, separately one tunnel output is controlled; Be provided with the major loop control circuit, inferior loop control circuit, drive circuit, voltage sampling circuit and power stage circuit, it is characterized in that: the inferior loop control circuit that comprises two comparators formations and the gating signal generation that comprises the Digital Logical Circuits formation are set select circuit to control inferior loop power tube, make the load current size of two-way output arbitrarily, in each switch periods, all send the control gating signal to two branch roads, and two gating signals are mutually anti-phase, so that two secondary switch rise and open respectively and turn-off once in the decline stage at inductive current, realize the stable output of two branch roads.
Realize the circuit of the control method of above-mentioned single inductance dual-output DC-DC Switching Power Supply, be provided with the major loop control circuit, inferior loop control circuit, drive circuit, voltage sampling circuit and power stage circuit, the output of major loop control circuit connects time loop control circuit, the major loop control circuit also is connected with drive circuit is two-way, inferior loop control circuit output connects drive circuit, drive circuit output connects power stage circuit, power stage circuit output is connected with major loop control circuit and time loop control circuit respectively by voltage sampling circuit, power stage circuit output also connects the major loop control circuit, it is characterized in that: the secondary loop control circuit comprises the first voltage comparator and second voltage comparator, the positive input termination reference voltage of the first voltage comparator, negative input termination the first branch road sampled voltage signal, the anode input of second voltage comparator connects the second branch road sampled voltage signal, and the negative terminal input connects reference voltage;
A gating signal that is connected between secondary loop control circuit and the drive circuit is set produces and the selection circuit, comprise the narrow-pulse generation circuit, latch cicuit, selection circuit and the shaping circuit that connect successively; Wherein:
Narrow-pulse generation circuit is provided with first～the 66 NAND gate, 2 resistance R 1, R2,2 capacitor C 1, C2 and first, the 22 inverter, two inputs of the first NAND gate all connect the clock signal of oscillator in the major loop control circuit and are connected with an input of the second NAND gate, the end of the output contact resistance R1 of the first NAND gate, the other end of resistance R 1 connects an end of capacitor C 1 and another input of the second NAND gate, the other end ground connection of capacitor C 1, two inputs of the output of the second NAND gate and the 3rd NAND gate link together, and the output of the 3rd NAND gate connects the input of the first inverter; Two defeated duty cycle signals that all connect digital logic module output in the major loop control circuit of the 4th NAND gate, the end of the output contact resistance R2 of the 4th NAND gate, the other end of resistance R 2 connects an end of capacitor C 2 and an input of the 5th NAND gate, the other end ground connection of capacitor C 2, the duty cycle signals of digital logic module output in another input termination major loop control circuit of the 5th NAND gate, two inputs of the output of the 5th NAND gate and the 6th NAND gate link together, and the output of the 6th NAND gate connects the input of the second inverter;
Latch cicuit is provided with 2 the first d type flip flop and the second d type flip flop and three with asynchronous resetting function, the 4 two inverter, the data input pin of the input of the 3rd inverter and the second d type flip flop all connects the duty cycle signals of digital logic module output in the major loop control circuit, the input of the 4th inverter connects the output of the first comparator in the secondary loop control circuit, the data input pin of the first d type flip flop connects the output of the 3rd inverter, the input end of clock of the first d type flip flop connects the output of the second comparator in the secondary loop control circuit, the zero clearing input of the first d type flip flop connects the output of the first inverter in the narrow-pulse generation circuit, the input end of clock of the second d type flip flop connects the output of the 4th inverter, and the zero clearing input of the second d type flip flop connects the output of the second inverter in the narrow-pulse generation circuit;
Select circuit to be provided with first～the 44 alternative data selector, a data input of the first data selector connects the output of the second d type flip flop in the latch cicuit, first, the in-phase clock input of the second two data selectors all connects the duty cycle signals of digital logic module output in the major loop control circuit, first, the inversion clock input of the second two data selectors all connects the output of the 3rd inverter in the latch cicuit, first, the equal ground connection of another data input pin of the second two data selectors, a data input of the second data selector connects the output of the first d type flip flop in the latch cicuit, a data input of the 3rd data selector connects the output of the first data selector, the 3rd, the in-phase clock input of the 4 two data selector all connects the duty cycle signals of digital logic module output in the major loop control circuit, the 3rd, the inversion clock input of the 4 two data selector all connects the output of the 3rd inverter in the latch cicuit, the 3rd, the equal ground connection of another data input pin of the 4 two data selector, a data input of the 4th data selector connects the output of the second data selector.
Shaping circuit is provided with first, the second two NOR gate and the 5th, the 6 two inverter, the output of the 4th data selector in the circuit is selected in an input selecting of the first NOR gate, another input of the first NOR gate connects the output of selecting the first data selector in the circuit, the output of the first NOR gate connects the input of the 5th inverter, an input of the second NOR gate connects the output of selecting the 3rd data selector in the circuit, another input of the second NOR gate connects the output of selecting the second data selector in the circuit, the input of hex inverter connects the output of the second NOR gate, and the 5th, the output of the 6 two inverter produces the gating control signal of control time loop power tube switch.
Advantage of the present invention and remarkable result:
(1) the inferior loop control circuit that comprises two comparators formations and the gating signal generation that comprises the Digital Logical Circuits formation being set selects circuit to control inferior loop power tube, make the load current size of two-way output arbitrarily, in each switch periods, all send the control gating signal to two branch roads, and two gating signals are mutually anti-phase, so that two secondary switch rise and open respectively and turn-off once in the decline stage at inductive current, realize the stable output of two branch roads.In one-period, produce two gating signals, control respectively the turn-on and turn-off of the first branch power pipe and the second branch power pipe, overcome because single gating signal control simultaneously during two branch power pipes, can only be by the feedback signal of the large branch road of load current as the control major loop, thus another branch road load current that causes must be less than the shortcoming of this branch road load current.
(2) this control circuit is simple and easy to realize, the secondary loop that only needs two comparators of design to consist of, the strobe generation circuit that Digital Logic consists of, can realize above-mentioned functions, control method is simple and reliable, and circuit is easily realized, and it is little to improve the shared chip area of circuit.
Description of drawings
Fig. 1 is the electric theory diagram of prior art;
Fig. 2 is sequential and the inductive current figure of prior art;
Fig. 3 is electric theory diagram of the present invention;
Fig. 4 is a kind of specific implementation circuit of the present invention;
Fig. 5 is a kind of implementation that gating signal is selected circuit in the circuit of the present invention;
Fig. 6 is the control sequential chart (high level represents the power tube unlatching of signal controlling) of Fig. 4 circuit.
Embodiment
Such as Fig. 3, the present invention is provided with major loop control circuit 1, inferior loop control circuit 2, strobe generation circuit 3, drive circuit 4, voltage sampling circuit 5 and power stage circuit 6.Fig. 1 compares with prior art, major loop control circuit 1, drive circuit 4, voltage sampling circuit 5 and power stage circuit 6 are identical with the prior art structure, but inferior loop control circuit 2 unlike the prior art, and other has increased the strobe generation circuit 3 that is connected between time loop control circuit 2 and the drive circuit 4.
Such as Fig. 4, major loop control circuit 1 comprises reference voltage generating circuit, error comparator EA, oscillator and slope equalizer, peak current detection circuit and opposite current detection circuit, PWM modulator, current-limiting circuit, Digital Logic.The inverting input of major loop error amplifier EA connects the end of sampling resistor R5, R6, R7 in the sample circuit, and in-phase input end connects the output voltage of reference voltage generating circuit; The drain electrode of anode, major loop power tube Mp1 and the Mp2 of an input termination inductance L X of opposite current detection circuit, another input end grounding; The drain electrode of anode, major loop power tube Mp1 and the Mp2 of the input termination inductance L X of current detection circuit; The input of slope equalizer connects the output of oscillator; The output of the anti-phase input termination major loop error amplifier EA of PWM modulator, in-phase input end connects the output of slope equalizer, current detection circuit; The output of the input termination PWM modulator of Digital Logical Circuits, current detection circuit, slope equalizer, oscillator, the output of Digital Logical Circuits produce control signal SN, the SP of control major loop power tube switch.
The grid of major loop the first power tube Mp1 connects the duty ratio that major loop produces and drives signal PD, and the source electrode of Mp1 meets input supply voltage Vin, the drain electrode that the drain electrode of Mp1 meets the anode of inductance L X and major loop the second power tube Mn1 in.The grid of major loop the second power tube Mp2 connects the duty ratio driving signal ND that major loop produces, the source ground of Mn1.The negative terminal of inductance L X connects the source electrode of branch power pipe Mp2 and Mp3, branch power pipe Mp2 is connected grid and is connected respectively the gating that the gating secondary drive circuit produces and drive signal D1 and D2 with Mp3, branch power pipe Mp2 is connected drain electrode and is connected respectively the end of sampling resistor R1, the R2 of the end of anode, load resistance Ro1 and Ro2 of branch road output filter capacitor C1 and C2 and sample circuit with Mp3.The other end of the sampling resistor R1 of sample circuit connects respectively the end of sampling resistor R3, the inverting input of branch road comparator C MP1.The other end of the sampling resistor R2 of sample circuit connects respectively the in-phase input end of sampling resistor R4, branch road comparator C MP2.The other end ground connection of sampling resistor R3, R4.The in-phase input end of the in-phase input end of branch road comparator C MP1, the inverting input of CMP2, error amplifier and the output of reference voltage connect.The output of branch road comparator C MP1 selects circuit to be connected with gating signal.The output of branch road comparator C MP2 selects circuit to be connected with gating signal.The output of oscillator selects circuit, Digital Logical Circuits to be connected with harmonic compensation circuit, gating signal.
Drive circuit 4 comprises driving and dead band control circuit, is the circuit structure of maturation, and its internal structure does not repeat them here.Output signal S1, S2 that output signal SN, the SP that the input termination major loop control circuit of this circuit produces and inferior loop control circuit produce; The output of drive circuit produces driving signal PD, the ND of driving major loop power tube switch and driving signal D1, the D2 of control time loop power tube switch.
Power stage circuit 6 comprises the circuit of synchronous rectification that the first power tube Mp1 and the second power tube Mn1 consist of, inductance L X, and branch power pipe Mp2 and Mp3.The grid of the first power tube Mp1 meets the duty ratio driving signal PD that major loop produces, and the source electrode of Mp1 meets input supply voltage Vin; The grid of the second power tube Mn1 connects the duty ratio driving signal ND that major loop produces, the source ground of Mn1; Branch power pipe Mp2 is connected grid and is connected respectively the gating that the gating secondary drive circuit produces and drive signal D1 and D2 with Mp3, branch power pipe Mp2 is connected drain electrode and is connected respectively the end of sampling resistor R1, the R2 of the end of anode, load resistance Ro1 and Ro2 of branch road output filter capacitor C1 and C2 and sample circuit with Mp3, the drain electrode of positive termination the first power tube Mp1 of inductance L X, the drain electrode of the second power tube Mn1, the negative terminal of inductance L X connects the source electrode of branch power pipe Mp2 and Mp3.
Voltage sampling circuit 5 comprises sampling resistor R1, R2, R3, R4, R5, R6, R7, annexation is as follows: the end of sampling resistor R1, R2 connects respectively the end of anode, load resistance Ro1 and Ro2 of drain electrode, branch road output filter capacitor C1 and the C2 of branch power pipe Mp2 and Mp3, and the other end of sampling resistor R1 connects respectively the end of sampling resistor R3, the inverting input of branch road comparator C MP1.The other end of the sampling resistor R2 of sample circuit connects respectively the in-phase input end of sampling resistor R4, branch road comparator C MP2.The other end ground connection of sampling resistor R3, R4, the end of sampling resistor R5, R6, R7 connects the inverting input of major loop error amplifier EA, another termination first branch road output voltage of R5, another termination second branch road output voltage of R6, the other end ground connection of R7.
Foregoing circuit is the control loop of typical peak-current mode, is mature technology.
Secondary loop control circuit 2 comprises the first branch voltage comparator C MP1 and the second branch road comparator C MP2.The positive input termination reference voltage V ref of CMP1 wherein, negative input termination the first branch road sampled voltage signal Vo1 when the output voltage VO UT1 of the first branch road surpasses set point, exports a trailing edge signal Vcmp1.The anode input of CMP2 meets the second branch road sampled voltage signal Vo2, and the negative terminal input meets reference voltage signal Vref, when the output voltage VO UT2 of the second branch road surpasses set point, exports a rising edge signal Vcmp2.
Referring to Fig. 5, gating signal selects circuit 3 to produce input duty cycle signal S1 and the S2 of one group of driver module.Gating signal selects circuit 3 to comprise narrow-pulse generation circuit 7, and latch cicuit 8 is selected circuit 9 and shaping circuit 10, and narrow-pulse generation circuit 7 is by NAND gate nand2, resistance R 1, R2 and capacitor C 1, C2, inverter 1, inverter 2.The shaping circuit that NAND gate nand2 and inverter consist of produces one group of narrow pulse signal CLK_pulse and SP_pulse.Latch cicuit 8 is made of two effective 2 d type flip flops of rising edge with asynchronous resetting function, latch the trailing edge of Vcmp1 and the rising edge of Vcmp2, avoid because comparator C MP1 and CMP2 relatively form interference to the switch of branch power pipe because of the mistake that noise etc. reason causes.Select circuit 9 to be consisted of by 4 alternative data selector MUX1 to MUX4, when wherein MUX1 and MUX2 are created in respectively major loop the first power tube Mp1 and major loop the second power tube Mn1 conducting, gating control signal S1_PD and the S1_ND of the first branch power pipe Mp2, when MUX3 and MUX4 are created in respectively major loop the first power tube Mp1 and major loop the second power tube Mn1 conducting, gating control signal S2_PD and the S2_ND of the second branch power pipe Mp3.Shaping circuit 10 is with gating control signal Si_PD and the Si_ND(i=1,2 of segmentation) be combined into smooth continuous gating control signal Si(i=1,2).Voltage sampling circuit 5 is in series by the resistance of the different resistances of three groups of groups, chooses suitable resistance, so that sampled voltage Vo1, the Vo2 of three sample circuits and K * (Vo1+Vo2) can compare with same reference voltage V ref.Gating signal selects output signal S1, the S2 of circuit to be connected respectively with the input of drive circuit.
An input of narrow-pulse generation circuit 7 connects the CLK signal, the data input pin of d type flip flop DFF1 in another input of the input of narrow-pulse generation circuit, the latch cicuit 8, select circuit MUXi(i=1,2,3,4) the data-signal input connect, connect the SP signal, the SP signal after anti-phase, connect d type flip flop DFF2 in the latch cicuit data input pin, select circuit MUXi(i=1,2,3,4) the inversion clock signal input part.Two outputs of narrow pulse generator are connected respectively the data clear terminal of two d type flip flop DFF1, DFF2 and are connected with latch cicuit.The data input pin of d type flip flop DFF1 is connected the inversion signal of output signal Vcmp1 and is connected in the latch cicuit with branch road comparator C MP1, and the data input pin of d type flip flop DFF2 is connected output and is connected in the latch cicuit with branch road comparator C MP2.Output Q1, the Q2 of d type flip flop DFF2, DFF1 connect with the first data input pin (S1) of being connected circuit MUX1, MUX2 respectively in the latch cicuit.The output MO1 of MUX1 is connected the input of the first data input pin (S1), shaping circuit and is connected with MUX3.The output MO2 of MUX2 is connected the input of the first data input pin (S2), shaping circuit and is connected with MUX4.MUXi(i=1,2,3,4) the second input (S2) is ground connection all.The output MO3 of MUX3 is connected input and is connected with shaping circuit, the output MO4 of MUX4 is connected input and is connected with combinational circuit.
The operation principle of circuit of the present invention: the primary and secondary loop control method that adopts time-sharing multiplex, output at each output branch road arranges the timesharing actuating switch, a clock cycle is divided into a plurality of unit, in each clock cycle division unit, separately one tunnel output is controlled.Setting comprises that two comparators inferior loop that consists of and the gating signal that comprises the Digital Logical Circuits formation produce the selection circuit and control time loop power tube, make the load current size of two-way output arbitrarily, in each switch periods, all send the control gating signal to two branch roads, and two gating signals are mutually anti-phase, so that two secondary switch rise and distinguish switch once in the decline stage at inductive current, each cycle is when beginning, open major loop power tube and the second branch power pipe by clock signal, first and second output voltages of exporting branch roads of sampling respectively send into afterwards error amplifier and reference voltage compares, produce the first negative-feedback signal, select the first negative-feedback signal to compare with triangular signal and sensed current signal, produce the driving signal of control major loop power tube switch; The output voltage of the second branch road of sampling is sent into the first comparator and reference voltage relatively, produces the second negative-feedback signal; The sample output voltage of the first branch road is sent into the second comparator and reference voltage relatively, produces the 3rd negative-feedback signal; When the second negative-feedback signal is higher than reference voltage, produce high level signal, be used for turn-offing the second branch power pipe and open the first branch power pipe; When the 3rd negative-feedback signal is higher than reference voltage, produce high level signal, be used for turn-offing the first branch power pipe and open the second branch power pipe.
The charging of (1) second branch road:, each cycle is when beginning, clock signal of system CLK opens major loop the first power tube Mp1, CLK will open the second branch power pipe Mp2 simultaneously through the burst pulse that narrow-pulse generation circuit produces simultaneously, input voltage vin provides energy to the second output branch road, until rising to the sampled voltage Vo2 of the second branch road, the output voltage of the second branch road is higher than reference voltage V ref, secondary control loop will produce the voltage signal Vcmp2 of a rising edge, the second branch power pipe Mp3 is turn-offed, and the second branch road charging process finishes.
The charging of (2) first branch roads and afterflow: secondary control loop produces the voltage signal Vcmp2 of a rising edge, when the second branch power pipe Mp3 turn-offs, the Vcmp2 of this rising edge also opens the first branch power pipe Mp2 simultaneously, input voltage vin provides energy for the first branch road, the first branch road output voltage rises, until peak electricity flow pattern major loop turn-offs major loop the first power tube Mp1, and open major loop the second power tube Mp2.The major loop charging process finishes, and inductance enters the afterflow stage.At this moment, inductive current flow through first output branch road, the first output branch road afterflow, the first branch road output voltage continues to rise, until the sampled voltage Vo1 of the first branch road is higher than reference voltage V ref, produce the Vcmp1 signal of a trailing edge, the first branch power pipe Mp2 is turn-offed, the first branch road charging process finishes;
(3) second branch road afterflows: the Vcmp1 signal of trailing edge, when the first branch power pipe Mp2 is turn-offed, open the second branch power pipe Mp3, inductive current is through the second branch power pipe Mp3 afterflow, until a switch periods finishes;
The process of (1)～(3) above repeating, the like this work that goes round and begins again of completing circuit.
In each switch periods, all send the control gating signals to two branch roads, and two gating signals are mutually anti-phase, so that two secondary switch rise and distinguish switch once in the decline stage at inductive current;
Operating process in complete switch periods is as follows;
Each cycle is opened main circuit power pipe and the second branch power pipe by clock signal when beginning;
The output voltages of sampling the first and second output branch roads are that K * (Vo1+Vo2) sends into error amplifier afterwards, compare with reference voltage, produce the first negative-feedback signal, select the first negative-feedback signal, compare with triangular signal and sensed current signal, produce the driving signal of control main power tube switch;
The sample output voltage of the second branch road is sent into comparator one, with reference voltage relatively, produce the second negative-feedback signal;
The sample output voltage of the first branch road is sent into comparator two, and reference voltage relatively produces the 3rd negative-feedback signal;
When the second negative-feedback signal is higher than reference voltage, produce high level signal, be used for turn-offing the second branch power pipe and open the first branch power pipe;
When the 3rd negative-feedback signal is higher than reference voltage, produce high level signal, be used for turn-offing the first branch power pipe and open the second branch power pipe.
Major loop control circuit 1, the circuit of drive circuit 4 and power stage 6 circuit consists of and working method can be with reference to prior art, skip over herein and do not show, below will mainly describe main body circuit of the present invention and the course of work, be i.e. formation and the course of work of secondary loop and branch road strobe generation circuit.
Realize the based on the comparison device control of secondary loop control circuit 2 of the switch converters of above-mentioned control mode, positive input terminal connects the first branch road sampled voltage, negative terminal connects the first branch voltage comparator of reference voltage, positive input terminal connects the second branch road sampled voltage, negative terminal connects the second branch voltage comparator of reference voltage, and output Vcmp1, the Vcmp2 of two comparators connects strobe generation circuit circuit 3.
Produced gating signal S1, the S2 of control branch power pipe switch by strobe generation circuit 3, these two signals drive driving signal D1, the D2 of branch power pipe Mp2, Mp3 by driver module 4 rear generations;
Sample circuit 5 passes through electric resistance partial pressure, produce one group can with relatively sampled voltage K of reference voltage * (Vo1+Vo2) (K＜1), Vo1, Vo2, by selecting different resistance, make sampled voltage K * (Vo1+Vo2), Vo1, Vo2 can with same reference voltage V ref relatively, make whole switch converters only use a reference voltage, save the area of reference voltage generating circuit;
Inferior loop control circuit 2 compares sampled voltage Vo2 and reference voltage V ref, when the sampled voltage Vo2 of the second branch road is lower than reference voltage V ref, the Vcmp2 of the second branch voltage comparator C MP2 output low level, when the sampled voltage Vo2 of the second branch road is higher than reference voltage V ref, the Vcmp2 of the second branch voltage comparator C MP2 output high level;
Inferior loop control circuit 2 compares sampled voltage Vo1 and reference voltage V ref, when the sampled voltage Vo1 of the first branch road is lower than reference voltage V ref, the Vcmp1 of the first branch voltage comparator C MP1 output high level, when the sampled voltage Vo1 of the first branch road is higher than reference voltage V ref, the Vcmp1 of the first branch voltage comparator C MP1 output low level;
Gating signal selects circuit 3 output signal of comparator to be latched and produces the gating signal of one group of control branch power pipe turn-on and turn-off: when major loop the first power tube Mp1 conducting and Vcmp2 are high level by low transition, produce a triggering signal, this triggering signal is closed the second branch power pipe Mp3 and is opened simultaneously the first branch power pipe Mp2; After major loop the second power tube Mn1 conducting and Vcmp1 are low level by the high level saltus step, produce a triggering signal, this signal at stop the first branch power pipe Mp2 also opens the second branch power pipe Mp3 simultaneously.Like this, in a switch periods, there are two signal S1 and S2 to control the first branch power pipe and the second branch power pipe;
Referring to Fig. 6, with the sequential of prior art as seen, this programme is in one-period, the gating signal S1 that produces and S2 can so that the first branch power pipe and the second branch power pipe within each clock cycle, in induction charging process and the inductive discharge process, all open and turn-off once, thereby avoided the current limit of particular branches.
Claims (1)
1. the control method of a single inductance dual-output DC-DC Switching Power Supply, integrated two DC-DC converters in chip piece, produce the output of two kinds of voltages, two output branch roads share an inductance, adopt the primary and secondary loop control method of time-sharing multiplex, at each output of exporting branch road the timesharing actuating switch is set, a clock cycle is divided into a plurality of unit, in each clock cycle division unit, separately one tunnel output is controlled; Be provided with major loop control circuit, inferior loop control circuit, drive circuit, voltage sampling circuit and power stage circuit; Setting comprises that two comparators inferior loop control circuit that consists of and the gating signal that comprises the Digital Logical Circuits formation produce the selection circuit and control time loop power tube, make the load current size of two-way output arbitrarily, in each switch periods, all send the control gating signal to two branch roads, and two gating signals are mutually anti-phase, so that two time loop power tubes rise and open respectively and turn-off once in the decline stage at inductive current, realize the stable output of two branch roads; It is characterized in that:
The output of major loop control circuit connects time loop control circuit, the major loop control circuit also is connected with drive circuit is two-way, inferior loop control circuit output connects drive circuit, drive circuit output connects power stage circuit, power stage circuit output is connected with major loop control circuit and time loop control circuit respectively by voltage sampling circuit, power stage circuit output also connects the major loop control circuit, inferior loop control circuit comprises the first voltage comparator and second voltage comparator, the positive input termination reference voltage of the first voltage comparator, negative input termination the first branch road sampled voltage signal, the anode input of second voltage comparator connects the second branch road sampled voltage signal, and the negative terminal input connects reference voltage;
A gating signal that is connected between time loop control circuit and the drive circuit is set produces the selection circuit, comprise the narrow-pulse generation circuit, latch cicuit, selection circuit and the shaping circuit that connect successively; Wherein:
Narrow-pulse generation circuit is provided with first～the 66 NAND gate, 2 resistance R 1, R2,2 capacitor C 1, C2 and first, the 22 inverter, two inputs of the first NAND gate all connect the clock signal of oscillator in the major loop control circuit and are connected with an input of the second NAND gate, the end of the output contact resistance R1 of the first NAND gate, the other end of resistance R 1 connects an end of capacitor C 1 and another input of the second NAND gate, the other end ground connection of capacitor C 1, two inputs of the output of the second NAND gate and the 3rd NAND gate link together, and the output of the 3rd NAND gate connects the input of the first inverter; Two inputs of the 4th NAND gate all connect the duty cycle signals of digital logic module output in the major loop control circuit, the end of the output contact resistance R2 of the 4th NAND gate, the other end of resistance R 2 connects an end of capacitor C 2 and an input of the 5th NAND gate, the other end ground connection of capacitor C 2, the duty cycle signals of digital logic module output in another input termination major loop control circuit of the 5th NAND gate, two inputs of the output of the 5th NAND gate and the 6th NAND gate link together, and the output of the 6th NAND gate connects the input of the second inverter;
Latch cicuit is provided with 2 the first d type flip flop and the second d type flip flop and three with asynchronous resetting function, the 4 two inverter, the data input pin of the input of the 3rd inverter and the second d type flip flop all connects the duty cycle signals of digital logic module output in the major loop control circuit, the input of the 4th inverter connects the output of the first voltage comparator in time loop control circuit, the data input pin of the first d type flip flop connects the output of the 3rd inverter, the input end of clock of the first d type flip flop connects the output of second voltage comparator in time loop control circuit, the zero clearing input of the first d type flip flop connects the output of the first inverter in the narrow-pulse generation circuit, the input end of clock of the second d type flip flop connects the output of the 4th inverter, and the zero clearing input of the second d type flip flop connects the output of the second inverter in the narrow-pulse generation circuit;
Select circuit to be provided with first～the 44 alternative data selector, a data input of the first data selector connects the output of the second d type flip flop in the latch cicuit, first, the in-phase clock input of the second two data selectors all connects the duty cycle signals of digital logic module output in the major loop control circuit, first, the inversion clock input of the second two data selectors all connects the output of the 3rd inverter in the latch cicuit, first, the equal ground connection of another data input pin of the second two data selectors, a data input of the second data selector connects the output of the first d type flip flop in the latch cicuit, a data input of the 3rd data selector connects the output of the first data selector, the 3rd, the in-phase clock input of the 4 two data selector all connects the duty cycle signals of digital logic module output in the major loop control circuit, the 3rd, the inversion clock input of the 4 two data selector all connects the output of the 3rd inverter in the latch cicuit, the 3rd, the equal ground connection of another data input pin of the 4 two data selector, a data input of the 4th data selector connects the output of the second data selector;
Shaping circuit is provided with first, the second two NOR gate and the 5th, the 6 two inverter, the output of the 4th data selector in the circuit is selected in an input selecting of the first NOR gate, another input of the first NOR gate connects the output of selecting the first data selector in the circuit, the output of the first NOR gate connects the input of the 5th inverter, an input of the second NOR gate connects the output of selecting the 3rd data selector in the circuit, another input of the second NOR gate connects the output of selecting the second data selector in the circuit, the input of hex inverter connects the output of the second NOR gate, and the 5th, the output of the 6 two inverter produces the control gating signal of control time loop power tube switch.
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| CN102820781B (en) * | 2012-08-30 | 2014-08-06 | 东南大学 | Single-inductance double-output switch power supply based on ripple control |
| CN103618455B (en) * | 2013-12-10 | 2016-02-03 | 东南大学 | Reduce method and circuit thereof that single inductance dual-output converter exports steady-state error |
| CN103701307B (en) * | 2013-12-31 | 2016-03-30 | 成都芯源系统有限公司 | Single-inductor multi-output buck converter and control circuit and control method thereof |
| CN105763174B (en) * | 2014-12-17 | 2019-03-12 | 联芯科技有限公司 | Adaptive multiphased triangular wave module, production method and enabled/forbidden energy method |
| CN105763047B (en) * | 2016-03-08 | 2018-11-02 | 中山大学 | A kind of all-wave inductive current sample circuit |
| CN107666241A (en) * | 2016-07-30 | 2018-02-06 | 智瑞佳（苏州）半导体科技有限公司 | A kind of digital DC D/C powers conversion chip and its control method |
| CN108183611B (en) * | 2017-12-26 | 2019-12-06 | 成都芯源系统有限公司 | control device and method of bidirectional switch circuit |
| TWI692926B (en) * | 2018-05-21 | 2020-05-01 | 瑞鼎科技股份有限公司 | Time multiplexing circuit applied to dc-dc converting system |
| CN109474171A (en) * | 2018-12-27 | 2019-03-15 | 北京集创北方科技股份有限公司 | Control circuit and power management chip |
| US11128219B1 (en) * | 2020-05-25 | 2021-09-21 | Novatek Microelectronics Corp. | Control circuit for voltage generator |
| CN112965130B (en) * | 2021-01-25 | 2022-11-08 | 江西瑞晟光电科技有限公司 | Device and method for detecting impurities on surface of wafer |
| CN113472368B (en) * | 2021-06-30 | 2022-04-22 | 杭州电子科技大学 | Multi-frequency-point maximum power control circuit of transmitting coil |
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| US8975879B2 (en) * | 2009-09-14 | 2015-03-10 | Dialog Semiconductor Gmbh | Switching converter having a plurality N of outputs providing N output signals and at least one inductor and method for controlling such a switching converter |
| CN102055322A (en) * | 2009-11-03 | 2011-05-11 | 立锜科技股份有限公司 | Single-inductor multi-output power converter and control method thereof |
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