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Publication numberCN102324845 A
Publication typeApplication
Application numberCN 201110285931
Publication date18 Jan 2012
Filing date23 Sep 2011
Priority date23 Sep 2011
Also published asCN102324845B
Publication number201110285931.7, CN 102324845 A, CN 102324845A, CN 201110285931, CN-A-102324845, CN102324845 A, CN102324845A, CN201110285931, CN201110285931.7
Inventors孙伟锋, 徐申, 时龙兴, 李牧, 杨淼, 葛芳莉, 陆晓霞, 陆生礼
Applicant东南大学
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Control method for single-inductance double-output DC-DC (direct current) switching power supply and circuit thereof
CN 102324845 A
Abstract
The invention relates to a control method for a single-inductance double-output DC-DC (direct current) switching power supply and a circuit thereof. Two DC-DC converters are integrated in one chip to generate outputs of two voltages. Two output branches share one inductance. A time sharing multiplex primary and secondary loop control method is adopted. A time sharing conduction switch is arrangedat an output end of each output branch. One clock period is divided into a plurality of units. In each divided unit of the clock period, one path of output is independently controlled. The control method is characterized in that a secondary loop which comprises two comparators and a gating signal generation selection circuit which comprises a digital logic circuit are arranged to control a secondary loop power tube, so that the sizes of load currents of two paths of outputs are random; and in each switching period, control gating signals are sent to the two branches and the two gating signalshave opposite phases, so that two secondary switches are respectively turned on and turned off for once in the ascending and descending stages of an inductive current, and thus, the stable outputs ofthe two branches are realized.
Claims(2)  translated from Chinese
1. 一种单电感双输出DC-DC开关电源的控制方法,在一块芯片中集成两个DC-DC变换器,产生两种电压的输出,两输出支路共用一个电感,采用分时复用的主、次环路控制方法, 在每个输出支路的输出端设置分时导通开关,将一个时钟周期划分为多个单元,在每一时钟周期划分单元中,单独对一路输出进行控制;设有主环路控制电路、次环路控制电路、驱动电路、电压采样电路及功率级电路,其特征在于:设置包括两个比较器构成的次环路控制电路和包括数字逻辑电路构成的选通信号产生选择电路来控制次环路功率管,使两路输出的负载电流大小任意,每个开关周期内,均向两个支路发送控制选通信号,且两个选通信号相互反相,使得两个次级开关在电感电流上升和下降阶段内分别开启和关断一次,实现两支路的稳定输出。 1. A method for controlling a single inductor dual-output DC-DC switching power supply, integrated in a single chip DC-DC converter in two, producing two voltage outputs, the two share an inductive output branch, using time division multiplexing primary, secondary loop control method, time-setting switch is turned on at an output terminal of each output branch, one clock period is divided into a plurality of units, in the division unit in each clock cycle, one output is controlled separately ; provided with a main control loop circuit, the secondary loop control circuit, the driving circuit, a voltage sampling circuit and power stage, characterized by: setting comprises two comparators constituting the secondary loop control circuit and includes a digital logic circuit comprising strobe selection circuit to control the second generation loop power control, so that the two output load current size of any, within each switching cycle, the two branches are to send control strobe, strobe and two mutually opposite phase, so that two secondary switches are turned on and off once, to achieve a stable output in the two branches of the inductor current rise and fall phase.
2. 一种实现权利要求1所述单电感双输出DC-DC开关电源的控制方法的电路,设有主环路控制电路、次环路控制电路、驱动电路、电压采样电路及功率级电路,主环路控制电路输出连接次环路控制电路,主环路控制电路还与驱动电路双向连接,次环路控制电路输出连接驱动电路,驱动电路输出连接功率级电路,功率级电路输出通过电压采样电路分别与主环路控制电路及次环路控制电路连接,功率级电路输出还连接主环路控制电路,其特征在于:次级环路控制电路包括第一电压比较器和第二电压比较器,第一电压比较器的正输入端接基准电压,负输入端接第一支路采样电压信号,第二电压比较器的正端输入接第二支路采样电压信号,负端输入接基准电压;设置一个连接于次级环路控制电路和驱动电路之间的选通信号产生及选择电路,包括依次连接的窄脉冲产生电路、锁存电路、选择电路及整形电路;其中:窄脉冲产生电路设有第一〜第六6个与非门、2个电阻Rl、R2、2个电容Cl、C2以及第一、第二2个反相器,第一与非门的两个输入端均连接主环路控制电路中振荡器的输出时钟信号并与第二与非门的一个输入端连接,第一与非门的输出端连接电阻Rl的一端,电阻Rl的另一端连接电容Cl的一端及第二与非门的另一个输入端,电容Cl的另一端接地,第二与非门的输出端与第三与非门的两个输入端连接在一起,第三与非门的输出端连接第一反相器的输入端;第四与非门的两个输均连接主环路控制电路中数字逻辑模块输出的占空比信号,第四与非门的输出端连接电阻R2的一端,电阻R2的另一端连接电容C2的一端及第五与非门的一个输入端,电容C2的另一端接地,第五与非门的另一个输入端接主环路控制电路中数字逻辑模块输出的占空比信号,第五与非门的输出端与第六与非门的两个输入端连接在一起,第六与非门的输出端连接第二反相器的输入端;锁存电路设有2个具有异步清零功能的第一D触发器和第二D触发器以及第三、第四两个反相器,第三反相器的输入端及第二D触发器的数据输入端均连接主环路控制电路中数字逻辑模块输出的占空比信号,第四反相器的输入端连接次级环路控制电路中第一比较器的输出端,第一D触发器的数据输入端连接第三反相器的输出端,第一D触发器的时钟输入端连接次级环路控制电路中第二比较器的输出端,第一D触发器的清零输入端连接窄脉冲产生电路中第一反相器的输出端,第二D触发器的时钟输入端连接第四反相器的输出端,第二D触发器的清零输入端连接窄脉冲产生电路中第二反相器的输出端;选择电路设有第一〜第四4个二选一数据选择器,第一数据选择器的一个数据输入端连接锁存电路中第二D触发器的输出端,第一、第二两个数据选择器的同相时钟输入端均连接主环路控制电路中数字逻辑模块输出的占空比信号,第一、第二两个数据选择器的反相时钟输入端均连接锁存电路中第三反相器的输出端,第一、第二两个数据选择器的另一个数据输入端均接地,第二数据选择器的一个数据输入端连接锁存电路中第一D触发器的输出端,第三数据选择器的一个数据输入端连接第一数据选择器的输出端,第三、第四两个数据选择器的同相时钟输入端均连接主环路控制电路中数字逻辑模块输出的占空比信号, 第三、第四两个数据选择器的反相时钟输入端均连接锁存电路中第三反相器的输出端,第三、第四两个数据选择器的另一个数据输入端均接地,第四数据选择器的一个数据输入端连接第二数据选择器的输出端;整形电路设有第一、第二两个或非门和第五、第六两个反相器,第一或非门的一个输入端接选择电路中第四数据选择器的输出端,第一或非门的另一个输入端连接选择电路中第一数据选择器的输出端,第一或非门的输出端连接第五反相器的输入端,第二或非门的一个输入端连接选择电路中第三数据选择器的输出端,第二或非门的另一个输入端连接选择电路中第二数据选择器的输出端,第六反相器的输入端连接第二或非门的输出端,第五、第六两个反相器的输出端产生控制次环路功率管开关的选通控制信号。 2. A method for controlling the realization of the circuit a single inductor dual-output DC-DC switching power supply of claim with the main loop control circuit, the second loop control circuit, driver circuit, voltage sampling circuit and power stage, Main loop control circuit outputs a control circuit connected to the secondary loop, the main loop control circuit further bi-directionally connected with the driving circuit, the output of the secondary loop control circuit connected to the drive circuit, the drive circuit output connected to a power stage circuit, the power output stage circuit through the voltage sampling respectively with the main circuit and the secondary loop control circuit connected to the loop control circuit, the power output stage circuit is also connected to the main control loop circuit, characterized in that: the secondary loop control circuit comprises a first voltage comparator and a second voltage comparator , the first voltage comparator positive input termination reference voltage, the negative input terminal of the first branch sampled voltage signal, the positive terminal of the second voltage comparator input connected to the second branch sampled voltage signal, a negative input terminal connected to the reference voltage ; set up a connection to the secondary loop control gate signal generating circuit and the driving circuit and between the selection circuit comprises a narrow pulse generating circuit connected in sequence, the latch circuit, the selection circuit and the shaping circuit; wherein: the narrow pulse generating circuit 6 is provided with first to sixth NAND gates, two resistors Rl, R2,2 capacitors Cl, C2 and the first and second two inverters, a first NAND gate with two inputs are connected main loop control circuit oscillator output clock signal and connected to an input of a second NAND gate, the output of the first NAND gate connected to one end of the resistor Rl, and the other end connected to one end of the resistor Rl and capacitor Cl Another input of the second NAND gate, the other end of the capacitor Cl, and connected to the output terminal of the second NAND gate and a third NAND gate with two input terminals, connected to the output terminal of the third NAND gate input of the first inverter; fourth NAND gate with two inputs are connected to the main loop of the control circuit duty cycle signal output of the digital logic module, the fourth end of the resistor R2 is connected to the output terminal of the NAND gate, the other end of the resistor R2 is connected one end of the capacitor C2 and the fifth NAND gate one input terminal, the other end of the capacitor C2, and the other input connected to the fifth main control loop of the NAND gate circuit outputs a digital logic module duty cycle signal, connected to the output terminal of the fifth and sixth NAND gate with two inputs of the NAND gate together, a sixth input of the second inverter connected to the output terminal of the NAND gate; latch circuit is provided There are two asynchronous clear function of the first D flip-flop and a second D flip-flop, and a third, a fourth two inverters, the data input of the input of the third inverter and a second D flip-flop are connected to the main loop of the control circuit duty cycle signal output of the digital logic module, the input of the fourth inverter circuit connected to the secondary loop control output of the first comparator, a first D flip-flop data input end of the third inverter connected to the output of the clock input of the first D flip-flop circuit connected to the secondary loop control output of the second comparator, the clear input of the first D flip-flop is connected narrow pulse generated circuit output of the first inverter, a clock input of the second D flip-flop connected to the output terminal of the fourth inverter, the clear input of the second D flip-flop is connected a short pulse generation circuit of the second inverter the output device; selection circuit has first to fourth four second election data selector, a first data selector connected to a data input terminal of the latch circuit in the output of the second D flip-flop, a first, with the phase clock input of the second two data selectors are connected to the main loop control circuit duty cycle signal output of the digital logic module, the inverted clock input of the first, second two data selectors are connected to the latch circuit, the output of the third inverter, first, the other two data input of the second data selector are grounded, the second data selector connected to a data input terminal of the first D flip-flop latch circuit with the phase clock input terminal of a data input terminal with the output terminal, the third data selector connects the first output terminal of the data selector, the third, fourth two data selectors are connected to the main control loop digital logic circuit modules duty cycle signal output of the third, fourth two data selectors are connected to an inverted clock input terminal of the latch circuit in the output of the third inverter, a third, a fourth data selector of the other two a data input terminal grounded, a data input terminal connected to the fourth data selector output terminal of the second data selector; shaping circuit provided with a first, a second two NOR gates and fifth, sixth two anti- phase detector, an input terminal of the first NOR gate selection circuit to select the output of the fourth data terminal, the other input of the first NOR gate is connected to a first selection circuit in the output of the data selector, a first the output of the NOR gate is connected a fifth input terminal of the inverter, an input of the second NOR gate is connected to select the output of the third data selector circuit, the other input of the second NOR gate is connected to select second data selector circuit output terminal, the input terminal of the sixth inverter connected to an output terminal of the second NOR gate, the fifth, the sixth output terminal of the inverter generates two sub-loop power control switch tube gating control signal.
Description  translated from Chinese

单电感双输出DC-DC开关电源的控制方法及其电路 Single Inductor Dual Output DC-DC switching power supply control method and circuit

技术领域 FIELD

[0001] 本发明涉及电源转换器,特别涉及在集成电路内部的一种单电感双输出DC-DC开关电源的控制方法及其电路,属于微电子技术领域。 [0001] The present invention relates to a power converter, and more particularly in the integrated circuit inside a single inductor dual-output DC-DC switching power supply control method and circuit belongs to the field of microelectronics.

背景技术 BACKGROUND

[0002] 在现代集成电路领域中,为了降低功耗同时保持集成电路的性能,多电压供电成为主流趋势,能够提供两路(及多路)不同电压的单电感双(多)路电压输出DC-DC转换芯片应运而生。 [0002] In modern integrated circuits, in order to reduce power consumption while maintaining the performance of integrated circuits, multi-voltage power supply become a mainstream trend, providing two-way (and multiple) different voltage single inductor dual (more) DC voltage outputs -DC converter chip emerged. 传统单电感双路电压输出的DC-DC转换器,控制方法多样,其中峰值电流型单电感双输出DC-DC因其具有较高的转化效率和较小的电压纹波,从而成为研究的热点,现有的控制电路(图1)是主环路为传统的工作于连续电流模式(CCM)的峰值电流模式,而次环路的控制仍然为工作于连续电流模式(CCM)的峰值电流模式。 Traditional single inductor dual voltage output DC-DC converters, control methods varied, including single-inductor peak current dual-output DC-DC because hotspots with high conversion efficiency and smaller voltage ripple, making research , conventional control circuit (FIG. 1) is the main loop for the traditional operating in continuous current mode (CCM) of the peak current mode, while the second control loop is still operating in continuous current mode (CCM) of the peak current mode . 该控制方式有一个缺陷:如图2所示,由于只用一个比较器来控制次环路,所以只能在电感上升时间段内产生一个次级环路控制信号,来控制两个次环路功率管,致使两路输出的负载电流范围受限。 The control method has a flaw: shown in Figure 2, because of only one comparator to control the secondary loop, the rise in the inductance period so only one secondary loop generates a control signal to control the two secondary loops power tube, resulting in two output load current range is limited. 具体表现为一路的负载电流必须低于另外一路的负载电流,(在图2所示的例子中为第一支路的负载电流小于第二支路的负载电流)否则,单电感双路输出DC-DC转换器系统会产生振荡,引起大于常态的输出电压纹波。 Specific performance all the way to the load current must be less than another way of load current (in the example shown in Figure 2, the first branch of the load current is less than the second branch of the load current) Otherwise, single inductor dual output DC -DC converter system will oscillate, causing higher than normal output voltage ripple.

发明内容 SUMMARY

[0003] 本发明在现有技术的基础上,提供一种单电感双输出DC-DC开关变换器的控制方法及其电路,采用与现有技术相同的主环路控制模式,加入和改良了由两个比较器构成的次环路和由数字逻辑电路构成的选通信号产生选择电路来控制次环路功率管,可以使两路输出的负载电流大小任意,不受上述限制,同时单电感双输出DC-DC转换器仍然保持稳定。 [0003] The present invention is based on existing technology, to provide a single inductor dual-output DC-DC switching converter control method and circuit, using the same prior art main loop control mode, added and improved by the second loop and strobe by digital logic circuits consisting of two comparators produce selection circuit to control the second loop power control, you can make two output load current size of any, subject to the above restrictions, while single-inductor Dual Output DC-DC converter remains stable.

[0004] 本发明的技术方案是:一种单电感双输出DC-DC开关电源的控制方法,在一块芯片中集成两个DC-DC变换器,产生两种电压的输出,两输出支路共用一个电感,采用分时复用的主、次环路控制方法,在每个输出支路的输出端设置分时导通开关,将一个时钟周期划分为多个单元,在每一时钟周期划分单元中,单独对一路输出进行控制;设有主环路控制电路、次环路控制电路、驱动电路、电压采样电路及功率级电路,其特征在于:设置包括两个比较器构成的次环路控制电路和包括数字逻辑电路构成的选通信号产生选择电路来控制次环路功率管,使两路输出的负载电流大小任意,每个开关周期内,均向两个支路发送控制选通信号,且两个选通信号相互反相,使得两个次级开关在电感电流上升和下降阶段内分别开启和关断一次,实现两支路的稳定输出。 [0004] The present invention is a technical solution: a single inductor dual-output DC-DC switching power supply control method, two DC-DC converter integrated in a single chip, resulting in two voltage outputs, two output branch share an inductor, using time division multiplexing of the primary and secondary loop control method, set the time-conduction switch output at the output of each branch, one clock cycle is divided into multiple units, each clock cycle is divided into units , a separate control of one output; provided with a main control loop circuit, the secondary loop control circuit, the driving circuit, a voltage sampling circuit and power stage, characterized by: setting a minor loop comprising two comparators constitute control circuit and includes a strobe generation digital logic circuit to control the second selection circuit loop power control, so that the two output load current size of any, within each switching cycle, the two branches are to send control strobe and inverted between the two strobe signals, respectively, so that two secondary switches on and off once, to achieve a stable output in the two branches of the inductor current rise and fall phase.

[0005] 实现上述单电感双输出DC-DC开关电源的控制方法的电路,设有主环路控制电路、次环路控制电路、驱动电路、电压采样电路及功率级电路,主环路控制电路输出连接次环路控制电路,主环路控制电路还与驱动电路双向连接,次环路控制电路输出连接驱动电路,驱动电路输出连接功率级电路,功率级电路输出通过电压采样电路分别与主环路控制电路及次环路控制电路连接,功率级电路输出还连接主环路控制电路,其特征在于:次级环路控制电路包括第一电压比较器和第二电压比较器,第一电压比较器的正输入端接基准电压,负输入端接第一支路采样电压信号,第二电压比较器的正端输入接第二支路采样电压信号,负端输入接基准电压; [0005] The method of the control circuit to achieve single-inductor dual-output DC-DC switching power supply, a main loop control circuit, the secondary loop control circuit, driver circuit, voltage sampling circuit and power stage, the main loop control circuit output control circuit connected to the secondary loop, the main loop control circuit further two-way connection with the driving circuit, the output of the secondary loop control circuit connected to the drive circuit, the drive circuit connected to the output power stage, the power output stage circuit and the main ring, respectively through the voltage sampling circuit path control circuit and the secondary loop control circuit is connected, the power output stage circuit is also connected to the main control loop circuit, characterized in that: the secondary loop control circuit comprises a first voltage comparator and the second voltage comparator, a first voltage comparator positive input termination reference voltage, a negative input connected to a first branch sampled voltage signal, the positive terminal of the second voltage comparator connected to the second branch sampled input voltage signal, a negative input terminal connected to the reference voltage;

设置一个连接于次级环路控制电路和驱动电路之间的选通信号产生及选择电路,包括依次连接的窄脉冲产生电路、锁存电路、选择电路及整形电路;其中: Set a connection to the secondary loop control gate signal generating circuit and the driving circuit and between the selection circuit comprises a narrow pulse generating circuit connected in sequence, the latch circuit, the selection circuit and the shaping circuit; wherein:

窄脉冲产生电路设有第一〜第六6个与非门、2个电阻Rl、R2、2个电容Cl、C2以及第一、第二2个反相器,第一与非门的两个输入端均连接主环路控制电路中振荡器的输出时钟信号并与第二与非门的一个输入端连接,第一与非门的输出端连接电阻Rl的一端,电阻Rl的另一端连接电容Cl的一端及第二与非门的另一个输入端,电容Cl的另一端接地,第二与非门的输出端与第三与非门的两个输入端连接在一起,第三与非门的输出端连接第一反相器的输入端;第四与非门的两个输均连接主环路控制电路中数字逻辑模块输出的占空比信号,第四与非门的输出端连接电阻R2的一端,电阻R2的另一端连接电容C2的一端及第五与非门的一个输入端,电容C2的另一端接地,第五与非门的另一个输入端接主环路控制电路中数字逻辑模块输出的占空比信号,第五与非门的输出端与第六与非门的两个输入端连接在一起,第六与非门的输出端连接第二反相器的输入端; Narrow pulse generating circuit 6 is provided with first to sixth NAND gates, two resistors Rl, R2,2 capacitors Cl, C2 and the first and second two inverters, two first NAND gate inputs are connected to the main loop control circuit oscillator output clock signal and connected to an input of a second NAND gate, the output of the first NAND gate connected to one end of the resistor Rl, and the other end of the resistor Rl connected capacitor Cl and a second end connected to the other input terminal of the NAND gate, the other end of the capacitor Cl and the second output terminal of the NAND gate and a third NAND gate with two inputs together, a third NAND gate input connected to the output terminal of the first inverter; fourth with two input NAND gate are connected to the main loop controls the duty cycle signal circuit digital logic module output, and the output of the fourth NAND gate connection resistance One end of one end, the other end of R2 is connected to the resistor R2 and the capacitor C2 and an input terminal of the fifth NAND gate, the other end of the capacitor C2, the fifth and the other input terminal of the NAND gate circuit of the main loop digital control duty cycle signal output of the logic module, a fifth NAND gate connected to the output terminal and two input terminals of the sixth NAND gate together, the output of the sixth NAND gate connected to the input terminal of the second inverter;

锁存电路设有2个具有异步清零功能的第一D触发器和第二D触发器以及第三、第四两个反相器,第三反相器的输入端及第二D触发器的数据输入端均连接主环路控制电路中数字逻辑模块输出的占空比信号,第四反相器的输入端连接次级环路控制电路中第一比较器的输出端,第一D触发器的数据输入端连接第三反相器的输出端,第一D触发器的时钟输入端连接次级环路控制电路中第二比较器的输出端,第一D触发器的清零输入端连接窄脉冲产生电路中第一反相器的输出端,第二D触发器的时钟输入端连接第四反相器的输出端,第二D触发器的清零输入端连接窄脉冲产生电路中第二反相器的输出端; The latch circuit has two asynchronous clear function of the first D flip-flop and the second D flip-flop, and a third, a fourth two inverters, the input of the third inverter and a second D flip-flop The data input terminals are connected to the main loop of the control circuit duty cycle signal output of the digital logic module, the input of the fourth inverter circuit connected to the secondary loop control output of the first comparator, a first D flip-flop data input terminal is connected to the output of the third inverter, a clock input of the first D flip-flop circuit connected to the secondary loop control output of the second comparator, the clear input of the first D flip-flop A short pulse generation circuit connected to the output terminal of the first inverter, a clock input of the second D flip-flop connected to the output of the fourth inverter, the clear input of the second D flip-flop is connected a short pulse generation circuit output of the second inverter;

选择电路设有第一〜第四4个二选一数据选择器,第一数据选择器的一个数据输入端连接锁存电路中第二D触发器的输出端,第一、第二两个数据选择器的同相时钟输入端均连接主环路控制电路中数字逻辑模块输出的占空比信号,第一、第二两个数据选择器的反相时钟输入端均连接锁存电路中第三反相器的输出端,第一、第二两个数据选择器的另一个数据输入端均接地,第二数据选择器的一个数据输入端连接锁存电路中第一D触发器的输出端,第三数据选择器的一个数据输入端连接第一数据选择器的输出端,第三、第四两个数据选择器的同相时钟输入端均连接主环路控制电路中数字逻辑模块输出的占空比信号, 第三、第四两个数据选择器的反相时钟输入端均连接锁存电路中第三反相器的输出端,第三、第四两个数据选择器的另一个数据输入端均接地,第四数据选择器的一个数据输入端连接第二数据选择器的输出端。 Selection circuit has first to fourth four second election data selector, a first data selector connected to a data input terminal D of the second latch circuit in the output of flip-flop, the first, second two data with the phase clock input of the selector are connected to the main loop control circuit duty cycle signal output of the digital logic module, the first, the inverted clock input of the second two data selectors are connected to the latch circuit in the third anti- the output of the phase detector, a first, the other two data input of the second data selector are grounded, the second data selector, a data input terminal of the latch circuit connected to the output terminal of the first D flip-flop in the first with the phase clock input terminal of a data input terminal connected to the three first data selector to select the output of data, the third, fourth two data selectors are connected to the main loop in the control circuit of the duty cycle of the digital logic module output signal, third, fourth two data selectors are connected to an inverted clock input terminal of the latch circuit in the output of the third inverter, a third, a fourth data selector of the other two data input terminals are a data input terminal to ground, the fourth data selector connects the second output terminal of the data selector.

[0006] 整形电路设有第一、第二两个或非门和第五、第六两个反相器,第一或非门的一个输入端接选择电路中第四数据选择器的输出端,第一或非门的另一个输入端连接选择电路中第一数据选择器的输出端,第一或非门的输出端连接第五反相器的输入端,第二或非门的一个输入端连接选择电路中第三数据选择器的输出端,第二或非门的另一个输入端连接选择电路中第二数据选择器的输出端,第六反相器的输入端连接第二或非门的输出端,第五、第六两个反相器的输出端产生控制次环路功率管开关的选通控制信号。 [0006] The shaping circuit is provided with first, second two NOR gates and fifth, sixth two inverters, an input terminal of the first NOR gate selection circuit of the fourth output terminal of the data selector , the other input of the first NOR gate is connected to select a first data selector circuit output terminal, the output terminal of the first NOR gate is connected the input terminal of the fifth inverter, a second input of the NOR gate terminal is connected to select the output of the third data selector circuit, the other input of the second NOR gate is connected to the selection circuit in the second output terminal of the data selector, the input of the sixth inverter connected to the second NOR output of AND gate, the fifth, the sixth output terminal of the control of two inverters generate secondary loop power control switch gating control signal.

[0007] 本发明的优点及显著效果:(1)设置包括两个比较器构成的次环路控制电路和包括数字逻辑电路构成的选通信号产生选择电路来控制次环路功率管,使两路输出的负载电流大小任意,每个开关周期内, 均向两个支路发送控制选通信号,且两个选通信号相互反相,使得两个次级开关在电感电流上升和下降阶段内分别开启和关断一次,实现两支路的稳定输出。 [0007] advantages of the present invention and the significant effect: (1) Set comprises two comparators constituting the secondary loop control circuit and includes a strobe signal generating digital logic circuit controls the selection circuit to the secondary loop power control, so that the two output load current size of any, within each switching cycle, the two branches are to send control strobe, strobe and two mutually inverted, so that the two sub-switching inductor current rise and fall within the stage respectively, on and off once, to achieve two-way a stable output. 在一个周期内产生两个选通信号,分别控制第一支路功率管和第二支路功率管的导通和关断,克服了由于单一选通信号控制同时两个支路功率管时,只能由负载电流大的支路作为控制主环路的反馈信号,从而造成的另一支路负载电流必须小于这一支路负载电流的缺点。 Generates two strobe signals in one cycle, control the first branch tube and the second power branch of the power transistor is turned on and off, to overcome due to the single control strobe signal power tubes simultaneously when the two branches, only by the load current of the main branch as the control loop feedback signal, resulting in the other leg must be less than the load current drawback of this branch of the load current.

[0008] (2)本控制电路简单易实现,只需设计两个比较器构成的次级环路,数字逻辑构成的选通信号产生电路,即可实现上述功能,控制方法简单可靠,电路易实现,且改进电路所占版图面积小。 [0008] (2) The control circuit is simple and easy to implement, just design the secondary loop consisting of two comparators, a strobe signal generating circuit composed of digital logic, you can achieve the above functions, the control method is simple and reliable, easy circuit implementation, and improved circuit layout area occupied by small.

附图说明 Brief Description

[0009] 图1为现有技术的电原理框图; 图2为现有技术的时序及电感电流图; 图3为本发明的电原理框图; [0009] Figure 1 is an electrical block diagram of the prior art; Figure 2 is a prior art timing diagram and the inductor current; electrical schematic block diagram of Figure 3 of the present invention;

图4为本发明的一种具体实现电路; Figure 4 of the present invention a concrete realization of the circuit;

图5为本发明电路中选通信号选择电路的一种实现方式; A circuit of the present invention. FIG. 5 select a communication number selection circuit implementation;

图6为图4电路的控制时序图(高电平表示信号控制的功率管开启)。 Figure 6 is a timing diagram of the control circuit in Figure 4 (a high level control signal indicating power tube open).

具体实施方式 DETAILED DESCRIPTION

[0010] 如图3,本发明设有主环路控制电路1、次环路控制电路2、选通信号产生电路3、驱动电路4、电压采样电路5和功率级电路6。 [0010] 3, the present invention is provided with a control circuit as shown in the main loop, the secondary loop control circuit 2, a strobe signal generating circuit 3, a drive circuit 4, a voltage sampling circuit 5 and the power stage 6. 与现有技术图1相比,主环路控制电路1、驱动电路4、电压采样电路5和功率级电路6与现有技术结构相同,但次环路控制电路2与现有技术不同,另增加了连接于次环路控制电路2和驱动电路4之间的选通信号产生电路3。 Compared with the prior art FIG. 1, the main loop control circuit 1, the driving circuit 4, a voltage sampling circuit 5 and the power stage 6 and the same as the prior art structure, but the second loop-control circuit 2 and the prior art, the other increasing the control loop connected to the secondary circuit 2 and the gate signal driving circuit 4 between the generating circuit 3.

[0011] 如图4,主环路控制电路1包括基准电压产生电路,误差比较器EA,振荡器和斜率补偿电路,峰值电流检测电路和反向电流检测电路,PWM调制器,限流电路,数字逻辑。 [0011] Figure 4, the main loop control circuit includes a reference voltage generation circuit, error comparator EA, oscillator and slope compensation circuit, the peak current detection circuit and reverse current detection circuit, PWM modulator, current limiting circuit, digital logic. 主环路误差放大器EA的反相输入端连接采样电路中采样电阻R5、R6、R7的一端,同相输入端连接基准电压产生电路的输出电压;反向电流检测电路的一个输入端接电感LX的正端、主环路功率管Mpl和Mp2的漏极,另一个输入端接地;电流检测电路的输入端接电感LX的正端、 主环路功率管Mpl和Mp2的漏极;斜率补偿电路的输入接振荡器的输出;PWM调制器的反相输入端接主环路误差放大器EA的输出端,同相输入端接斜率补偿电路、电流检测电路的输出;数字逻辑电路的输入端接PWM调制器、电流检测电路、斜率补偿电路、振荡器的输出,数字逻辑电路的输出端产生控制主环路功率管开关的控制信号SN、SP。 Inverting input terminal of the error amplifier EA of the main loop sampling circuit connected to the sampling resistor R5, R6, R7, at one end, connected to the noninverting input of the reference voltage generating circuit output voltage; an input connected to the inductor LX of the reverse current detecting circuit the positive terminal, the main loop power transistor Mpl and the drain of Mp2, the other input is grounded; input termination LX inductor current detection circuit of the positive terminal, the main loop power transistor Mpl and the drain of Mp2; slope compensation circuit input connected to the oscillator output; the output of the PWM modulator of the inverting input terminal of the error amplifier EA of the main loop, non-inverting input output termination slope compensation circuit, the current detection circuit; input end of the PWM modulator for digital logic circuits , the current detection circuit, the slope compensation circuit, the oscillator output, the output terminal of the digital logic circuit generates control signals SN main loop power control switch, SP.

[0012] 主环路第一功率管Mpl的栅极接主环路产生的占空比驱动信号PD,Mpl的源极接输入电源电压Vin,Mpl的漏极接电感LX的正端以及主环路第二功率管Mnl的漏极于。 [0012] the duty cycle of the driving signal PD main loop of the first power transistor gate connected to the main loop Mpl generated, Mpl source connected to the input supply voltage Vin, Mpl LX drain connected to the positive terminal of the inductor and the main ring Road Mnl second power drain pipe in. 主环路第二功率管Mp2的栅极接主环路产生的占空比驱动信号ND,Mnl的源极接地。 The duty cycle of the drive signal ND main loop of the second power transistor gate connected to the main loop Mp2 generated, Mnl source grounded. 电感LX 的负端接支路功率管Mp2和Mp3的源极,支路功率管Mp2和Mp3的栅极分别连接选通次级驱动电路产生的选通驱动信号Dl和D2,支路功率管Mp2和Mp3的漏极分别连接支路输出滤波电容Cl和C2的正端、负载电阻Rol和Ro2的一端以及采样电路的采样电阻Rl、R2的一端。 Inductance LX negative termination branch power source tube Mp2 and Mp3 pole, branch power tube Mp2 and gate are connected strobe Mp3 secondary drive circuit generates a drive signal strobe Dl and D2, branch power tube Mp2 Mp3 drain and output filter capacitors are connected to the branch Cl and C2 positive side, the load resistance Rol and Ro2 sampling resistor Rl end and sampling circuit, one end of R2. 采样电路的采样电阻Rl的另一端分别连接采样电阻R3的一端、支路比较器CMPl的反相输入端。 The other end of the sampling resistor Rl sampling circuit are connected to the inverting input terminal of the resistor R3 sampling end, the branch of the comparator CMPl. 采样电路的采样电阻R2的另一端分别连接采样电阻R4、支路比较器CMP2的同相输入端。 The other end of the sampling circuit sampling resistor R2 are connected sampling resistor R4, the branch of the comparator CMP2-inverting input. 采样电阻R3、R4的另一端接地。 Sampling resistors R3, R4 of the other end. 支路比较器CMPl的同相输入端、CMP2的反相输入端、误差放大器的同相输入端以及基准电压的输出端连接。 Noninverting input branch of comparator CMPl, CMP2 inverting input of the error amplifier non-inverting input terminal and an output terminal connected to a reference voltage. 支路比较器CMPl的输出端与选通信号选择电路连接。 The output branch comparator CMPl is connected to the gate signal selection circuit. 支路比较器CMP2的输出端与选通信号选择电路连接。 The output branch of the comparator CMP2 is connected to the gate signal selection circuit. 振荡器的输出端与谐波补偿电路、选通信号选择电路、数字逻辑电路连接。 The output of the oscillator and the harmonic compensation circuit, strobe selection circuits, digital logic circuits.

[0013] 驱动电路4包括驱动和死区控制电路,为成熟的电路结构,其内部结构在此不再赘述。 [0013] The drive circuit 4 includes drivers and dead time control circuit, the circuit structure is mature, its internal structure is not described here. 该电路的输入端接主环路控制电路产生的输出信号SN、SP以及次环路控制电路产生的输出信号Si、S2 ;驱动电路的输出端产生驱动主环路功率管开关的驱动信号PD、ND和控制次环路功率管开关的驱动信号Dl、D2。 Input terminal of the main loop circuit control circuit generates an output signal SN, SP and a secondary loop control circuit generates an output signal Si, S2; the output of the drive circuit generates a drive signal driving the main loop power transistor PD switches, Dl ND drive signals and control sub-loop power control switch, D2.

[0014] 功率级电路6包括第一功率管Mpl和第二功率管Mnl构成的同步整流电路,电感LX,以及支路功率管Mp2和Mp3。 [0014] the power stage circuit 6 includes a first power synchronous rectifier circuit and a second power tube tube Mpl Mnl constituted inductance LX, and branch power tube Mp2 and Mp3. 第一功率管Mpl的栅极接主环路产生的占空比驱动信号PD,Mpl的源极接输入电源电压Vin,;第二功率管Mnl的栅极接主环路产生的占空比驱动信号ND,Mnl的源极接地;,支路功率管Mp2和Mp3的栅极分别连接选通次级驱动电路产生的选通驱动信号Dl和D2,支路功率管Mp2和Mp3的漏极分别连接支路输出滤波电容Cl和C2 的正端、负载电阻Rol和Ro2的一端以及采样电路的采样电阻Rl、R2的一端,电感LX的正端接第一功率管Mpl的漏极、第二功率管Mnl的漏极,电感LX的负端接支路功率管Mp2和Mp3的源极。 The duty cycle of the drive signal PD first power transistor gate connected to the main loop Mpl generated, Mpl input source connected to the second power supply voltage Vin ,; tube connected to the gate of the main loop Mnl generated duty driving signal ND, Mnl source grounded;, branch power transistor Mp2 and Mp3 are connected to the gate of a gate driving signal Dl gate driving circuit of the secondary and D2, branch power transistor Mp2 and Mp3 are connected to the drain sampling resistor Rl branch output filter capacitors Cl and C2 positive side, the load resistance Rol and Ro2 end and a sampling circuit, one end of R2, the positive terminal of the first inductor LX Mpl power drain pipe, a second power tube Mnl drain inductance LX negative termination branch power source tube Mp2 and Mp3 pole.

[0015] 电压采样电路5包括采样电阻1?1、1?2、1?3、1?4、1?5、1?6、1?7,连接关系如下:采样电阻R1、R2的一端分别连接支路功率管Mp2和Mp3的漏极、支路输出滤波电容Cl和C2的正端、 负载电阻Rol和Ro2的一端,采样电阻Rl的另一端分别连接采样电阻R3的一端、支路比较器CMPl的反相输入端。 [0015] voltage sampling circuit 5 includes a sampling resistor 1,1 2,1 3,1 4,1 5,1 6,1 7 connects the following:??????? Sampling resistor R1, R2, respectively, at one end connecting branch power drain pipe Mp2 and Mp3, branch output filter capacitors Cl and C2 of the positive terminal of the load resistors Rol and Ro2 at one end, and the other terminal of the sampling resistor Rl are connected to the sampling end of the resistor R3, the branch comparator CMPl inverting input. 采样电路的采样电阻R2的另一端分别连接采样电阻R4、支路比较器CMP2的同相输入端。 The other end of the sampling circuit sampling resistor R2 are connected sampling resistor R4, the branch of the comparator CMP2-inverting input. 采样电阻R3、R4的另一端接地,采样电阻R5、R6、R7的一端连接主环路误差放大器EA的反相输入端,R5的另一端接第一支路输出电压,R6的另一端接第二支路输出电压,R7的另一端接地。 Sampling resistors R3, R4 of the other end, the sampling resistor R5, R6, R7 is connected one end of the main loop error amplifier EA of the inverting input terminal, the other end of the first branch output voltage R5, R6 of the other end of the first two branch output voltages, R7 of the other end.

[0016] 上述电路为典型的峰值电流模式的控制环路,为成熟技术。 [0016] The circuit described above typical peak current control loop mode, a mature technology.

[0017] 次级环路控制电路2包括第一支路电压比较器CMPl和第二支路比较器CMP2。 [0017] the secondary loop control circuit 2 comprises a first branch and a second voltage comparator CMPl branch comparator CMP2. 其中CMPl的正输入端接基准电压Vref,负输入端接第一支路采样电压信号Vol,当第一支路的输出电压VOUTl超过设定值时,输出一个下降沿信号Vcmpl。 Wherein CMPl positive input termination reference voltage Vref, the negative input terminal of the first branch sampled voltage signal Vol, when the first branch of the output voltage VOUTl exceeds the set value, outputs a falling edge signal Vcmpl. CMP2的正端输入接第二支路采样电压信号Vo2,负端输入接基准电压信号Vref,当第二支路的输出电压V0UT2超过设定值时,输出一个上升沿信号Vcmp2。 CMP2 input connected to the positive terminal of the second branch sampling voltage signal Vo2, negative input connected to a reference voltage signal Vref, when the second branch of the output voltage V0UT2 exceeds a set value, the output signal of a rising edge Vcmp2.

[0018] 参看图5,选通信号选择电路3产生一组驱动模块的输入占空比信号Sl和S2。 [0018] Referring to Figure 5, the strobe selection circuit 3 generates a set of input duty cycle signal Sl drive module and S2. 选通信号选择电路3包括窄脉冲产生电路7,锁存电路8,选择电路9和整形电路10,窄脉冲产生电路7由与非门nand2,电阻Rl、R2和电容Cl、C2、反相器1、反相器2。 Strobe signal selecting circuit 3 comprises a narrow pulse generating circuit 7, the latch circuit 8, the selection circuit 9 and the shaping circuit 10, a narrow pulse generating circuit 7 is composed of a NAND gate nand2, resistors Rl, R2 and capacitor Cl, C2, inverter 1, an inverter 2. 与非门nand2和反相器构成的整形电路,产生一组窄脉冲信号CLK_pulSe和SP_pulse。 NAND gate nand2 shaping circuit of inverters and generate a set of narrow pulse signal CLK_pulSe and SP_pulse. 锁存电路8由两个具有异步清零功能的上升沿有效的2个D触发器构成,锁存Vcmpl的下降沿和Vcmp2的上升沿,避免因为比较器CMPl和CMP2因噪声等等原因造成的误比较对支路功率管的开关形成干扰。 The latch circuit 8 is composed of two rising edge of two D flip-flop with asynchronous clear function of composition, falling and rising edge of the latch Vcmpl Vcmp2 avoid because comparator CMP2 CMPl and causes due to noise, etc. false comparison branch power switch tube interfere. 选择电路9由4个二选一数据选择器MUXl至MUX4构成,其中MUXl和MUX2分别产生在主环路第一功率管Mpl和主环路第二功率管Mnl导通时,第一支路功率管Mp2的选通控制信号S1_PD和S1_ND,MUX3和MUX4分别产生在主环路第一功率管Mpl和主环路第二功率管Mnl导通时,第二支路功率管Mp3的选通控制信号S2_PD和S2_ND。 When selecting circuit 9 by 4 second election data selector MUXl to MUX4 constitution, which MUXl and MUX2 generate in the main loop of the first power transistor Mpl and the main loop of the second power transistor Mnl conduction, the first branch of power tube Mp2 gating control signal S1_PD and S1_ND, MUX3 and MUX4 generate power in the main loop of the first tube and the main loop Mpl Mnl second power tube is turned on, the second branch pipe Mp3 power gating control signal S2_PD and S2_ND. 整形电路10将分段的选通控制信号Si_PD和Si_ND (i=l、2)组合成为光滑连续的选通控制信号Si (i=l、 2)。 Shaping circuit 10 will be segmented and strobe control signal Si_PD Si_ND (i = l, 2) combined into a smooth continuous strobe control signal Si (i = l, 2). 电压采样电路5由三组组不同阻值的电阻串联而成,选取合适的电阻阻值,使得三个采样电路的采样电压Vol、Vo2以及KX (Vol+Vo2)可以和同一个基准电压Vref进行比较。 Sampling voltage sampling circuit 5 by three groups of different value resistor in series, select the appropriate resistor, making the three sampling circuit voltage Vol, Vo2 and KX (Vol + Vo2) can be performed with a reference voltage Vref Compare. 选通信号选择电路的输出信号Si、S2与驱动电路的输入端分别连接。 Strobe signal selection circuit output signal Si, the input terminal S2 of the driver circuit are connected.

[0019] 窄脉冲产生电路7的一个输入端连接CLK信号,窄脉冲产生电路的输入端另一个输入端、锁存电路8中D触发器DFFl的数据输入端、选择电路MUXi (i=l、2、3、4)的数据信号输入端连接,接SP信号,SP信号经反相后连接锁存电路中D触发器DFF2的数据输入端、 选择电路MUXi (i=l、2、3、4)的反相时钟信号输入端。 [0019] A short pulse generation circuit 7 to one input terminal connected to the CLK signal, the narrow pulse generating circuit to another input terminal of the input terminal, a data input terminal of the latch circuit 8 and the D flip-flop DFFl selection circuit MUXi (i = l, 2,3,4) connected to a data signal input terminal, connected to the SP signal, SP signal by the inverting input terminal of the data latch circuit connected to the D flip-flops DFF2, the selection circuit MUXi (i = l, 2,3,4 ) of the inverted clock signal input terminal. 窄脉冲电路的两个输出端分别和锁存电路中两个D触发器DFF1、DFF2的数据清零端连接。 Two outputs respectively narrow pulse circuit and latch circuit two D flip-flops DFF1, DFF2 data cleared terminal. 锁存电路中D触发器DFFl的数据输入端和支路比较器CMPl的输出信号Vcmpl的反相信号连接,锁存电路中D触发器DFF2 的数据输入端和支路比较器CMP2的输出端连接。 The inverted signal of the latch circuit connected to the data D input terminal of flip-flop DFFl branch comparator CMPl and the output signal Vcmpl, the data input terminals and branch output of the comparator CMP2 is connected D flip-flops DFF2 latch circuit . 锁存电路中D触发器DFF2、DFFl的输出端Q1、Q2分别和选择电路MUX1、MUX2的第一数据输入端(Si)连接。 D flip-flops DFF2, DFFl output terminal Q1, Q2 and the selection circuit MUX1, MUX2 a first data input terminal (Si) connected to the latch circuit, respectively. MUXl的输出端MOl和MUX3的第一数据输入端(Si)、整形电路的输入端连接。 MUXl MUX3 output terminal MOl and a first data input terminal (Si), the input of the shaping circuit is connected. MUX2的输出端M02和MUX4的第一数据输入端(S2)、整形电路的输入端连接。 M02 and the output of MUX2 MUX4 first data input terminal (S2), the input of the shaping circuit is connected. MUXi (i=l、2、3、4)的第二输入端(S2)均接地。 MUXi (i = l, 2,3,4) of a second input terminal (S2) are grounded. MUX3的输出端M03和整形电路的输入端连接,MUX4的输出端M04和组合电路的输入端连接。 M03 and the input of the output shaping circuit connected MUX3, MUX4 inputs output of M04 and a combination circuit.

[0020] 本发明电路的工作原理:采用分时复用的主、次环路控制方法,在每个输出支路的输出端设置分时导通开关,将一个时钟周期划分为多个单元,在每一时钟周期划分单元中, 单独对一路输出进行控制。 [0020] inventive circuit works: The primary and secondary loop control method for time-multiplexed output at the output of each branch set time-switch is turned on, the clock cycle is divided into multiple units, In each clock cycle division unit, a separate control for one output. 设置包括两个比较器构成的次环路和包括数字逻辑电路构成的选通信号产生选择电路来控制次环路功率管,使两路输出的负载电流大小任意,每个开关周期内,均向两个支路发送控制选通信号,且两个选通信号相互反相,使得两个次级开关在电感电流上升和下降阶段内分别开关一次,每个周期开始时,由时钟信号开启主环路功率管和第二支路功率管,分别采样第一和第二输出支路的输出电压之后送入误差放大器与基准电压比较,产生第一负反馈信号,选择第一负反馈信号与三角波信号及检测电流信号相比较,产生控制主环路功率管开关的驱动信号;采样第二支路的输出电压送入第一比较器与基准电压比较,产生第二负反馈信号;采样第一支路的输出电压,送入第二比较器与基准电压比较,产生第三负反馈信号;当第二负反馈信号高于基准电压时,产生高电平信号, 用于关断第二支路功率管和开启第一支路功率管;当第三负反馈信号高于基准电压时,产生高电平信号,用于关断第一支路功率管和开启第二支路功率管。 Settings include secondary loop consisting of two comparators and include strobe generation digital logic circuit selection circuit to control the secondary loop power control, so that the two output load current size of any, within each switching cycle, both to two branches transmission control strobe signal, and two strobe signals mutually inverted, so that two secondary switches in the inductor current rise and fall time switch stage respectively, beginning of each cycle, the clock signal is on the primary ring After the power tube and the second path branch power tube, respectively sampled first and second output branch of the output voltage fed to the error amplifier with a reference voltage comparison, generating a first negative feedback signal, selecting the first negative feedback signal with the triangular wave signal and comparing the detected current signal, generating a driving signal controlling the main loop power control switch; sampling the output voltage of the second branch and fed to the first comparator comparing the reference voltage, generating a second negative feedback signal; sampling a first branch output voltage, the second comparator is fed with a reference voltage comparator, generating a third negative feedback signal; a negative feedback signal when the second is higher than the reference voltage, generating a high level signal for turning off the second power branch pipe and the opening of the first branch power tube; when the third negative feedback signal is higher than the reference voltage, resulting in a high level signal for turning off the first branch power tube and open a second branch power tubes.

[0021] (1)第二支路充电:,每个周期开始时,系统时钟信号CLK开启主环路第一功率管Mpl,同时CLK经过窄脉冲产生电路所产生的窄脉冲将同时开启第二支路功率管Mp2,输入电压Vin提供能量给第二输出支路,直至第二支路的输出电压上升至第二支路的采样电压Vo2高于基准电压Vref,次级控制环路将产生一个上升沿的电压信号Vcmp2,将第二支路功率管Mp3关断,第二支路充电过程结束。 [0021] (1) charging a second branch:, beginning of each cycle, the system clock signal CLK to open the main loop of the first power transistor Mpl, while narrow pulse CLK after generating a narrow pulse generated by the circuit will also open the second branch power tube Mp2, the input voltage Vin provides energy to the second output branch, the second branch of the output until the voltage rises to the second branch of the sampled voltage Vo2 is higher than the reference voltage Vref, the secondary control loop will generate a rising edge of the voltage signal Vcmp2, the second branch pipe Mp3 power off, the end of the second branch charging process.

[0022] (2)第一支路充电和续流:次级控制环路产生一个上升沿的电压信号Vcmp2,第二支路功率管Mp3关断的同时,该上升沿的Vcmp2同时也开启第一支路功率管Mp2,输入电压Vin给第一支路提供能量,第一支路输出电压上升,直至峰值电流型主环路将主环路第一功率管Mpl关断,并开启主环路第二功率管Mp2。 [0022] (2) The first branch of charge and freewheeling: secondary control loop generates a voltage signal Vcmp2 a rising edge, the second branch pipe Mp3 power off while the rising edge of Vcmp2 but also opened the first one-way power tube Mp2, the input voltage Vin to provide energy to the first branch, the first branch output voltage rise until the peak current type main loop of the main loop of the first power transistor Mpl off, and turn the main loop The second power tube Mp2. 主环路充电过程结束,电感进入续流阶段。 Main loop charging process is completed, the inductor into the freewheeling stage. 此时,电感电流流经第一输出支路,第一输出支路续流,第一支路输出电压继续上升,直至第一支路的采样电压Vol高于基准电压Vref,产生一个下降沿的Vcmpl信号,将第一支路功率管Mp2关断,第一支路充电过程结束; At this time, the inductor current flows through the first output branch, a first output branch freewheeling, a first branch output voltage continues to rise until the first branch of the voltage sampling Vol higher than the reference voltage Vref, generates a falling edge Vcmpl signal, the first branch pipe Mp2 turns off the power, end of the first branch charging process;

(3)第二支路续流:下降沿的Vcmpl信号,将第一支路功率管Mp2关断的同时,开启第二支路功率管Mp3,电感电流经第二支路功率管Mp3续流,直至一个开关周期结束; 重复上面(1)〜(3)的过程,这样完成电路周而复始的工作。 (3) The second branch freewheeling: Vcmpl signal falling edge, the first branch pipe Mp2 power off while the power to open a second branch pipe Mp3, power inductor current through the second branch pipe Mp3 freewheeling until the end of a switching cycle; repeat the above (1) to (3) of the process, thus completing the circuit cycle of work.

[0023] 每个开关周期内,均向两个支路发送控制选通信号,且两个选通信号相互反相,使得两个次级开关在电感电流上升和下降阶段内分别开关一次; [0023] each switching cycle, are sent to two control branches strobe signal, and two strobe signals mutually inverted, so that two secondary switches in the inductor current rise and fall phase switching time, respectively;

一个完整的开关周期内的操作过程如下; During operation a complete switching cycle is as follows;

每个周期开始时,由时钟信号开启主回路功率管和第二支路功率管; 采样第一和第二输出支路的输出电压为KX (Vol+Vo2)之后送入误差放大器,与基准电压比较,产生第一负反馈信号,选择第一负反馈信号,与三角波信号及检测电流信号相比较,产生控制主功率管开关的驱动信号; Beginning of each cycle, the clock signal is turned on by the power transistor and the second main circuit branch power tube; sampled first and second output branch of the output voltage is fed to the error amplifier KX (Vol + Vo2) After that, the reference voltage comparison, generating a first negative feedback signal, selecting the first negative feedback signal, compared with the triangular wave signal and the detected current signal, generating a driving signal controlling the main power switch tube;

采样第二支路的输出电压,送入比较器一,与基准电压比较,产生第二负反馈信号; 采样第一支路的输出电压,送入比较器二,基准电压比较,产生第三负反馈信号; 当第二负反馈信号高于基准电压时,产生高电平信号,用于关断第二支路功率管和开启第一支路功率管; Sampling the output voltage of the second branch, fed to a comparator, comparing with the reference voltage, generating a second negative feedback signal; sampling the output voltage of the first branch, fed into two comparators, a reference voltage comparator, generating a third negative feedback signal; when the second negative feedback signal is higher than the reference voltage, resulting in a high level signal for turning off the second branch power tube and open the first branch power tube;

当第三负反馈信号高于基准电压时,产生高电平信号,用于关断第一支路功率管和开启第二支路功率管。 When the third negative feedback signal is higher than the reference voltage, resulting in a high level signal for turning off the power transistor and the first branch to open a second branch power tubes.

[0024] 主环路控制电路1,驱动电路4和功率级6电路的电路构成和工作方式可以参考现有技术,此处略过不表,以下将主要描述本发明的主体电路和工作过程,即次级环路和支路选通信号产生电路的构成和工作过程。 [0024] The main loop control circuit 1, drive circuit 4 and the power stage 6 and the circuit configuration of the circuit can refer to the prior art mode of operation, where no skip table, the main circuit will be mainly described below and the operation of the present invention, That secondary loop and branch strobe generation and work processes constitute the circuit.

[0025] 实现上述控制方式的开关变换器的次级环路控制电路2基于比较器控制,正输入端连接第一支路采样电压,负端连接基准电压的第一支路电压比较器,正输入端连接第二支路采样电压,负端连接基准电压的第二支路电压比较器,两个比较器的输出VCmpl、VCmp2 连接选通信号产生电路电路3。 [0025] to achieve the above control method of a switching converter based on the secondary loop control circuit 2 to control a comparator, the positive input terminal connected to a first branch sampling voltage, the reference voltage connected to the negative terminal of the first voltage comparator branch, n input is connected a second branch sampling voltage, negative terminal of the second branch of the voltage reference voltage comparator, two comparator output VCmpl, VCmp2 strobe signal generating circuit connected to the circuit 3.

[0026] 由选通信号产生电路3产生控制支路功率管开关的选通信号Si、S2,这两个信号通过驱动模块4后产生驱动支路功率管Mp2、Mp3的驱动信号D1、D2 ; [0026] by the gate signal generating circuit 3 generates a control branch power switch tube strobe signal Si, S2, the two signals generated by the drive module drive branch power tube Mp2, Mp3 drive signals D1, D2 after 4;

采样电路5通过电阻分压,产生一组可与基准电压比较的采样电压KX (Vol+Vo2) (K<1)、Vol、Vo2,通过选择不同的电阻,使采样电压KX (Vol+Vo2)、Vol、Vo2可与同一个基准电压Vref比较,使整个开关变换器只使用一个基准电压,节省基准电压产生电路的面积; Sampling circuit 5 via a resistor divider, to produce a set of comparison with a reference voltage sampled voltage KX (Vol + Vo2) (K <1), Vol, Vo2, by selecting different resistance, the sampling voltage KX (Vol + Vo2) , Vol, Vo2 may be compared with a reference voltage Vref, the entire switching converter using only one reference voltage, the reference voltage generating save area of the circuit;

次环路控制电路2将采样电压Vo2与基准电压Vref比较,当第二支路的采样电压Vo2 低于基准电压Vref时,第二支路电压比较器CMP2输出低电平的Vcmp2,当第二支路的采样电压Vo2高于基准电压Vref时,第二支路电压比较器CMP2输出高电平的Vcmp2 ; Secondary loop control circuit 2 compares the sampled voltage Vo2 with the reference voltage Vref, when sampling the voltage of the second branch of Vo2 is lower than the reference voltage Vref, the second branch output low voltage comparator CMP2 of Vcmp2, when the second When sampled voltage higher than the reference voltage Vo2 branch Vref, the second branch output high voltage comparator CMP2 of Vcmp2;

次环路控制电路2将采样电压Vol与基准电压Vref比较,当第一支路的采样电压Vol 低于基准电压Vref时,第一支路电压比较器CMPl输出高电平的Vcmpl,当第一支路的采样电压Vol高于基准电压Vref时,第一支路电压比较器CMPl输出低电平的Vcmpl ;选通信号选择电路3将比较器的输出信号锁存并产生一组控制支路功率管导通和关断的选通信号:当主回路第一功率管Mpl导通且Vcmp2由低电平跳变为高电平时,产生一个触发信号,该触发信号关闭第二支路功率管Mp3并同时开启第一支路功率管Mp2;当主回路第二功率管Mnl导通且Vcmpl由高电平跳变为低电平后,产生一个触发信号,该信号关闭第一支路功率管Mp2并同时开启第二支路功率管Mp3。 Secondary loop control circuit compares the sampled voltage Vol 2 and the reference voltage Vref, when the first branch of the voltage sampling Vol below the reference voltage Vref, the first branch of the voltage comparator outputs a high CMPl Vcmpl, when the first sampling branch voltage higher than the reference voltage Vol Vref, the first branch output low voltage comparator CMPl of Vcmpl; strobe selection circuit 3 latches the output signal of the comparator and generates a set of control branch power MOSFET on and off the strobe: When the main circuit of the first power transistor is turned on and Vcmp2 Mpl jump from low to high, generates a trigger signal, the trigger signal is turned off and the second branch power tube Mp3 At the same time open the first branch power tube Mp2; when the main circuit of the second power transistor is turned on and Vcmpl Mnl jump from high to low, generates a trigger signal that closes the first branch power tube and at the same time Mp2 open a second branch power tubes Mp3. 这样,在一个开关周期内,有两个信号Sl和S2控制第一支路功率管和第二支路功率管; Thus, in a switching cycle, there are two signals Sl and S2 control the first and second branches branch power tube power tube;

参看图6,与现有技术的时序比较可见,本方案在一个周期内,产生的选通信号Sl和S2 可以使得第一支路功率管和第二支路功率管在每个时钟周期内,电感充电过程和电感放电过程中,均开启和关断一次,从而避免了特定支路的电流限制。 Referring to Figure 6, and comparing the timing of the prior art can be seen, the program in one cycle, strobe Sl and S2 can be generated so that the first and second branches branch power tube power tube in each clock cycle, inductance inductance during charging and discharging process, both on and off once, thus avoiding a specific branch of the current limit.

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CN103701307A *31 Dec 20132 Apr 2014成都芯源系统有限公司Single inductance multi-output buck converter as well as control circuit and control method of single inductance multi-output buck converter
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Classifications
International ClassificationH02M3/156
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