CN102237788A - Charge pump circuit and memory - Google Patents
Charge pump circuit and memory Download PDFInfo
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- CN102237788A CN102237788A CN2010101688379A CN201010168837A CN102237788A CN 102237788 A CN102237788 A CN 102237788A CN 2010101688379 A CN2010101688379 A CN 2010101688379A CN 201010168837 A CN201010168837 A CN 201010168837A CN 102237788 A CN102237788 A CN 102237788A
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- charge pump
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Abstract
The invention provides a charge pump circuit and a memory. The charge pump circuit comprises a clock driver and a charge pump unit, wherein the charge pump unit is used for providing voltages for a first type of loads and a second type of loads under the drive of the clock driver; the clock driver comprises a first clock driver and a second clock driver; the drive capacity of the first clock driver is more than that of the second clock driver; the first clock driver is used for driving the charge pump unit to provide the voltages for the first type of loads; and the second clock driver is used for driving the charge pump unit to provide the voltages for the second type of loads. When the charge pump circuit provides voltages for small loads, the clock driver with the weak drive capacity is used; and the clock driver with the weak drive capacity has lower parasitic capacitance due to adopting a small-size device, so the clock driver with the weak drive capacity can be reduced in power consumption when the charge pump circuit provides the voltages for the small loads.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of charge pump circuit and memory.
Background technology
In the information age, information stores is one of most important technology contents in the information technology.Memories such as DRAM, EEPROM, flash memory obtain application more and more widely.
Based on low-power consumption, requirement cheaply, the supply voltage of memory is lower usually, for example 2.5V, 1.8V etc., yet " writing " and " removing " in order to realize information, usually need be far above the program voltage and the erasing voltage of supply voltage, for example 8V or 11V etc.Therefore, charge pump circuit is widely used in the memory, is used for obtaining higher program voltage, erasing voltage by lower supply voltage.
With reference to figure 1, show two-stage Dickson charge pump schematic diagram.As shown in Figure 1, each voltage-boosting stage of Dickson charge pump is managed (grid connects drain electrode), is connected in the electric capacity formation that NMOS manages source electrode by the NMOS of a diode connection, and the other end of electric capacity is connected in clock oscillation circuit.Wherein, the electric capacity of each voltage-boosting stage is equivalent coupling capacitance, and clock oscillation circuit produces
The not overlapping clock of two-phase, the amplitude of clock generally equates with supply voltage VDD.During charge pump work, when
Be low level, power supply V
DDBy the NMOS pipe C1 is charged, when
During for high level, C1 top crown voltage jump is 2V
DD, to the C2 charging, like this, electric charge has just passed to the right from the left side.And work as
When being low level again, because the unidirectional conduction of diode connection NMOS pipe, electric charge can't transmit go back to the left side from the right, and like this, along with the increase of charge pump progression, electric charge just is delivered to output from power supply continuously, thereby obtains required high pressure.Usually need clock driver in the prior art, with the opening and closing of control NMOS pipe.
With reference to figure 2, show the schematic diagram that prior art is applied to the charge pump circuit of memory.As shown in Figure 2, in the prior art, in the programming and erase process of memory, adopt same clock driver 200 and same charge pump unit 100 that program voltage and erasing voltage are provided.Between charge pump unit 100 and memory cell array 400, comprise a selector 300: in the programming process, charge pump circuit provides program voltage to memory cell array 400, and selector 300 makes the output of charge pump unit 100 and the programming incoming end conducting in the memory cell array 400; In the erase process, charge pump circuit provides erasing voltage to memory, and selector 300 makes wipes the incoming end conducting in the output of charge pump unit 100 and the memory cell array 400.For described memory cell array 400, its programming incoming end and to wipe incoming end different usually, for example for " floating boom " type memory, the programming incoming end is the transistorized source electrode of floating boom, is the floating boom transistor drain and wipe incoming end.So, charge pump circuit is in the process that program voltage and erasing voltage are provided, and the load size that the electric charge delivery side of pump is connected is different.
Because electric current is extracted in the load meeting of charge pump output, and in order to make charge pump keep work, drive current must be greater than load current, this just needs clock driver to have stronger driving force, so that bigger drive current to be provided, especially for heavy load, the driving force of corresponding clock driver requires higher.Charge pump circuit as shown in Figure 2 includes only a clock driver, described clock driver is in order to be applicable to the situation that drives different big or small loads in programming and the erase process, the driving force of clock driver needs enough by force to drive the situation than heavy load, just can meet the demands, and in order to obtain bigger driving force, usually need the conducting resistance of clock driver smaller, in order to realize less conducting resistance, the general clock driver that adopts big breadth length ratio, yet, the parasitic capacitance of big breadth length ratio device can be bigger, and the parasitic capacitance conference causes bigger power consumption.
Summary of the invention
The problem that the present invention solves provides a kind of charge pump circuit, to improve the bigger problem of power consumption.
For addressing the above problem, the invention provides a kind of charge pump circuit, comprising: clock driver and charge pump unit, wherein, described charge pump unit is used for providing voltage to the first kind and the second type load under the driving of clock driver; Described clock driver comprises first clock driver and second clock driver, and the driving force of described first clock driver is greater than the driving force of second clock driver, described first clock driver is used to drive charge pump unit provides voltage to first kind load, and described second clock driver is used to drive charge pump unit provides voltage to the second type load.
Optionally, described charge pump unit is first charge pump that all links to each other with first clock driver and second clock driver.
Optionally, charge pump unit comprises: first charge pump that links to each other with first clock driver and second charge pump that links to each other with the second clock driver, described first charge pump provides voltage to first kind load under first clock driver drives, described second charge pump provides voltage to the second type load under the second clock driver drives.
A kind of memory that comprises described charge pump circuit, described memory also comprises memory cell array, described clock driver is used to drive charge pump unit provides program voltage and erasing voltage to memory cell array respectively.
Optionally, first clock driver drives charge pump unit and provides program voltage to the programming incoming end of memory cell array, and second clock driver drives charge pump unit provides erasing voltage to the incoming end of wiping of memory cell array.
Optionally, first clock driver drives charge pump unit and provides erasing voltage to the incoming end of wiping of memory cell array, and second clock driver drives charge pump unit provides program voltage to the programming incoming end of memory cell array.
Optionally, described memory also comprises controller and selector, described controller is used for providing programming instruction or erasing instruction respectively to first clock driver and second clock driver, first, the second clock driver triggers the charge pump circuit unit respectively and provides program voltage or erasing voltage to memory cell array, described controller also provides programming instruction or erasing instruction to selector, described selector links to each other with charge pump unit and memory cell array, under the triggering of described programming instruction or erasing instruction, the programming incoming end of the output of corresponding connection charge pump unit and memory cell array or wipe incoming end.
A kind of memory that comprises described charge pump circuit, described memory also comprises controller, described controller is used for providing programming instruction to first clock driver and first charge pump, provides erasing instruction to the second clock driver and second charge pump; Perhaps, described controller is used for providing erasing instruction to first clock driver and first charge pump, provides programming instruction to the second clock driver and second charge pump.
Compared with prior art, the present invention has the following advantages: be used for when little load provides voltage, adopt the weak clock driver of driving force, and the weak clock driver of driving force is owing to adopt small size device, its parasitic capacitance is less, so be used for when little load provides voltage, can reducing power consumption.
Description of drawings
Fig. 1 is a prior art Dickson charge pump schematic diagram;
Fig. 2 is the schematic diagram that prior art is used for the charge pump circuit of memory;
Fig. 3 is the schematic diagram of charge pump circuit one execution mode of the present invention;
Fig. 4 is the schematic diagram of memory one embodiment of the present invention;
Fig. 5 is the schematic diagram of the another embodiment of memory of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth a lot of details in the following description so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background section, prior art is used for the charge pump circuit of memory, in program voltage and erasing voltage process are provided, use same clock driver, in order to be suitable for the programming process and the erase process of memory simultaneously, the strong clock driver of available technology adopting driving force is to satisfy the situation of heavy load, in fact, when the output of charge pump circuit is little load, do not need the clock driver of big driving force.The clock driver that described driving force is strong can cause big power consumption owing to have bigger parasitic capacitance.
At the problems referred to above, the invention provides a kind of charge pump circuit, with reference to figure 3, show the schematic diagram of charge pump circuit one execution mode of the present invention.
Described charge pump circuit comprises clock driver 203 and charge pump unit 101, wherein,
With heavy load as first kind load, with little load as the second type load, so, first clock driver 201 that driving force is strong is used to drive charge pump unit 101 provides the process of voltage to first kind load, and the weak second clock driver 202 of driving force is used to drive charge pump unit 101 provides process from voltage to the second type load.
In prior art, at charge pump circuit when little load provides voltage, still adopt the strong clock driver of driving force to compare, charge pump circuit provided by the invention, clock driver a little less than when little load provides voltage, adopting driving force, and the weak clock driver of driving force is owing to adopt small size device, its parasitic capacitance is less, so when little load provides voltage, required power consumption is more much smaller than existing technical scheme.
Because charge pump circuit is widely used in the memory, below in conjunction with the specific embodiment of memory, charge pump circuit of the present invention is elaborated.With reference to figure 4, show the schematic diagram of memory one embodiment.As shown in Figure 4, in the present embodiment, charge pump circuit provides program voltage and erasing voltage to memory, described memory comprises: controller 500, clock driver 203, charge pump unit 101, selector 301 and memory array cell 401, described clock driver 203 comprises Mbus driver 201 and wipes clock driver 202, wherein:
The drive signal booster tension that provides according to clock driver 203 is provided charge pump unit 101, after the output voltage of charge pump unit 101 reaches target voltage (program voltage or erasing voltage), and export target voltage.
The course of work of present embodiment memory is: the memory information of carrying out is write fashionable, controller 500 sends programming instruction to the Mbus driver 201 and the selector 301 of clock driver 203, Mbus driver 201 is under the triggering of described programming instruction, send drive signal to charge pump unit 101, charge pump unit 101 is under the driving of Mbus driver 201, through the multistage process of boosting, reach program voltage (for example 8V), the output output program voltage of charge pump unit 101, selector 301 is under the triggering of described programming instruction, be communicated with the output of charge pump unit 101 and the programming incoming end of memory cell array 401, the output of charge pump unit 101 is exported program voltage to the programming incoming end of memory cell array 401, thereby finishes the process that memory data writes.
Similarly, in erase process, controller 500 to clock driver 203 wipe clock driver 202 and selector 301 sends erasing instruction, wipe clock driver 202 under the triggering of described programming instruction, send drive signal to charge pump unit 101, charge pump unit 101 is under the driving of wiping clock driver 202, through the multistage process of boosting, reach erasing voltage (for example 10V), the output output erasing voltage of charge pump unit 101, selector 301 is under the triggering of described erasing instruction, the incoming end of wiping that is communicated with the output of charge pump unit 101 and memory cell array 401, the output of charge pump unit 101 is exported erasing voltages to memory cell array 401, thereby finishes the process of memory erase data message.
Provide in the erase process of program voltage at programming incoming end in the prior art to little load, adopt the strong clock driver of driving force, because the loss of parasitic capacitance, the efficient of charge pump circuit during programming (ratio of power output and input power) is lower, is 10%.And in the technical program, clock driver comprise driving force big Mbus driver, driving force little wipe clock driver, the load of programming process is less, then adopt the less Mbus driver of driving force, owing to reduced the loss of parasitic capacitance, the efficient of charge pump improves greatly during programming, is 30%～40%.Charge pump circuit of the present invention can also have other embodiment, with reference to figure 5, shows the schematic diagram of the memory that comprises the another embodiment of charge pump circuit.The memory of present embodiment comprises: controller 501, clock driver 203, charge pump unit 101, memory cell array 401.
Present embodiment part same as the previously described embodiments repeats no more, and the difference of present embodiment and the foregoing description is:
Described programmed charges pump 103 links to each other with Mbus driver 201, and simultaneously, the output of described programmed charges pump 103 directly links to each other with the programming incoming end of memory cell array 401.
Describedly wipe charge pump 102 and wipe clock driver 202 and link to each other, simultaneously, the described output of wiping charge pump 102 directly links to each other with the incoming end of wiping of memory cell array 401.
In the programming process, under the driving of Mbus driver 201, programmed charges pump 103 reaches program voltage through the process of boosting, and to programming incoming end output program voltage; In the erase process, under the driving of wiping clock driver 202, wipe charge pump 102 and reach erasing voltage through the process of boosting, and to wiping incoming end output erasing voltage.
In the present embodiment, the load of programmed charges pump 103 outputs is greater than the load of wiping charge pump 102 outputs, and correspondingly, the driving force of described Mbus driver 201 is greater than the driving force of wiping clock driver 202.Because it is less relatively to wipe the driving force of clock driver 202, the size of wiping clock driver 202 is less, thereby the parasitic capacitance of wiping clock driver 202 is less, and then has reduced the power consumption in the erase process.
In the present embodiment, programmed charges pump 103 with wipe charge pump 102 respectively with the programming input of memory cell array 400 with wipe input and directly link to each other, need not to be communicated with charge pump and memory cell array by selector shown in the image pattern 4, thereby simplify the structure.
Need to prove, in the foregoing description, is example with the load of charge pump in the programming process greater than the load of charge pump in the erase process, but, the present invention is not limited thereto, because " programming " of memory cell array, " wipe " the mechanism difference, the load of charge pump may be less than the charge pump load in the erase process in the programming process, in this case, with the load of wiping incoming end as first kind load, with with the programming incoming end load as the second type load, correspondingly, wipe the driving force of the driving force of clock driver greater than the Mbus driver, those skilled in the art can make amendment according to the description of the foregoing description, distortion and replacement.
Need to prove, in the charge pump circuit provided by the invention, adopt the strong clock driver of driving force to be used to drive heavy load, adopt the weak clock driver of driving force to be used to drive little load.When selecting clock driver, can select to be applicable to the clock driver of described loading condition earlier according to the efficient of loading condition and clock driver.
To sum up, charge pump circuit provided by the invention comprises the Mbus driver and wipes clock driver, be used for when little load provides voltage, adopt the weak clock driver of driving force, and the weak clock driver of driving force is owing to adopt small size device, its parasitic capacitance is less, so be used for when little load provides voltage, required power consumption is smaller.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (8)
1. a charge pump circuit is characterized in that, comprising: clock driver and charge pump unit, and wherein, described charge pump unit is used for providing voltage to the first kind and the second type load under the driving of clock driver;
Described clock driver comprises first clock driver and second clock driver, and the driving force of described first clock driver is greater than the driving force of second clock driver, described first clock driver is used to drive charge pump unit provides voltage to first kind load, and described second clock driver is used to drive charge pump unit provides voltage to the second type load.
2. charge pump circuit as claimed in claim 1 is characterized in that, described charge pump unit is first charge pump that all links to each other with first clock driver and second clock driver.
3. charge pump circuit as claimed in claim 1, it is characterized in that, charge pump unit comprises: first charge pump that links to each other with first clock driver and second charge pump that links to each other with the second clock driver, described first charge pump provides voltage to first kind load under first clock driver drives, described second charge pump provides voltage to the second type load under the second clock driver drives.
4. memory that comprises claim 1 or 2 described charge pump circuits, described memory also comprises memory cell array, described clock driver is used to drive charge pump unit provides program voltage and erasing voltage to memory cell array respectively.
5. memory as claimed in claim 4, it is characterized in that, first clock driver drives charge pump unit and provides program voltage to the programming incoming end of memory cell array, and second clock driver drives charge pump unit provides erasing voltage to the incoming end of wiping of memory cell array.
6. memory as claimed in claim 4, it is characterized in that, first clock driver drives charge pump unit and provides erasing voltage to the incoming end of wiping of memory cell array, and second clock driver drives charge pump unit provides program voltage to the programming incoming end of memory cell array.
7. as the memory of charge pump circuit as described in the claim 4, it is characterized in that, described memory also comprises controller and selector, described controller is used for providing programming instruction or erasing instruction respectively to first clock driver and second clock driver, first, the second clock driver triggers charge pump unit respectively and provides program voltage or erasing voltage to memory cell array, described controller also provides programming instruction or erasing instruction to selector, described selector links to each other with charge pump unit and memory cell array, under the triggering of described programming instruction or erasing instruction, the programming incoming end of the output of corresponding connection charge pump unit and memory cell array or wipe incoming end.
8. memory that comprises the described charge pump circuit of claim 3, described memory also comprises controller, described controller is used for providing programming instruction to first clock driver and first charge pump, provides erasing instruction to the second clock driver and second charge pump; Perhaps, described controller is used for providing erasing instruction to first clock driver and first charge pump, provides programming instruction to the second clock driver and second charge pump.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010168837.9A CN102237788B (en) | 2010-04-29 | 2010-04-29 | Charge pump circuit and memory |
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|---|---|---|---|
| CN201010168837.9A CN102237788B (en) | 2010-04-29 | 2010-04-29 | Charge pump circuit and memory |
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| CN102237788A true CN102237788A (en) | 2011-11-09 |
| CN102237788B CN102237788B (en) | 2014-12-10 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137181A (en) * | 2013-02-25 | 2013-06-05 | 上海宏力半导体制造有限公司 | Memory, memory array programming method, and voltage supply system |
| CN103812332A (en) * | 2014-03-05 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Charge pump circuit and storage |
| CN104967307A (en) * | 2015-06-23 | 2015-10-07 | 北京兆易创新科技股份有限公司 | charge pump clock driving method and system |
| CN109842290A (en) * | 2017-11-24 | 2019-06-04 | 北京兆易创新科技股份有限公司 | A kind of high pressure bleeder circuit, charge pump circuit and NOR FLASH |
| CN112636587A (en) * | 2020-12-30 | 2021-04-09 | 深圳市芯天下技术有限公司 | Charge pump circuit and nonvolatile memory |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105551523B (en) * | 2015-12-10 | 2019-08-30 | 北京兆易创新科技股份有限公司 | Nand memory and its device for balancing the WL Voltage Establishment time |
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| US20040012436A1 (en) * | 2002-07-18 | 2004-01-22 | Pekny Theodore T. | Clock regulation scheme for varying loads |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137181A (en) * | 2013-02-25 | 2013-06-05 | 上海宏力半导体制造有限公司 | Memory, memory array programming method, and voltage supply system |
| CN103812332A (en) * | 2014-03-05 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Charge pump circuit and storage |
| CN103812332B (en) * | 2014-03-05 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | A kind of charge pump circuit and memory |
| CN104967307A (en) * | 2015-06-23 | 2015-10-07 | 北京兆易创新科技股份有限公司 | charge pump clock driving method and system |
| CN104967307B (en) * | 2015-06-23 | 2017-12-19 | 北京兆易创新科技股份有限公司 | The clock driving method and system of a kind of charge pump |
| CN109842290A (en) * | 2017-11-24 | 2019-06-04 | 北京兆易创新科技股份有限公司 | A kind of high pressure bleeder circuit, charge pump circuit and NOR FLASH |
| CN112636587A (en) * | 2020-12-30 | 2021-04-09 | 深圳市芯天下技术有限公司 | Charge pump circuit and nonvolatile memory |
| CN112636587B (en) * | 2020-12-30 | 2022-03-08 | 芯天下技术股份有限公司 | Charge pump circuit and nonvolatile memory |
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| CN102237788B (en) | 2014-12-10 |
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