CN102223143A - Clock signal protective device, clock signal protective method and clock detection compensating circuit - Google Patents
Clock signal protective device, clock signal protective method and clock detection compensating circuit Download PDFInfo
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Abstract
The invention discloses a clock signal protective device comprising an input clock detecting module, an output clock selecting module, an output clock detecting module and a clock compensation output module, wherein the input clock detecting module is used for detecting input clock and generating clock selection signals according to the detecting result; the output clock selecting module is used for determining the middle output clock according to the clock selecting signals; the output clock detecting module is used for detecting whether the middle output clock is normal; the clock compensation output module is used for repairing the middle output clock, carrying out output when the abnormality of the middle output clock is detected, and shifting and outputting the middle output clock when the normality of the middle output clock and the meeting of the prearranged clock period are detected. In the invention, the situations such as duty cycle, clock loss and deterioration can be quickly detected and repaired, and high stability and reliability of the clock signal can be ensured.
Description
Technical field
The present invention relates to circuit design field, particularly relate to method and a kind of clock detection compensating circuit of a kind of device of clock signal protection, the protection of a kind of clock signal.
Background technology
For digital communication network, it need provide the professional of multiple different application and guarantee the quality of miscellaneous service, from general service to intelligent value-added service, from voice to data, integrated service such as image, multiple business and deposit and make the clock problem of system seem more and more important.
The stable clock signal is the basis of various device operate as normal in the digital communication network, if there is not good clock signal, digital information just phenomenons such as error code, slip can occur inevitably in transmittance process, thereby causes the decline of communication quality.According to the difference of business, its influence degree is also different.For example, some needs the chip of clock, if the clock of input occurs discontinuous or disturbs, will cause the state machine confusion in this chip, and it is unusual that chip operation is occurred, even behind recovering clock signals, chip still can't be got back to normal operating conditions.If the function that this chip is responsible for is important, will cause the communication system operate as normal to have a strong impact on.
Be stability and the reliability of safeguarding clock signal, usually adopt clock signal device as shown in Figure 1 in the prior art, this device mainly comprises clock detection module 101 and clock selection module 102, wherein, described clock detection module is used for receiving input time (as the input clock f0 of Fig. 1, input clock f1) and the local reference clock (standby clock on the clock system integrated circuit board, identical with the frequency of input clock, but clock accuracy and stability will be worse than input clock, in system, can only use the short time, operating time generally is no more than 100 seconds), and to the clock of input at certain hour in the cycle (as 1000 clock cycle), according to local reference clock the clock number of input is added up, judge within a certain period of time, whether statistics is predetermined result, and corresponding output testing result (as testing result among Fig. 10 and testing result 1); Be specially, if then testing result is that input clock signal is normally indicated, if not, then testing result is the input clock signal faulty indication.
Described clock selection module 102 is used for input clock being switched, and exporting final output clock f by testing result (testing result 0 of input clock f0 as shown in Figure 1 and the testing result 1 of input clock f1).For example, if f0 road clock failure, f1 road clock is normal, then clock is switched to the f1 clock, simultaneously, and clock failure index signal outputting alarm; If the f1 clock is also undesired, just switch to local reference clock, simultaneously, clock failure index signal outputting alarm; If f0 road clock failure recovers, switching to f0 road clock so.
Yet there is following shortcoming in this prior art:
1, the clock detection module is just added up the clock number of input, because local reference clock and input clock are not same clock sources, input clock generally from the net of communication system synchronously or the timing reference input of degree of precision, clock accuracy is better than+/-4.6PPM (abbreviation of part per million, expression a few millionths), thereby the precision of local reference clock will be far below the precision of input clock, in this case, local reference clock and input clock frequency then can produce certain frequency departure (generally+/-50PPM about), therefore be greater than certain time period detection time, if loss of clock, testing result can not very fast indication so.In this process, clock selection module still will be selected this road clock output, will cause output clock f to lose a lot of clock cycle (if the detection use is that 1000 clock cycle are as judging thresholding, export so with regard to 1000 clock cycle of deterioration), clock quality is being required strict chip, this process will cause this chip operation unusual, and also can't operate as normal after clock recovery, consequence is very serious, and this allows to occur in system anything but;
2, present, the chip that much needs clock signal has very strict demand (general 40-60%) to the duty ratio of input clock, but prior art can't detect the variation of duty ratio;
3, existing design can't directly detect the burr of input clock, and method that can only be by statistics clock number is through just reflecting after a while.Before reflecting, possible system is fault.In addition, testing circuit also can not detect the situation of a small amount of burr.
Therefore; need the urgent technical problem that solves of those skilled in the art to be exactly at present: the device and method that how can propose a kind of clock signal protection with innovating; with fast detecting and repair the situation of duty ratio, loss of clock and deterioration, guarantee the high stability and the reliability of clock signal.
Summary of the invention
Technical problem to be solved by this invention provides device, method and a kind of clock detection compensating circuit of a kind of clock signal protection, with fast detecting and repair the situation of duty ratio, loss of clock and deterioration, guarantees the high stability and the reliability of clock signal.
In order to solve the problems of the technologies described above, the embodiment of the invention discloses a kind of device of clock signal protection, comprising:
The input clock detection module is used to detect input clock, and produces clock selection signal according to testing result;
The output clock selection module is used for determining middle output clock according to described clock selection signal;
Output clock detection module, whether be used to detect described middle output clock normal;
The clock compensation output module is used in the middle of detect the output clock and occurs when unusual, repairs described in the middle of the output clock line output of going forward side by side; And, in the middle of detect the output clock recovery normal and when satisfying default clock cycle, switch to this centre and export clock and export.
Preferably, described output clock detection module comprises:
Array writes submodule, is used for according to high frequency reference clock the signal data of exporting clock in the middle of described being write array continuously;
The data parsing submodule is used to judge whether the current array value that writes meets normal value, if judge that then described middle output clock is normal; If not, judge that then described middle output clock is unusual.
Preferably, described array writes submodule and comprises d type flip flop assembly and array logic circuit, wherein, comprises a plurality of memory cell in the described array logic circuit, and the length of described memory cell is determined by output clock and high frequency reference clock in the middle of current; The number of d type flip flop is according to the length relative set of described memory cell in the described d type flip flop assembly, the data terminal of d type flip flop connects intermediate output clock signal, output is connected to memory cell corresponding in the data terminal of next d type flip flop and the array logic circuit, and clock end connects the high frequency reference clock signal; Described data parsing submodule is a comparison circuit;
The signal data of output clock is shifted continuously by high frequency reference clock in the middle of described, writes in the memory cell of array logic circuit correspondence, generates corresponding array value.
Preferably, described clock compensation output module comprises:
The local clock switching submodule is used for that the output clock occurs when unusual in the middle of present clock period detects, the next clock cycle adopt local reference clock repair or replace described in the middle of the laggard line output of output clock;
The clock recovery processing sub, it is normal and when satisfying at least three clock cycle to be used in the middle of detect the output clock recovery, switch to described recovery normal in the middle of the output clock export.
Preferably, described device also comprises:
The fault statistics module is used to add up invalid testing result of described input clock and/or the unusual testing result of described middle output clock.
Preferably, described input clock has multichannel, and described input clock detection module comprises:
The statistics submodule is used for the number according to input clock in the local reference clock statistics certain hour, if the number of described input clock then triggers normal output sub-module in presetting range; Otherwise, trigger unusual output sub-module;
Normal output sub-module is used to export the effective testing result of input clock, and produces first clock selection signal, and described first clock selection signal is for selecting the signal of this road input clock output;
Unusual output sub-module is used to export the invalid testing result of input clock, blocks this road input clock, and produces second clock selection signal, and it is the signal that switches to effective input clock that described second clock is selected signal.
Preferably, described array logic circuit is a kind of complex programmable logic device (CPLD) or a kind of on-site programmable gate array FPGA.
The embodiment of the invention also discloses a kind of method of clock signal protection, comprising:
Detect input clock, and produce clock selection signal according to testing result;
Determine middle output clock according to described clock selection signal;
Detect described in the middle of the output clock whether normal, if in the middle of detecting the output clock occur unusual, then repair described in the middle of the output clock line output of going forward side by side; Also satisfy the default clock cycle if the output clock recovery is normal in the middle of detecting, then switch to this centre output clock and export.
Preferably, whether normal step comprises to export clock in the middle of the described detection:
Write the signal data of exporting clock in the middle of described in the array continuously according to high frequency reference clock;
Judge whether the current array value that writes meets normal value, if judge that then described middle output clock is normal; If not, judge that then described middle output clock is unusual.
Preferably, the go forward side by side step of line output of output clock was in the middle of repairing when unusual appearred in the output clock in the middle of described the detecting:
The output clock occurs when unusual in the middle of present clock period detects, the next clock cycle adopt local reference clock repair or replace described in the middle of the laggard line output of output clock;
The output clock recovery is normal and switch to this centre when satisfying default clock cycle and export the step that clock exports and be in the middle of described the detecting:
In the middle of detecting, export when clock recovery is normal also satisfies at least three clock cycle, switch to the normal middle output clock of described recovery and export.
Preferably, described method also comprises:
Add up invalid testing result of described input clock and/or the unusual testing result of described middle output clock.
Preferably, described input clock has multichannel, and described detection input clock also comprises according to the step that testing result produces clock selection signal;
Number according to input clock in the local reference clock statistics certain hour, if the number of described input clock is in presetting range, then export the effective testing result of input clock, and producing first clock selection signal, described first clock selection signal is for selecting the signal of this road input clock output; Otherwise the invalid testing result of output input clock is blocked this road input clock, and produces second clock selection signal, and it is the signal that switches to effective input clock that described second clock is selected signal.
The embodiment of the invention also discloses a kind of clock detection compensating circuit, comprising:
The array logic circuit comprises a plurality of memory cell, and the length of described memory cell is determined by output clock and high frequency reference clock in the middle of current;
The d type flip flop assembly, comprise a plurality of d type flip flops according to the length relative set of described memory cell, the data terminal of described d type flip flop connects intermediate output clock signal, output is connected to memory cell corresponding in the data terminal of next d type flip flop and the array logic circuit, and clock end connects the high frequency reference clock signal;
The signal data of output clock is shifted continuously by high frequency reference clock in the middle of described, writes in the memory cell of array logic circuit correspondence, generates corresponding array value;
Comparison circuit is used to judge whether the current array value that writes meets normal value, if judge that then described middle output clock is normal; If not, judge that then described middle output clock is unusual;
Decision circuitry is used in the middle of detect the output clock and occurs producing first clock signal when unusual; And, in the middle of detect the output clock recovery normal and when satisfying default clock cycle, produce second clock signal; Described first clock signal is local reference clock signal; Described second clock signal is for recovering normal intermediate output clock signal;
Select circuit, connect local reference clock signal and middle output clock, be used for exporting local reference clock according to described first clock signal; And, recover normal middle output clock according to described second clock signal output.
Compared with prior art, the present invention has the following advantages:
At first, the mode that the present invention adopts array value to resolve, can be simultaneously, fast detecting output clock (in the embodiment of the invention in the middle of output clock) situation of duty ratio, loss of clock and deterioration in output procedure, and the clock of damage in time repaired, to realize the seamless switching of clock; And, adopt anti-shake mechanism after this output clock recovery is normal, guarantee its stable through some cycles, just switch to this clock and export, thereby effectively guaranteed the high stability and the reliability of clock signal; The present invention needing in the digital communicating field can be widely used in the equipment of high stable clock, can improve the stability and the accuracy of professional transmission efficiently.
Moreover structure of the present invention is flexible, can or carry out multiple combination according to concrete needs adjustment design, and circuit cost is lower.
Description of drawings
Fig. 1 is the structure chart of clock signal protective device commonly used in the prior art;
Fig. 2 is the structured flowchart of a kind of clock signal protective device embodiment of the present invention;
Fig. 3 a, Fig. 3 b and Fig. 3 c are the waveform schematic diagrames of a kind of middle output clock abnormal conditions of the present invention;
Fig. 4 is the structure chart of the physical circuit example of a kind of middle output clock detection module of the present invention;
Fig. 5 is the structure chart of the physical circuit example of a kind of clock compensation output module of the present invention;
Fig. 6 uses the waveform schematic diagram that the present invention carries out clock compensation;
Fig. 7 is the flow chart of the method embodiment 1 of a kind of clock signal protection of the present invention;
Fig. 8 is the flow chart of the method embodiment 2 of a kind of clock signal protection of the present invention;
Fig. 9 is the structure chart of a kind of clock detection compensating circuit of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
One of core idea of the embodiment of the invention is whether the output clock breaks down in the middle of the fast detecting in output procedure, if then in time repair described middle output clock, and the clock after the described reparation is exported as final output clock; Clock recovery is normal also stablizes some cycles if export in the middle of detecting, and then switches to this centre output clock, and will recover normal middle output clock and export as final output clock.
With reference to figure 2, show the structured flowchart of the device embodiment of a kind of clock signal protection of the present invention, specifically can comprise with lower module:
Input clock detection module 201 is used to detect input clock, and produces clock selection signal according to testing result;
Output clock selection module 202 is used for determining middle output clock according to described clock selection signal;
Output clock detection module 203, whether be used to detect described middle output clock normal;
Clock compensation output module 204 is used in the middle of detect the output clock and occurs when unusual, repairs described in the middle of the output clock, and the clock after will repairing is exported as final output clock; And, in the middle of detect the output clock recovery normal and when satisfying default clock cycle, switch to this centre output clock, the normal middle clock of exporting of this recoverys is exported as final output clock.
In specific implementation, described input clock has multichannel usually, and in a preferred embodiment of the present invention, described input clock detection module 201 specifically can comprise following submodule:
The statistics submodule is used for the number according to input clock in the local reference clock statistics certain hour, if the number of described input clock then triggers normal output sub-module in presetting range; Otherwise, trigger unusual output sub-module;
Normal output sub-module is used to export the effective testing result of input clock, and produces first clock selection signal, and described first clock selection signal is for selecting the signal of this road input clock output;
Unusual output sub-module is used to export the invalid testing result of input clock, blocks this road input clock, and produces second clock selection signal, and it is the signal that switches to effective input clock that described second clock is selected signal.
Supposing currently has two-way input clock f0 and f1 to insert input clock detection module a and b respectively, and simultaneously, described input clock detection module a also is connected local reference clock with b.In this case, input clock detection module a can be according to the number of the input clock f0 in the local reference clock statistics certain hour that inserts, and input clock detection module b can be according to the number of the input clock f1 in the local reference clock statistics certain hour that inserts.If the clock number in presetting range, thinks that then input clock is normal; Otherwise think that input clock is unusual.
For example, if the input clock that detects is 10MHz, local reference clock is 10MHz, local reference clock precision is lower than+/-100PPM, the input clock frequency excursion be+/-10PPM, guarantee that clock stable monitors.In this case, the deviation range that input clock and local reference clock can be set is, be no more than+/-200PPM; And it is 100ms that the detection statistics time is set, and then in this time range, statistical value surpasses+/-200 countings, just thinks that input clock breaks down, and in this scope, just thinks that input clock is normal.
In practice,, then can directly select this road clock to be middle output clock, promptly can produce the clock selection signal (first clock selection signal) of selecting this road input clock output if current input clock is normal; If current input clock is unusual, then do not select current input clock, export (second clock selection signal) and select to switch to normal input clock, for example, if current input clock f0 breaks down, and f1 is normal, and the clock selection signal of Chan Shenging is for selecting output f1 road clock signal so.
Output clock selection module 202 can be determined current middle output clock f according to the clock selection signal that described input clock detection module 201 produces, as is input clock f0, input clock f1 or local reference clock.
The statistics of clock number makes because the input clock detection module is based on the detection principle of input clock, thereby, middle output clock f (prolonging and use example, may be input clock f0 or input clock f1) in output procedure, the situation of following several faults often may occur:
1) detecting one road input clock has fault, switch to another road clock after, some clock cycle have been lost in the centre; Specifically can be with reference to two kinds of waveforms shown in the figure 3a, output clock f is input clock f0 and when breaking down in the middle of detecting, the moment that switches to input clock f1 can the deterioration clock.
2) input clock signal is a differential signal, but a utmost point (negative or positive electrode) short circuit is arranged or opens circuit, and cause the duty ratio deterioration, but it is unusual not detect input clock, continues the original clock of output; Specifically can with reference to shown in the figure 3b the duty ratio deterioration appears when middle output clock f is input clock f0 and the time two kinds of waveforms.
3) because the cable of electromagnetic interference or plug clock transfer causes clock to have burr, it is the clock deterioration, but the deterioration time is shorter, it is unusual not detect clock, continue the original clock of output, specifically can in the middle of shown in the figure 3c, export the oscillogram that occurs clock deterioration (burr) when clock f is input clock f0.
Described output clock detection module 203 promptly is used to detect the situation of above-mentioned middle output clock failure.In a preferred embodiment of the present invention, described output clock detection module 203 specifically can comprise following submodule:
Array writes submodule, is used for according to high frequency reference clock the signal data of exporting clock in the middle of described being write array continuously;
The data parsing submodule is used to judge whether the current array value that writes meets normal value, if judge that then described middle output clock is normal; If not, judge that then described middle output clock is unusual.
For making those skilled in the art understand the present invention better, below provide a kind of physical circuit example of exporting the clock detection module.
With reference to figure 4, described output clock detection module specifically can comprise d type flip flop assembly 41, array logic circuit 42 and comparison circuit 43;
Wherein, comprise a plurality of memory cell in the described array logic circuit 42, be used to store the value that d type flip flop writes under the effect of high frequency reference clock, the left side of array can be set to 0, the right can be set to the n position, preferably, described array logic circuit can adopt complex programmable logic device (CPLD) or on-site programmable gate array FPGA to realize.
Need to prove that the length of memory cell is determined according to output clock and high frequency reference clock in the middle of current in the described array.
The number of d type flip flop (DFF) is according to the length relative set of described memory cell in the described d type flip flop assembly 41, output clock f in the middle of the data terminal of d type flip flop (D end) connects, output (Q end) is connected to memory cell corresponding in the data terminal of next d type flip flop and the array logic circuit 42, and clock end connects the high frequency reference clock signal;
In concrete the application, the signal data of described middle output clock will be shifted continuously by high frequency reference clock, write in the memory cell of array logic circuit correspondence, thereby generate corresponding array value.
43 of comparison circuits are mainly used in resolves the content of array, by analyzing the content in the array, judge clock whether continuously, whether duty ratio correct, and exports judged result.
For example, the reference frequency of output clock f is 10MHz in the middle of the current detection, and high frequency reference clock is 250MHz, and can obtain so between every of the array is 4ns at interval, during n=25, can adorn next 10MHz clock; During n=14, can adorn 0.6 clock cycle; The redundant error of clock is taken into account, design n=14, then the normal value of array should be:
The array normal value (0,1 ..., 10)=(00000000000);
The array normal value (0,1 ..., 10)=(10000000000);
The array normal value (0,1 ..., 10)=(11000000000);
The array normal value (0,1 ..., 10)=(11100000000);
The array normal value (0,1 ..., 10)=(11110000000);
The array normal value (0,1 ..., 10)=(11111000000);
The array normal value (0,1 ..., 10)=(11111100000);
The array normal value (0,1 ..., 10)=(11111110000);
The array normal value (0,1 ..., 10)=(11111111000);
The array normal value (0,1 ..., 10)=(11111111100);
The array normal value (0,1 ..., 10)=(11111111110);
The array normal value (0,1 ..., 10)=(11111111111);
The array normal value (0,1 ..., 10)=(01111111111);
The array normal value (0,1 ..., 10)=(00111111111);
The array normal value (0,1 ..., 10)=(00011111111);
The array normal value (0,1 ..., 10)=(00001111111);
The array normal value (0,1 ..., 10)=(00001111111);
The array normal value (0,1 ..., 10)=(00000111111);
The array normal value (0,1 ..., 10)=(00000011111);
The array normal value (0,1 ..., 10)=(00000001111);
The array normal value (0,1 ..., 10)=(00000000111);
The array normal value (0,1 ..., 10)=(00000000011);
The array normal value (0,1 ..., 10)=(00000000001);
The array normal value (0,1 ..., 10)=(00000000000);
Comparison circuit can judge fast by contrast current number class value and above-mentioned array normal value whether current middle output clock occurs unusually.
For example, if the not corresponding above-mentioned normal value of array value represents that then clock has the clock greater than 4ns to disturb, and the situation of clock deterioration promptly occurs.
Or as, if array value is:
Array value (0,1 ..., 14)=(000000000000000);
Array value (0,1 ..., 14)=(111111111111111).
Illustrate that then clock duty cycle surpasses the scope of 40-60% (duty ratio deterioration), or the situation of loss of clock occurs.
Certainly, the physical circuit of above-mentioned output clock detection module is only as a kind of example, and it all is feasible that those skilled in the art adopt other circuit to realize, the present invention need not this to be limited.
The present invention adopts a kind of anti-shake mechanism to handle for detecting unusual middle output clock, switches to avoid clock table tennis, causes the instability of clock.Particularly, by an anti-shake thresholding (comprise the clock cycle of switching when unusual and recover the normal back stable clock cycle) is set, the output clock occurs when unusual in the middle of detecting, and repairs clock through the very short clock cycle (as 1 cycle); But in the middle of unusual the output clock recover again normal after, need stablize one period clock cycle (as 3-10 clock cycle) after, just can be switched.
As a kind of example of concrete application, described clock compensation output module 204 specifically can comprise following submodule:
The local clock switching submodule is used for that the output clock occurs when unusual in the middle of present clock period detects, the next clock cycle adopt local reference clock repair or replace described in the middle of the laggard line output of output clock;
The clock recovery processing sub, it is normal and when satisfying at least three clock cycle to be used in the middle of detect the output clock recovery, switch to described recovery normal in the middle of the output clock export.
For making those skilled in the art understand the present invention better, below provide a kind of physical circuit example of clock compensation output module.
With reference to figure 5, described clock compensation output module can comprise decision circuitry 51 and select circuit 52, be provided with anti-shake threshold value in the described decision circuitry 51, its input is connected with clock output detection module (not shown), trigger according to middle output clock anomalous signals, through the judgement of anti-shake thresholding, determine to produce the selection signal of which clock, and export this signal to selection circuit 52; The input of described selection circuit 52 connects local reference clock and middle output clock f, is used for the clock selection signal according to decision circuitry output, selects corresponding clock fout to export.
For example, if output clock f (selecting the input clock f0 of output) occurs unusual in the middle of present clock period detects, switch to local reference clock in the next clock cycle so at once, this moment, local reference clock just substituted the clock of fault, the signal of the compensating missing clock shown in second section waveform among Fig. 6, and handle signal after duty ratio deterioration or the clock deterioration (burr) shown in the 3rd section waveform; When failing clock f0 recover normal after, to judge input clock soon normal for decision circuitry so, stablize certain clock cycle through anti-shake thresholding so after, switching at present normally again rapidly, clock f0 exports.
By processing of the present invention, equipment clock switching or interference in all cases, can although in compensation process, have small deviation, can not exert an influence by using local reference clock polishing or substituting the clock that damages to device chip.
A kind of comparatively extreme situation also might appear in the reality, be that current multichannel input clock all breaks down, all break down as above-mentioned input clock f0 and f1, this situation is the situation of losing the clock time endless shown in Fig. 3 a, in this case, use the invention process regular meeting and continue to adopt local reference clock to compensate, thereby can effectively guarantee the effectively stable of clock signal.
As another preferred embodiment, in the clock signal protective device of the present invention the fault statistics module can also be set, be used to add up invalid testing result of described input clock and/or the unusual testing result of described middle output clock.
Particularly, the input of described fault statistics module can be connected with input clock detection module 201 and output clock detection module 203, input clock testing result and the middle change frequency of exporting the unusual testing result of clock to input are added up, and the output statistics; With thinking that inquiring about in the future failure cause stays to detect an interface, promptly as the test maintaining interface of this circuit.
Need to prove, in embodiments of the present invention, input clock is only provided the example of two-way, yet what those skilled in the art were easy to expect is, under the situation of multichannel input clock, the application of the concrete scheme of the present invention all is feasible, so the application of any multichannel input clock all is embodiment of the present invention, but this specification has not just been given unnecessary details at this as space is limited.
With reference to figure 7, show the flow chart of the method embodiment 1 of a kind of clock signal protection of the present invention, specifically can may further comprise the steps:
Step 701, detection input clock, and according to testing result generation clock selection signal;
Output clock in the middle of step 702, the described clock selection signal of foundation are determined;
Step 703, detect described in the middle of the output clock whether normal, if in the middle of detecting the output clock occur unusual, then repair described in the middle of the output clock line output of going forward side by side; Also satisfy the default clock cycle if the output clock recovery is normal in the middle of detecting, then switch to this centre output clock and export.
In specific implementation, described input clock has multichannel usually, and in a preferred embodiment of the present invention, described step 701 can comprise following substep:
The number of input clock in substep S1, the local reference clock statistics of the foundation certain hour, if the number of described input clock is in presetting range, then export the effective testing result of input clock, and producing first clock selection signal, described first clock selection signal is for selecting the signal of this road input clock output; Otherwise the invalid testing result of output input clock is blocked this road input clock, and produces second clock selection signal, and it is the signal that switches to effective input clock that described second clock is selected signal.
For conveniently circuit being tested and being safeguarded, in embodiments of the present invention, can also may further comprise the steps:
Add up invalid testing result of described input clock and/or the unusual testing result of described middle output clock.
With reference to figure 8, show the flow chart of the method embodiment 2 of a kind of clock signal protection of the present invention, specifically can may further comprise the steps:
Output clock in the middle of step 802, the described clock selection signal of foundation are determined;
Because method embodiment of the present invention is substantially corresponding to aforesaid device embodiment, so not detailed part in the description of present embodiment can just not given unnecessary details at this referring to the related description in the previous embodiment.
Need to prove, for aforesaid each method embodiment, for simple description, so it all is expressed as a series of combination of actions, but those skilled in the art should know, the present invention is not subjected to the restriction of described sequence of movement, because according to the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in the specification all belongs to preferred embodiment, and related action and module might not be that the present invention is necessary.
With reference to figure 9, show the structure chart of a kind of clock detection compensating circuit of the present invention, specifically can comprise:
Array logic circuit 91 comprises a plurality of memory cell, and the length of described memory cell is determined by output clock and high frequency reference clock in the middle of current; Be used to store the value that d type flip flop writes under the effect of high frequency reference clock.In practice, the left side of array can be set to 0, and the right can be set to the n position, and preferably, described array logic circuit can adopt complex programmable logic device (CPLD) or on-site programmable gate array FPGA to realize.
D type flip flop assembly 92, comprise a plurality of d type flip flops according to the length relative set of described memory cell, the data terminal of described d type flip flop connects intermediate output clock signal, output is connected to memory cell corresponding in the data terminal of next d type flip flop and the array logic circuit, and clock end connects the high frequency reference clock signal.
In concrete the application, the signal data of described middle output clock will be shifted continuously by high frequency reference clock, write in the memory cell of array logic circuit correspondence, thereby generate corresponding array value.
Comparison circuit 93 is used to judge whether the current array value that writes meets normal value, if judge that then described middle output clock is normal; If not, judge that then described middle output clock is unusual.
The measuring ability that whether the output clock broke down in the middle of above-mentioned array logic circuit 91, d type flip flop assembly 92 and comparison circuit 93 were mainly used in and finish.
Decision circuitry 94 is used in the middle of detect the output clock and occurs producing first clock signal when unusual; And, in the middle of detect the output clock recovery normal and when satisfying default clock cycle, produce second clock signal; Described first clock signal is local reference clock signal; Described second clock signal is for recovering normal intermediate output clock signal.
Select circuit 95, connect local reference clock signal and middle output clock, be used for according to the local reference clock of described first clock signal output as final output clock fout; And, export as the normal middle output clock of the recovery of final output clock fout according to described second clock signal.
Clock repair function when the output clock broke down in the middle of above-mentioned decision circuitry 94 and selection circuit 95 were mainly used in and finish.
Because present embodiment is corresponding to the description of aforesaid device embodiment appropriate section, so not detailed part in the description of present embodiment can just repeat no more at this referring to the related description in the previous embodiment.
Need to prove, among the present invention, relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint and have the relation of any this reality or in proper order between these entities or the operation.And, term " comprises " or its any other variant is intended to contain comprising of nonexcludability, thereby make and comprise that process, method, article or the equipment of a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or also be included as this process, method, article or equipment intrinsic key element.Do not having under the situation of more restrictions, the key element that limits by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
More than method and a kind of clock detection compensating circuit of the device of a kind of clock signal protection provided by the present invention, the protection of a kind of clock signal is described in detail, used specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (13)
1. the device of a clock signal protection is characterized in that, comprising:
The input clock detection module is used to detect input clock, and produces clock selection signal according to testing result;
The output clock selection module is used for determining middle output clock according to described clock selection signal;
Output clock detection module, whether be used to detect described middle output clock normal;
The clock compensation output module is used in the middle of detect the output clock and occurs when unusual, repairs described in the middle of the output clock line output of going forward side by side; And, in the middle of detect the output clock recovery normal and when satisfying default clock cycle, switch to this centre and export clock and export.
2. device as claimed in claim 1 is characterized in that, described output clock detection module comprises:
Array writes submodule, is used for according to high frequency reference clock the signal data of exporting clock in the middle of described being write array continuously;
The data parsing submodule is used to judge whether the current array value that writes meets normal value, if judge that then described middle output clock is normal; If not, judge that then described middle output clock is unusual.
3. device as claimed in claim 2, it is characterized in that described array writes submodule and comprises d type flip flop assembly and array logic circuit, wherein, comprise a plurality of memory cell in the described array logic circuit, the length of described memory cell is determined by output clock and high frequency reference clock in the middle of current; The number of d type flip flop is according to the length relative set of described memory cell in the described d type flip flop assembly, the data terminal of d type flip flop connects intermediate output clock signal, output is connected to memory cell corresponding in the data terminal of next d type flip flop and the array logic circuit, and clock end connects the high frequency reference clock signal; Described data parsing submodule is a comparison circuit;
The signal data of output clock is shifted continuously by high frequency reference clock in the middle of described, writes in the memory cell of array logic circuit correspondence, generates corresponding array value.
4. as claim 1,2 or 3 described devices, it is characterized in that described clock compensation output module comprises:
The local clock switching submodule is used for that the output clock occurs when unusual in the middle of present clock period detects, the next clock cycle adopt local reference clock repair or replace described in the middle of the laggard line output of output clock;
The clock recovery processing sub, it is normal and when satisfying at least three clock cycle to be used in the middle of detect the output clock recovery, switch to described recovery normal in the middle of the output clock export.
5. device as claimed in claim 1 is characterized in that, also comprises:
The fault statistics module is used to add up invalid testing result of described input clock and/or the unusual testing result of described middle output clock.
6. device as claimed in claim 1 is characterized in that described input clock has multichannel, and described input clock detection module comprises:
The statistics submodule is used for the number according to input clock in the local reference clock statistics certain hour, if the number of described input clock then triggers normal output sub-module in presetting range; Otherwise, trigger unusual output sub-module;
Normal output sub-module is used to export the effective testing result of input clock, and produces first clock selection signal, and described first clock selection signal is for selecting the signal of this road input clock output;
Unusual output sub-module is used to export the invalid testing result of input clock, blocks this road input clock, and produces second clock selection signal, and it is the signal that switches to effective input clock that described second clock is selected signal.
7. device as claimed in claim 3 is characterized in that, described array logic circuit is a kind of complex programmable logic device (CPLD) or a kind of on-site programmable gate array FPGA.
8. the method for a clock signal protection is characterized in that, comprising:
Detect input clock, and produce clock selection signal according to testing result;
Determine middle output clock according to described clock selection signal;
Detect described in the middle of the output clock whether normal, if in the middle of detecting the output clock occur unusual, then repair described in the middle of the output clock line output of going forward side by side; Also satisfy the default clock cycle if the output clock recovery is normal in the middle of detecting, then switch to this centre output clock and export.
9. method as claimed in claim 8 is characterized in that, whether normal step comprises the output clock in the middle of the described detection:
Write the signal data of exporting clock in the middle of described in the array continuously according to high frequency reference clock;
Judge whether the current array value that writes meets normal value, if judge that then described middle output clock is normal; If not, judge that then described middle output clock is unusual.
10. method as claimed in claim 8 or 9 is characterized in that, the go forward side by side step of line output of output clock was in the middle of repairing when unusual appearred in the output clock in the middle of described the detecting:
The output clock occurs when unusual in the middle of present clock period detects, the next clock cycle adopt local reference clock repair or replace described in the middle of the laggard line output of output clock;
The output clock recovery is normal and switch to this centre when satisfying default clock cycle and export the step that clock exports and be in the middle of described the detecting:
In the middle of detecting, export when clock recovery is normal also satisfies at least three clock cycle, switch to the normal middle output clock of described recovery and export.
11. method as claimed in claim 8 is characterized in that, also comprises:
Add up invalid testing result of described input clock and/or the unusual testing result of described middle output clock.
12. method as claimed in claim 8 is characterized in that, described input clock has multichannel, and described detection input clock also comprises according to the step that testing result produces clock selection signal;
Number according to input clock in the local reference clock statistics certain hour, if the number of described input clock is in presetting range, then export the effective testing result of input clock, and producing first clock selection signal, described first clock selection signal is for selecting the signal of this road input clock output; Otherwise the invalid testing result of output input clock is blocked this road input clock, and produces second clock selection signal, and it is the signal that switches to effective input clock that described second clock is selected signal.
13. a clock detection compensating circuit is characterized in that, comprising:
The array logic circuit comprises a plurality of memory cell, and the length of described memory cell is determined by output clock and high frequency reference clock in the middle of current;
The d type flip flop assembly, comprise a plurality of d type flip flops according to the length relative set of described memory cell, the data terminal of described d type flip flop connects intermediate output clock signal, output is connected to memory cell corresponding in the data terminal of next d type flip flop and the array logic circuit, and clock end connects the high frequency reference clock signal;
The signal data of output clock is shifted continuously by high frequency reference clock in the middle of described, writes in the memory cell of array logic circuit correspondence, generates corresponding array value;
Comparison circuit is used to judge whether the current array value that writes meets normal value, if judge that then described middle output clock is normal; If not, judge that then described middle output clock is unusual;
Decision circuitry is used in the middle of detect the output clock and occurs producing first clock signal when unusual; And, in the middle of detect the output clock recovery normal and when satisfying default clock cycle, produce second clock signal; Described first clock signal is local reference clock signal; Described second clock signal is for recovering normal intermediate output clock signal;
Select circuit, connect local reference clock signal and middle output clock, be used for exporting local reference clock according to described first clock signal; And, recover normal middle output clock according to described second clock signal output.
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| CN2010101480559A CN102223143A (en) | 2010-04-16 | 2010-04-16 | Clock signal protective device, clock signal protective method and clock detection compensating circuit |
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| CN2010101480559A CN102223143A (en) | 2010-04-16 | 2010-04-16 | Clock signal protective device, clock signal protective method and clock detection compensating circuit |
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| CN2010101480559A Pending CN102223143A (en) | 2010-04-16 | 2010-04-16 | Clock signal protective device, clock signal protective method and clock detection compensating circuit |
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| CN103051493A (en) * | 2012-12-13 | 2013-04-17 | 中兴通讯股份有限公司 | Service clock determination method and device and packet transport network equipment |
| CN105892560A (en) * | 2016-03-29 | 2016-08-24 | 杭州和利时自动化有限公司 | Clock detection method and system used for embedded system |
| WO2016141766A1 (en) * | 2015-03-09 | 2016-09-15 | 国核自仪系统工程有限公司 | Fpga clock signal self-detection method |
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| CN112769417A (en) * | 2019-11-01 | 2021-05-07 | 雅特力科技(重庆)有限公司 | Clock fault detector |
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| CN103051493A (en) * | 2012-12-13 | 2013-04-17 | 中兴通讯股份有限公司 | Service clock determination method and device and packet transport network equipment |
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| CN106776244A (en) * | 2017-03-10 | 2017-05-31 | 郑州云海信息技术有限公司 | A kind of server clock failure automatic detection repair system and method |
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| CN109687866A (en) * | 2018-12-24 | 2019-04-26 | 中国电子科技集团公司第五十八研究所 | A kind of compensation device ensureing PLL output clock |
| CN112769417A (en) * | 2019-11-01 | 2021-05-07 | 雅特力科技(重庆)有限公司 | Clock fault detector |
| CN112769417B (en) * | 2019-11-01 | 2022-05-20 | 雅特力科技(重庆)有限公司 | Clock fault detector |
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| WO2022110235A1 (en) * | 2020-11-30 | 2022-06-02 | 华为技术有限公司 | Chip and clock detection method |
| CN113448381A (en) * | 2021-05-28 | 2021-09-28 | 山东英信计算机技术有限公司 | CPLD working clock keeping method, system, storage medium and device |
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Application publication date: 20111019 |