CN102194717A - 半导体器件和在半导体管芯周围形成绝缘层的方法 - Google Patents

半导体器件和在半导体管芯周围形成绝缘层的方法 Download PDF

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CN102194717A
CN102194717A CN2011100556324A CN201110055632A CN102194717A CN 102194717 A CN102194717 A CN 102194717A CN 2011100556324 A CN2011100556324 A CN 2011100556324A CN 201110055632 A CN201110055632 A CN 201110055632A CN 102194717 A CN102194717 A CN 102194717A
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insulating barrier
semiconductor element
sealant
scribing block
semiconductor
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CN102194717B (zh
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林耀剑
陈康
方建敏
X·冯
X·包
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及半导体器件和在半导体管芯周围形成绝缘层的方法。多个半导体管芯被安装到临时载体。密封剂被沉积在半导体管芯和载体上。密封剂的一部分被指定作为管芯之间的划片街区，且密封剂的一部分被指定作为围绕密封剂的周界的衬底边缘。除去载体。第一绝缘层形成在管芯、划片街区和衬底边缘上。第一导电层形成在第一绝缘层上。第二绝缘层形成在第一导电层和第一绝缘层上。通过第一绝缘层和划片街区来单体化密封剂以分离半导体管芯。通道或网状图案可以形成在划片街区的相对侧的第一绝缘层中，或者第一绝缘层覆盖半导体管芯周围的模塑区和整个划片街区。

Description

半导体器件和在半导体管芯周围形成绝缘层的方法
技术领域
本发明总体上涉及半导体器件，并且更具体地说涉及半导体器件和在半导体管芯周围形成绝缘层的方法。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池、以及数字微镜器件（DMD）。
半导体器件执行多种功能，例如高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流（base current）或者通过掺杂工艺来操纵（manipulated）它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构（包括双极和场效应晶体管）控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构（包括电阻器、电容器、和电感器）产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化（singulating）单个管芯并且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占地面积（footprint），其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的管芯的前端工艺可以实现更小的管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占地面积的半导体器件封装。
图1a示出具有多个形成在衬底11上并且被划片街区14和晶片边缘16分开的半导体管芯12的常规半导体晶片10。接触焊盘18和介电层20形成在半导体管芯12的有源表面22上。钝化层24形成在介电层20上。然而，被指定用于单体化的划片街区14和晶片边缘16缺乏钝化。图1b示出在划片街区14和晶片边缘16上缺少的钝化层24的顶视图。再分布层（RDL）28形成在钝化层24上以扩展接触焊盘18的电连接。钝化层30形成在钝化层24和RDL 28上。凸块32至少部分地形成在模塑区34上并且电连接到RDL 28。在扇出型晶片级芯片规模封装（FO-WLCSP）中的边缘焊盘易于具有不稳定的接触电阻，尤其当在PVD中形成时。另外，在PVD中从FO－WLCSP的模塑区34除气影响氧化物刻蚀中的等离子体稳定性是已知的。
发明内容
存在对在FO－WLCSP中在氧化物刻蚀期间稳定的接触电阻和等离子体的需要。因此，在一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供临时载体，安装具有面向临时载体的接触焊盘的多个半导体管芯，以及在半导体管芯和临时载体上沉积密封剂。密封剂的一部分被指定作为半导体管芯之间的划片街区，并且密封剂的一部分被指定作为围绕密封剂的周界的衬底边缘。所述方法进一步包括以下步骤：除去临时载体，在半导体管芯、划片街区、以及衬底边缘上形成第一绝缘层，将第一导电层形成在第一绝缘层上并且电连接到接触焊盘，在第一导电层和第一绝缘层上形成第二绝缘层，以及通过第一绝缘层和划片街区单体化密封剂以分离半导体管芯。
在另一实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供载体，将半导体管芯安装到载体，以及在半导体管芯和载体上沉积密封剂。密封剂的一部分被指定作为半导体管芯之间的划片街区。所述方法进一步包括以下步骤：除去载体，在半导体管芯和划片街区上形成第一绝缘层，在第一绝缘层上形成第一导电层，在第一导电层和第一绝缘层上形成第二绝缘层，以及通过第一绝缘层和划片街区将密封剂单体化成半导体管芯。
在另一实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供多个半导体管芯，以及在所述半导体管芯上沉积密封剂。密封剂的一部分被指定作为半导体管芯之间的划片街区。所述方法进一步包括以下步骤：在半导体管芯和划片街区上形成第一绝缘层，在第一绝缘层上形成RDL，以及通过第一绝缘层和划片街区将密封剂单体化成半导体管芯。
在另一实施例中，本发明是一种半导体器件，该半导体器件包括：多个半导体管芯和沉积在所述半导体管芯上的密封剂。密封剂的一部分被指定作为半导体管芯之间的划片街区。第一绝缘层形成在半导体管芯和划片街区上。第一导电层形成在第一绝缘层上。第二绝缘层形成在第一导电层和第一绝缘层上。密封剂通过第一绝缘层和划片街区被单体化成半导体管芯。
附图说明
图1a-1b示出在划片街区或晶片边缘上没有钝化的常规半导体晶片；
图2示出具有安装到其表面的不同类型封装的PCB；
图3a-3c示出安装到所述PCB的典型半导体封装的更多细节；
图4a-4h示出在划片街区上和衬底边缘周围形成绝缘层的过程；
图5示出具有形成在划片街区上和衬底边缘周围的绝缘层的FO-WLCSP；
图6a-6d示出在划片街区上和衬底边缘周围的呈网状图案的绝缘层；以及
图7a-7c示出完全在划片街区上和衬底边缘周围的绝缘层。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀、以及无电极电镀（electroless plating）工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电极电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和刻蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品刻蚀作用除去了任何不规则的表面形貌（topography），产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化管芯，沿被叫做划片街区（saw street）或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块（stud bump）、导电胶、或线结合（wirebond）来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图2示出具有芯片载体衬底或印刷电路板（PCB）52的电子器件50，所述芯片载体衬底或印刷电路板（PCB）52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图2中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。
在图2中，PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线（trace）54形成在PCB 52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括线结合封装56和倒装芯片58，被示出在PCB 52上。另外，几种第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（land grid array，LGA）66、多芯片模块（MCM）68、四侧无引脚扁平封装（quad flat non-leaded package，QFN）70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图3a-3c示出示范性半导体封装。图3a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是导电材料（例如铝（AL）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、或银（Ag））的一个或多个层，并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，利用金硅共晶层或粘附材料（例如热的环氧或环氧树脂）将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和线结合82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染管芯74或线结合82来进行环境保护。
图3b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填充材料或环氧树脂粘附材料92被安装到载体90上。线结合94在接触焊盘96和98之间提供第一级封装互连。模塑料或密封剂100被沉积在半导体管芯88和线结合94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电极电镀这样合适的金属沉积形成在PCB 52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。
在图3c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。
BGA 60 利用凸块112电连接和机械连接到具有BGA型第二级封装的PCB 52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。
相对于图2和图3a-3c，图4a-4h示出在划片街区上和衬底边缘周围形成绝缘层的过程。在图4a中，衬底或载体120包含临时或牺牲基底材料，例如硅、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃纤维环氧树脂、氧化铍、或其它合适的低成本、刚性材料，用于结构支撑。可以在载体120上施加界面层或胶带（tape）122作为可利用紫外（UV）光或热释放的临时粘性或结合层。
半导体管芯124被安装到粘性带122上且接触焊盘126和有源表面128面向载体120。有源表面128包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面128内的其它电路元件以实现模拟电路或数字电路，例如数字信号处理器（DSP）、ASIC、存储器、或其它信号处理电路。半导体管芯124也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。
利用PVD、CVD、印刷、旋涂、喷涂或热氧化将绝缘或钝化层130形成在有源表面128和接触焊盘126上。绝缘层130可以是一层或多层的二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、聚酰亚胺、苯并环丁烯（benzocyclobutene，BCB）、聚苯并恶唑（polybenzoxazole，PBO）、或其它适当的介电材料。通过刻蚀工艺除去绝缘层130的一部分以暴露接触焊盘126。
图4b示出安装到粘性带122的半导体管芯124。利用浆料印刷（paste printing）、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器（applicator）在载体120和半导体管芯124上沉积密封剂或模塑料132。密封剂132可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂132不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在图4c中，通过化学刻蚀、机械剥离、CMP、机械研磨、热烘、激光扫描、湿法脱模、UV光或加热来除去载体120和粘性带122。半导体管芯124保持嵌有（embedded with）密封剂132，其用作具有嵌入或内陷的管芯的衬底133。划片街区134限定用于后来的单体化操作的区域。衬底边缘135限定衬底的周界。
在图4d中，通过PVD、CVD、印刷、旋涂、喷涂或热氧化将绝缘或钝化层136形成在衬底133上。绝缘层136可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似的绝缘和结构特性的其它材料。特别地，绝缘层136a覆盖被指定用于互连扇出的接触焊盘126、绝缘层130和模塑区138。通过刻蚀工艺除去绝缘层136a的一部分以暴露接触焊盘126。刻蚀工艺还在划片街区134的相对侧的绝缘层中产生间隙或通道140，其限定被指定用于单体化的划片区域上的绝缘层136b。通道140进一步限定沿衬底边缘135的绝缘层136c。
图4e是在衬底133上的绝缘层136的顶视图。在一个实施例中，通道140是10-30微米宽。绝缘层136b和136c部分地覆盖划片街区134和衬底边缘135。通道140延伸到封装钝化边缘以最小化从模塑表面138的前侧除气。绝缘层136还为后续层平面化表面并且保证接触焊盘126上的最后钝化的厚度用于凸块形成（bumping），其又控制测试板上的单体化管芯的可靠性，尤其是对于角凸块。
在图4f中，使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在绝缘层136a和接触焊盘126上形成导电层142。导电层142可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层142电连接到接触焊盘126并且用作RDL以扩展接触焊盘的电连接性。另外的RDL层可以建立在衬底上。
通过PVD、CVD、印刷、旋涂、喷涂或热氧化将绝缘或钝化层144形成在绝缘层136a和RDL 142上。绝缘层144可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似的绝缘和结构特性的其它材料。通过刻蚀工艺除去绝缘层144的一部分以暴露RDL 142。
在图4g中，使用蒸发、电解电镀、无电极电镀、球滴（ball drop）或丝网印刷工艺在RDL 142上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，和其组合，以及可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到RDL 142。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成至少部分地在模塑区138上延伸的球形球或凸块146。在一些应用中，凸块146二次回流以改善到RDL 142的电接触。所述凸块也可以被压缩结合到RDL 142。凸块146表示一种可以形成在RDL 142上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
在图4h中，利用锯条或激光切割工具148通过绝缘层136和划片街区134来单体化衬底133以将单个半导体管芯124分离成FO-WLCSP 150。锯条或激光切割工具148可以使用单切割（single cut）或阶梯切割（step cut）。
图5示出在单体化之后的FO-WLCSP 150。接触焊盘132、RDL 142和凸块146提供到有源表面130上的电路的电连接。绝缘层136形成在RDL 142之前并覆盖划片街区134和衬底边缘135（除了通道140）以减少从模塑区138的除气。绝缘层136改善了氧化物刻蚀期间的等离子体稳定性和对于扇出边缘焊盘的PVD中的接触电阻。绝缘层136还减少了单体化期间来自模塑区138的颗粒和其它污染物。
相对于图2和图3a-3c，图6a-6d示出在划片街区上和衬底边缘周围以网状图案形成绝缘层的过程。图6a示出类似于图4c的具有嵌入的半导体管芯164的衬底160。半导体管芯164具有有源表面170，该有源表面170包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面170内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯164也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。
利用PVD、CVD、印刷、旋涂、喷涂或热氧化将绝缘或介电层174形成在有源表面170和接触焊盘172上。绝缘层174可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、或其它适当的介电材料。通过刻蚀工艺除去绝缘层174的一部分以暴露接触焊盘172。
通过PVD、CVD、印刷、旋涂、喷涂或热氧化以网状图案将绝缘或钝化层176形成在半导体晶片160上。绝缘层176可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似的绝缘和结构特性的其它材料。特别地，绝缘层176a覆盖被指定用于互连扇出的接触焊盘172、绝缘层174和模塑区178。通过刻蚀工艺除去绝缘层176a的一部分以暴露接触焊盘172。刻蚀工艺还在划片街区166的两侧的绝缘层中都产生网状图案180，其限定在被指定用于单体化的划片街区166上的绝缘层176b。网状图案180进一步限定沿衬底边缘168的绝缘层176c。图6b是在半导体晶片160上的具有网状图案180的绝缘层176的顶视图。在网状图案180中，绝缘层176的一些部分在绝缘层176a之间延伸，并且绝缘层176的其它部分被网状图案破坏。图6c示出网状图案180以及存在和不存在绝缘层176的交替图案的进一步的细节。具有网状图案180的绝缘层176b和176c减少了从模塑区178的除气。
返回图6a，使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在绝缘层176a和接触焊盘172上形成导电层182。导电层182可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层182电连接到接触焊盘172并且用作RDL以扩展接触焊盘的电连接性。
通过PVD、CVD、印刷、旋涂、喷涂或热氧化将绝缘或钝化层184形成在绝缘层176a和RDL 182上。绝缘层184可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似的绝缘和结构特性的其它材料。通过刻蚀工艺除去绝缘层184的一部分以暴露RDL 182。
使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在RDL 182上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，和其组合，以及可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到RDL 182。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成至少部分地在模塑区178上延伸的球形球或凸块186。在一些应用中，凸块186二次回流以改善到RDL 182的电接触。所述凸块也可以被压缩结合到RDL 182。凸块186表示一种可以形成在RDL 182上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
在图6d中，类似于图5，利用锯条或激光切割工具188通过绝缘层176和划片街区166来单体化半导体晶片160以将单个半导体管芯164分离成FO-WLCSP 190。锯条或激光切割工具188可以使用单切割或阶梯切割。接触焊盘172、RDL 182和凸块186提供到有源表面170上的电路的电连接。绝缘层176形成在RDL 182之前并覆盖划片街区166和衬底边缘168（除了网状图案180）以减少从模塑区178的除气。绝缘层176改善了氧化物刻蚀期间的等离子体稳定性和对于扇出边缘焊盘的PVD中的接触电阻。绝缘层176还减少了单体化期间来自模塑区178的颗粒和其它污染物。
相对于图2和图3a-3c，图7a-7c示出以完全覆盖的方式在划片街区上和衬底边缘周围形成绝缘层的过程。图7a示出类似于图4c的具有嵌入的半导体管芯204的衬底200。半导体管芯204具有有源表面210，该有源表面210包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面210内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯164也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。
使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在有源表面210上形成导电层212。导电层212可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层212用作电连接到有源表面210上的电路的接触焊盘。
利用PVD、CVD、印刷、旋涂、喷涂或热氧化将绝缘或介电层214形成在有源表面210和接触焊盘212上。绝缘层212可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、或其它适当的介电材料。通过刻蚀工艺除去绝缘层214的一部分以暴露接触焊盘212。
通过PVD、CVD、印刷、旋涂、喷涂或热氧化以完全覆盖的方式将绝缘或钝化层216形成在半导体晶片200上。绝缘层216可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似的绝缘和结构特性的其它材料。特别地，绝缘层216覆盖被指定用于互连扇出的接触焊盘212、绝缘层214、模塑区218、衬底边缘208和划片街区206。通过刻蚀工艺除去绝缘层216的一部分以暴露接触焊盘212。图7b是完全覆盖半导体晶片200（包括模塑区218、划片街区206和衬底边缘208）的绝缘层216的顶视图。
使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在绝缘层216和接触焊盘212上形成导电层222。导电层222可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层222电连接到接触焊盘212并且用作RDL以扩展接触焊盘的电连接性。
通过PVD、CVD、印刷、旋涂、喷涂或热氧化将绝缘或钝化层224形成在绝缘层216和RDL 222上。绝缘层224可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似的绝缘和结构特性的其它材料。通过刻蚀工艺除去绝缘层224的一部分以暴露RDL 222。
使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在RDL 222上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，和其组合，以及可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到RDL 222。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成至少部分地在模塑区218上延伸的球形球或凸块226。在一些应用中，凸块226二次回流以改善到RDL 222的电接触。所述凸块也可以被压缩结合到RDL 222。凸块226表示一种可以形成在RDL 222上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
在图7c中，类似于图5，利用锯条或激光切割工具228通过绝缘层216和划片街区206来单体化半导体晶片200以将单个半导体管芯204分离成FO-WLCSP 230。锯条或激光切割工具228可以使用单切割或阶梯切割。接触焊盘212、RDL 222和凸块226提供到有源表面210上的电路的电连接。绝缘层216形成在RDL 222之前并完全覆盖划片街区206和衬底边缘208。绝缘层216改善了氧化物刻蚀期间的等离子体稳定性和对于扇出边缘焊盘的PVD中的接触电阻。绝缘层216还减少了单体化期间来自模塑区218的颗粒和其它污染物。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (24)

1.一种制造半导体器件的方法，包括：
提供临时载体;
安装具有面向临时载体的接触焊盘的多个半导体管芯;
在半导体管芯和临时载体上沉积密封剂，其中密封剂的一部分被指定作为半导体管芯之间的划片街区，并且密封剂的一部分被指定作为围绕密封剂的周界的衬底边缘；
除去临时载体；
在半导体管芯、划片街区、以及衬底边缘上形成第一绝缘层；
将第一导电层形成在第一绝缘层上并且电连接到接触焊盘；
在第一导电层和第一绝缘层上形成第二绝缘层；以及
通过第一绝缘层和划片街区单体化密封剂以分离半导体管芯。
2.根据权利要求1的方法，还包括形成第一绝缘层以覆盖半导体管芯周围的模塑区。
3.根据权利要求2的方法，还包括形成第一绝缘层以覆盖整个划片街区和模塑区。
4.根据权利要求1的方法，还包括在划片街区的相对侧的第一绝缘层中形成通道。
5.根据权利要求1的方法，还包括沿衬底边缘在第一绝缘层中形成通道。
6.根据权利要求1的方法，还包括以网状图案形成第一绝缘层以覆盖划片街区和衬底边缘。
7.根据权利要求1的方法，还包括在第一导电层上形成凸块。
8.一种制造半导体器件的方法，包括：
提供载体；
将半导体管芯安装到载体；以及
在半导体管芯和载体上沉积密封剂，其中密封剂的一部分被指定作为半导体管芯之间的划片街区；
除去载体；
在半导体管芯和划片街区上形成第一绝缘层；
在第一绝缘层上形成第一导电层；
在第一导电层和第一绝缘层上形成第二绝缘层；以及
通过第一绝缘层和划片街区将密封剂单体化成半导体管芯。
9.根据权利要求8的方法，其中密封剂的一部分被指定作为围绕密封剂的周界的衬底边缘。
10.根据权利要求9的方法，还包括沿衬底边缘在第一绝缘层中形成通道。
11.根据权利要求9的方法，还包括以网状图案形成第一绝缘层以覆盖划片街区和衬底边缘。
12.根据权利要求8的方法，还包括形成第一绝缘层以覆盖半导体管芯周围的模塑区。
13.根据权利要求12的方法，还包括形成第一绝缘层以覆盖整个划片街区和模塑区。
14.根据权利要求8的方法，还包括在划片街区的相对侧的第一绝缘层中形成通道。
15.一种制造半导体器件的方法，包括：
提供多个半导体管芯；
在所述半导体管芯上沉积密封剂，其中密封剂的一部分被指定作为半导体管芯之间的划片街区；
在半导体管芯和划片街区上形成第一绝缘层；
在第一绝缘层上形成再分布层（RDL）；以及
通过第一绝缘层和划片街区将密封剂单体化成半导体管芯。
16.根据权利要求15的方法，其中密封剂的一部分被指定作为围绕密封剂的周界的衬底边缘。
17.根据权利要求16的方法，还包括沿衬底边缘在第一绝缘层中形成通道。
18.根据权利要求16的方法，还包括以网状图案形成第一绝缘层以覆盖划片街区和衬底边缘。
19.根据权利要求15的方法，还包括形成第一绝缘层以覆盖半导体管芯周围的模塑区和整个划片街区。
20.根据权利要求15的方法，还包括在划片街区的相对侧的第一绝缘层中形成通道。
21.一种半导体器件，包括：
多个半导体管芯；
沉积在所述半导体管芯上的密封剂，其中密封剂的一部分被指定作为半导体管芯之间的划片街区；
形成在半导体管芯和划片街区上的第一绝缘层；
形成在第一绝缘层上的第一导电层；
形成在第一导电层和第一绝缘层上的第二绝缘层，其中密封剂通过第一绝缘层和划片街区被单体化成半导体管芯。
22.根据权利要求21的半导体器件，其中第一绝缘层覆盖半导体管芯周围的模塑区和整个划片街区。
23.根据权利要求21的半导体器件，还包括在划片街区的相对侧的第一绝缘层中形成的通道。
24.根据权利要求21的半导体器件，其中第一绝缘层以网状图案形成以覆盖划片街区。
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