CN102194684A - Grid dielectric layer manufacturing method - Google Patents
Grid dielectric layer manufacturing method Download PDFInfo
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- CN102194684A CN102194684A CN2010101236297A CN201010123629A CN102194684A CN 102194684 A CN102194684 A CN 102194684A CN 2010101236297 A CN2010101236297 A CN 2010101236297A CN 201010123629 A CN201010123629 A CN 201010123629A CN 102194684 A CN102194684 A CN 102194684A
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- dielectric layer
- gate dielectric
- semiconductor substrate
- ion implantation
- layer manufacturing
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Abstract
The invention discloses a grid dielectric layer manufacturing method, comprising the following steps: providing a semiconductor substrate; forming a shallow trench isolation structure in the semiconductor substrate; executing an ion implantation process; forming a well region in the semiconductor substrate; and forming a grid dielectric layer on the semiconductor substrate. In the method, after the shallow trench isolation structure is formed, no sacrificial oxide layer is formed, thus a long-time heat treatment process is not needed; and in the method, the step of removing the sacrificial oxide layer is omitted, thus avoiding a side ditch from appearing on the marginal area of the shallow trench isolation structure, and improving the performance of a semiconductor device.
Description
Technical field
The present invention relates to integrated circuit and make the field, particularly relate to a kind of gate dielectric layer manufacturing method.
Background technology
Make the field at integrated circuit, metal oxide semiconductor field effect tube (MOSFET) generally uses in the manufacture process of very lagre scale integrated circuit (VLSIC) (ULSI).Along with the continuous progress of semiconductor fabrication, the size of the grid of metal oxide semiconductor field effect tube is also more and more littler, and is also more and more higher for the requirement of the manufacturing process of gate dielectric layer.
Specifically please refer to Figure 1A～1E, it is the generalized section of each step corresponding construction of existing gate dielectric layer manufacturing method.
With reference to Figure 1A, Semiconductor substrate 10 at first is provided, then in described Semiconductor substrate 10, form fleet plough groove isolation structure 11, with each semiconductor device isolated insulation.Than traditional carrying out local oxide isolation technology (LOCOS), shallow ditch groove separation process is applicable to the active region isolation of the semiconductor device that 0.18 μ m is following more, and it can solve " beak " problem that is caused by carrying out local oxide isolation technology effectively.
With reference to Figure 1B, adopt the mode of boiler tube thermal oxidation (thermal oxidation), form sacrificial oxide layer (sacrifice oxide layer) 30 on described Semiconductor substrate 10, described sacrificial oxide layer 30 is used to avoid and may injects the channelling effect that causes by follow-up ion.General, the temperature of this boiler tube thermal oxidation technology is higher than 800 ℃, and the time of this boiler tube thermal oxidation is generally between 0.5～1.5 hour.
With reference to figure 1C, the mode by ion injects forms well region 12 in the Semiconductor substrate 10 around the described fleet plough groove isolation structure 11, and described well region 12 can be used for forming the conducting channel of metal oxide semiconductor field effect tube.For NMOS, described well region 12 can be the P trap; And for PMOS, described well region 12 can be the N trap.
With reference to figure 1D, in described Semiconductor substrate 10, form after the well region 12, in order to obtain high-quality gate dielectric layer, need to remove described sacrificial oxide layer 30.At present, industry normally adopts the mode of wet etching to remove described sacrificial oxide layer 30, for example, adopts hydrofluoric acid solution to remove sacrificial oxide layer 30, and this wet etching process need continues the long time, just can guarantee thoroughly to remove the sacrificial oxide layer 30 on Semiconductor substrate 10 surfaces.Yet, find that in actual production owing to passed through the hydrofluoric acid treatment process of long period, the pattern of described fleet plough groove isolation structure 11 fringe regions has been subjected to influence, has formed the gutter (divot) shown in dotted line among Fig. 1 E.
With reference to figure 1E, at last, utilize the mode of chemical vapour deposition (CVD), on described Semiconductor substrate 10, form gate dielectric layer 20, the material of described gate dielectric layer 20 is preferably silicon dioxide.
Yet, because the existence of described gutter very easily causes the in uneven thickness of described gate dielectric layer 20, and in the etched process of the follow-up polysilicon that carries out, be difficult to the polysilicon etching in the gutter is clean, make the edge current leakage of described fleet plough groove isolation structure 11; In addition, when forming described sacrificial oxide layer 30, need carry out the boiler tube thermal oxidation technology, this long heat treatment process very easily causes producing stress in described Semiconductor substrate, thereby causes producing the silicon chip static leakage current, and then influences the performance of semiconductor device.
Summary of the invention
The invention provides a kind of gate dielectric layer manufacturing method, to solve in the existing gate dielectric layer manufacturing method, be prone to the problem of gutter at the fleet plough groove isolation structure edge, and the present invention need not to carry out long heat treatment process, improved the performance of semiconductor device.
For solving the problems of the technologies described above, the invention provides a kind of gate dielectric layer manufacturing method, comprising: Semiconductor substrate is provided; In described Semiconductor substrate, form fleet plough groove isolation structure; Carry out ion implantation technology, in Semiconductor substrate, form well region; On described Semiconductor substrate, form gate dielectric layer.
Optionally, in described gate dielectric layer manufacturing method, described Semiconductor substrate is an epitaxial silicon chip.
Optionally, in described gate dielectric layer manufacturing method, described Semiconductor substrate is the silicon chip that hydrogenation process was handled.
Optionally, in described gate dielectric layer manufacturing method, the impurity that described ion implantation technology is injected is the boron ion, and the injection energy of described ion implantation technology is 200～400KeV, and the implantation dosage of described ion implantation technology is 1 * 10
13～2 * 10
13/ cm
2
Optionally, in described gate dielectric layer manufacturing method, the impurity that described ion implantation technology is injected is phosphonium ion, and the injection energy of described ion implantation technology is 400～600KeV, and the implantation dosage of described ion implantation technology is 0.5 * 10
13～2 * 10
13/ cm
2
Optionally, in described gate dielectric layer manufacturing method, the material of described gate dielectric layer is a silicon dioxide, and the thickness of described gate dielectric layer is
Owing to adopted technique scheme, compared with prior art, the present invention has the following advantages:
The present invention does not form sacrificial oxide layer after forming fleet plough groove isolation structure, therefore need not to carry out long heat treatment process, can avoid producing stress in Semiconductor substrate, has reduced the silicon chip static leakage current; And, because the present invention does not form sacrificial oxide layer, therefore after forming well region, omitted the step of removing sacrificial oxide layer, its fringe region that can guarantee fleet plough groove isolation structure can not corroded, thereby avoid gutter occurring at the fringe region of fleet plough groove isolation structure, can guarantee to form the uniform gate dielectric layer of thickness, prevent the edge current leakage of described fleet plough groove isolation structure, improve the performance of semiconductor device.
Description of drawings
Figure 1A～1E is the generalized section of each step corresponding construction of existing gate dielectric layer manufacturing method;
Fig. 2 is the flow chart of the gate dielectric layer manufacturing method that the embodiment of the invention provided;
Fig. 3 A～3C is the generalized section of each step corresponding construction of the gate dielectric layer manufacturing method that the embodiment of the invention provided.
Embodiment
Core concept of the present invention is, a kind of gate dielectric layer manufacturing method is provided, and this method does not form sacrificial oxide layer after forming fleet plough groove isolation structure, therefore need not to carry out long heat treatment process, can avoid in Semiconductor substrate, producing stress, reduce the silicon chip static leakage current; And, because the present invention does not form sacrificial oxide layer, therefore after forming well region, omitted the step of removing sacrificial oxide layer, the fringe region that can guarantee fleet plough groove isolation structure can not corroded, thereby avoid gutter occurring at the fringe region of fleet plough groove isolation structure, can guarantee to form the uniform gate dielectric layer of thickness, improve the performance of semiconductor device.
Please refer to Fig. 2, it is the flow chart of the gate dielectric layer manufacturing method that the embodiment of the invention provided, and in conjunction with this figure, this method may further comprise the steps:
Step S210 provides Semiconductor substrate;
Step S220 forms fleet plough groove isolation structure in described Semiconductor substrate;
Step S230 carries out ion implantation technology, forms well region in Semiconductor substrate;
Step S240 forms gate dielectric layer on described Semiconductor substrate.
Below in conjunction with generalized section gate dielectric layer manufacturing method of the present invention is described in more detail, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Specifically please refer to Fig. 3 A～3C, it is the generalized section of each step corresponding construction of the gate dielectric layer manufacturing method that the embodiment of the invention provided.
With reference to figure 3A, at first, provide Semiconductor substrate 100, then in described Semiconductor substrate 100, form fleet plough groove isolation structure 110, with each semiconductor device isolated insulation.
Preferably, described Semiconductor substrate 100 is epitaxial silicon chip (EPI wafer), and the crystal primary particle of described epitaxial silicon chip (crystal original particles, COP) density is less, help reducing the leakage current of semiconductor device, improve the puncture voltage of semiconductor device.Certainly, described Semiconductor substrate 100 also can be the lower silicon chip of other defect concentration, and for example, it can be the silicon chip (S2wafer) that hydrogenation process was handled.
Further, described fleet plough groove isolation structure 110 can form by following steps: at first, on described Semiconductor substrate 100, form pad oxide (not shown) and etching barrier layer (not shown), and on described etching barrier layer, form patterned light blockage layer, and be mask with described patterned light blockage layer, described pad oxide of etching and etching barrier layer are to Semiconductor substrate 100; Then, be mask with the etching barrier layer after the etching, the described Semiconductor substrate of etching 100 is to certain depth, to form shallow trench; Next, form the insulating barrier (not shown) that covers described shallow trench and etching barrier layer; Then, the insulating barrier that is filled in the described shallow trench is carried out planarization; At last, remove described pad oxide and etching barrier layer, to form fleet plough groove isolation structure 110.
With reference to figure 3B, carry out ion implantation technology, to form well region 120 in the Semiconductor substrate 100 around the fleet plough groove isolation structure 110, described well region 120 can be used for forming the conducting channel of metal oxide semiconductor field effect tube.
Preferably, for NMOS, described well region 120 is P traps, and the impurity that described ion implantation technology is injected is the boron ion, and the injection energy of described ion implantation technology is 200～400KeV, and the implantation dosage of described ion implantation technology is 1 * 10
13～2 * 10
13/ cm
2And for PMOS, described well region 120 is N traps, and the impurity that described ion implantation technology is injected is phosphonium ion, and the injection energy of described ion implantation technology is 400～600KeV, and the implantation dosage of described ion implantation technology is 0.5 * 10
13～2 * 10
13/ cm
2
The inventor is through repeatedly experiment discovery, after forming fleet plough groove isolation structure 110, carry out before the ion implantation technology, although do not form sacrificial oxide layer, but ion implantation technology does not cause obvious impairment to Semiconductor substrate 100, and owing to do not form sacrificial oxide layer, therefore need not to carry out long heat treatment process, reduced the silicon chip static leakage current; In addition, because the present invention does not form sacrificial oxide layer, therefore after forming well region 120, omitted the step of removing sacrificial oxide layer, the fringe region that can guarantee fleet plough groove isolation structure 110 can not corroded, thereby avoid gutter occurring at the fringe region of fleet plough groove isolation structure 110, can guarantee to form the uniform gate dielectric layer of thickness, and prevent the edge current leakage of described fleet plough groove isolation structure 110, improve the performance of semiconductor device.
With reference to figure 3C, can utilize the mode of chemical vapour deposition (CVD), on described Semiconductor substrate 100, form gate dielectric layer 300.Wherein, the material of described gate dielectric layer 210 is preferably silicon dioxide, the thickness of described gate dielectric layer 210 can for
In sum, therefore the present invention need not to carry out long heat treatment process owing to do not form sacrificial oxide layer after forming fleet plough groove isolation structure, avoids producing stress in Semiconductor substrate, has reduced the silicon chip static leakage current; And, because the present invention does not form sacrificial oxide layer, therefore after forming well region, omitted the step of removing sacrificial oxide layer, the fringe region that can guarantee fleet plough groove isolation structure can not corroded, thereby avoid gutter occurring at the fringe region of fleet plough groove isolation structure, can guarantee to form the uniform gate dielectric layer of thickness, prevent the edge current leakage of described fleet plough groove isolation structure, improve the performance of semiconductor device.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (7)
1. gate dielectric layer manufacturing method comprises:
Semiconductor substrate is provided;
In described Semiconductor substrate, form fleet plough groove isolation structure;
Carry out ion implantation technology, in Semiconductor substrate, form well region;
On described Semiconductor substrate, form gate dielectric layer.
2. gate dielectric layer manufacturing method as claimed in claim 1 is characterized in that described Semiconductor substrate is an epitaxial silicon chip.
3. gate dielectric layer manufacturing method as claimed in claim 1 is characterized in that, described Semiconductor substrate is the silicon chip that hydrogenation process was handled.
4. gate dielectric layer manufacturing method as claimed in claim 1 is characterized in that, the impurity that described ion implantation technology is injected is the boron ion, and the injection energy of described ion implantation technology is 200～400KeV, and the implantation dosage of described ion implantation technology is 1 * 10
13～2 * 10
13/ cm
2
5. gate dielectric layer manufacturing method as claimed in claim 1 is characterized in that, the impurity that described ion implantation technology is injected is phosphonium ion, and the injection energy of described ion implantation technology is 400～600KeV, and the implantation dosage of described ion implantation technology is 0.5 * 10
13～2 * 10
13/ cm
2
6. gate dielectric layer manufacturing method as claimed in claim 1 is characterized in that the material of described gate dielectric layer is a silicon dioxide.
7. gate dielectric layer manufacturing method as claimed in claim 6 is characterized in that the thickness of described gate dielectric layer is
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|---|---|---|---|
| CN 201010123629 CN102194684B (en) | 2010-03-12 | 2010-03-12 | Grid dielectric layer manufacturing method |
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| CN 201010123629 CN102194684B (en) | 2010-03-12 | 2010-03-12 | Grid dielectric layer manufacturing method |
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| CN102194684B CN102194684B (en) | 2013-02-27 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103887229A (en) * | 2014-03-20 | 2014-06-25 | 上海华力微电子有限公司 | Method for improving morphology of thick gate oxide |
| CN111627810A (en) * | 2020-06-05 | 2020-09-04 | 合肥晶合集成电路有限公司 | Semiconductor structure and manufacturing method thereof |
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| TW200505020A (en) * | 2003-07-24 | 2005-02-01 | Samsung Electronics Co Ltd | Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same |
| CN1873929A (en) * | 2005-06-03 | 2006-12-06 | 联华电子股份有限公司 | Component of metal oxide semiconductor transistor in high voltage, and fabricating method |
| US20080258134A1 (en) * | 2007-04-23 | 2008-10-23 | Mears Technologies, Inc. | Method for making a semiconductor device including shallow trench isolation (sti) regions with maskless superlattice deposition following sti formation and related structures |
| US20090206441A1 (en) * | 2008-02-15 | 2009-08-20 | International Business Machines Corporation | Method of forming coplanar active and isolation regions and structures thereof |
-
2010
- 2010-03-12 CN CN 201010123629 patent/CN102194684B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200505020A (en) * | 2003-07-24 | 2005-02-01 | Samsung Electronics Co Ltd | Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same |
| CN1873929A (en) * | 2005-06-03 | 2006-12-06 | 联华电子股份有限公司 | Component of metal oxide semiconductor transistor in high voltage, and fabricating method |
| US20080258134A1 (en) * | 2007-04-23 | 2008-10-23 | Mears Technologies, Inc. | Method for making a semiconductor device including shallow trench isolation (sti) regions with maskless superlattice deposition following sti formation and related structures |
| US20090206441A1 (en) * | 2008-02-15 | 2009-08-20 | International Business Machines Corporation | Method of forming coplanar active and isolation regions and structures thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103887229A (en) * | 2014-03-20 | 2014-06-25 | 上海华力微电子有限公司 | Method for improving morphology of thick gate oxide |
| CN111627810A (en) * | 2020-06-05 | 2020-09-04 | 合肥晶合集成电路有限公司 | Semiconductor structure and manufacturing method thereof |
| CN111627810B (en) * | 2020-06-05 | 2022-10-11 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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| CN102194684B (en) | 2013-02-27 |
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