CN102184089A - Data stream operating method in dynamic reconfigurable processor - Google Patents
Data stream operating method in dynamic reconfigurable processor Download PDFInfo
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Abstract
The invention provides a data stream operating method in a dynamic reconfigurable processor. The method comprises the following steps of: classifying data according to different action ranges of the data and performing a judgment operation on the data; transmitting the classified data to a processing unit array for processing in different modes according to judgment results; and after finishing processing, transmitting operational results processed by the processing unit array to an appointed position by selecting a corresponding gateway according to configuration information. By the method, data conflict is avoided effectively, the clearness of a data stream structure is ensured, and high-efficiency cooperation can be performed among modules so as to bring convenience for controlling.
Description
Technical field
The present invention relates to the dynamic reconfigurable processor technical field in the embedded system field, particularly relate to the method for data stream running in a kind of dynamic reconfigurable processor.
Background technology
The dynamic reconfigurable processor is a kind of new life's a processor framework, and its single core processor, special chip, field programmable logic array (FPLA) as compared with the past has significant advantage, is a direction of following circuit structure development.
At first, often contain a plurality of ALUs in the dynamic reconfigurable processor, and enormous amount, be referred to as many nuclear arrays.Array inside is equipped with the high routing unit of flexibility ratio, realizes between the ALU diversified interconnected.Therefore, the crowd after the route unit connects examines array can realize high speed processing to data stream, and more traditional monokaryon and few core processor have huge advantage on performance.Simultaneously, the special circuit that solidifies also has huge advantage in dirigibility.
Secondly, more traditional static reconfigurable circuit---field programmable logic array (FPLA), the dynamic reconfigurable processor has dynamic characteristics, the i.e. function of commutation circuit dynamically in the circuit operational process, but not static in the past reconfigurable circuit unalterable do not change circuit function, just programming circuit function before the circuit operation is carried out initialization to circuit.The benefit of doing like this is to have reduced by time-multiplexed mode the scale of circuit, and the full mapping of the circuit structure before reason is becomes the piecemeal mapping now, and has taked the mode of dynamic switching between piece and the piece just.
The dynamic reconfigurable processor can produce lot of data and flow when calculating, therefore, need the urgent technical matters that solves of those skilled in the art to be exactly at present: how can propose a kind of effective measures with innovating, to solve problems of the prior art, effectively avoid data collision, guarantee correctly collaborative work efficiently between each module.
Summary of the invention
Technical matters to be solved by this invention provides the method for data stream running in a kind of dynamic reconfigurable processor, and the data collision when effectively avoiding the dynamic reconfigurable processor to calculate guarantees correctly collaborative work efficiently between each module.
In order to address the above problem, the invention discloses the method for data stream running in a kind of dynamic reconfigurable processor, described method comprises:
The dynamic reconfigurable processor is judged whether these data only are used once and will be used the requirement of satisfying simultaneously as the pe array operand in pe array computing next time after data; Data are divided into the outer data of sheet, interaction data and pe array internal data in the sheet in the described dynamic reconfigurable processor;
If then the inside and outside DTU (Data Transfer unit) is directly delivered to pe array with these data and is handled;
If not, then the inside and outside DTU (Data Transfer unit) is written out to internal data memory with these data, by the internal data reader unit data is read in the data-carrier store internally, delivers to pe array and handles;
After pe array is finished data processing and finished, the operation result of pe array internal data is sent to assigned address according to configuration information.
Preferably, the source of described pe array internal data comprises external data that interaction data in the sheet that data interaction device in the last operation result, sheet of pe array reads in the data interaction working storage between data interaction working storage or processor, inside and outside DTU (Data Transfer unit) read in from the external data buffer and the data the internal data memory between subelement.
Preferably, the specified position of described configuration information comprises between the input end that is delivered to self pe array, processor external memory storage, subelement data interaction working storage and internal data memory between data interaction working storage, processor.
Preferably, described pe array internal data external data that to be interaction data in the sheet that data interaction device is read in the data interaction working storage between data interaction working storage or processor between subelement in the last operation result, sheet of pe array, inside and outside DTU (Data Transfer unit) read in from the external data buffer and in the data the internal data memory one or more.
Preferably, for the outer data of sheet, after pe array is handled data, internal data is write out device and is read in data processed result from pe array, needs are sent to the outer data of sheet are written out to the internal data buffer, external data is write out device data is read in the data buffer internally then, is written out to the processor external memory storage.
Preferably, described external data will be passed through external data buffer and internal data buffer respectively in the process that is read into and writes out pe array.
Preferably, when reading in the outer data of sheet, the external data reader unit only need be paid close attention to the external data buffer and whether be in the state of can writing.
Preferably, when writing the outer data of slice, external data is write out device and only need be paid close attention to the internal data buffer and whether be in readable state.
Compared with prior art, the present invention has the following advantages:
The present invention classifies to data according to the different reach of data and data is carried out decision, in different ways it being delivered to pe array according to result of determination handles, after pending the finishing according to configuration information, select for use respective via that pe array is sent to assigned address with the operation result of handling, effectively avoided data collision, guarantee the clear of data flow architecture, can work in coordination with efficiently between each module, be convenient to control.
Description of drawings
Fig. 1 is the data flow diagram of a kind of typical dynamic reconfigurable processor described in the specific embodiment of the invention;
Fig. 2 is the data interaction synoptic diagram between a kind of dynamic reconfigurable processor described in the specific embodiment of the invention;
Fig. 3 is the method flow diagram of data stream running in a kind of dynamic reconfigurable processor described in the embodiment of the invention;
Fig. 4 is the dynamic reconfigurable processor data stream running synoptic diagram described in the embodiment of the invention;
Fig. 5 is the operational flowchart of a pe array described in the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
A kind of data flow diagram of typical dynamic reconfigurable processor as shown in Figure 1.In conjunction with Fig. 1, the data of dynamic reconfigurable processor running flow process can be summarized as follows: the data in the processor external memory storage are dispensed in the inner a plurality of subelements of processor, and a plurality of subelements carry out data processing simultaneously, to reach the effect of parallel processing.After each subelement was handled, result was written out to the processor external memory storage; Have data interaction between each subelement of same reconfigurable processor inside, promptly subelement B can use the result of calculation of subelement A.For the data interaction between subelement, control by isochronous controller between subelement; Also have data interaction between the reconfigurable processor, promptly the subelement of processor B can use the result of calculation of the subelement of processor A.
Data interaction synoptic diagram between processor as shown in Figure 2.The dynamic reconfigurable processor structurally can be divided into following four parts:
1. data storage device
A) store pending data.
B) intermediate result of storage computing.
C) net result of storage computing.
D) be used for the buffer memory of data interaction.
2. data shifting apparatus
Be used for the data carrying between the data storage device.
3. arithmetic element
A) arithmetic element is a pe array, specifically referring to Fig. 1.
B) processing unit is an arithmetic logical unit, can realize the basic arithmetical operation function and the arithmetic logical operation function of logical operation function and some customizations.
C) connect by routing unit between the processing unit, to realize the flexible and fast data transmission between the processing unit.
D) the entire process cell array is controlled by timing control unit, with the sequential relationship between the input of Coordination Treatment cell array, computing, the output.
E) pe array can realize data in enormous quantities are carried out the fast processing of cycling.
4. sync control device
A) sync control device is an isochronous controller between subelement.
B) under its control, a plurality of subelements (1 to N, N is the subelement number) are all finished a plurality of subelements behind the appointment subtask separately (what herein a plurality of can be with before is a plurality of inconsistent) just can carry out its next subtask in sequence of subtask separately.
C) isochronous controller has been realized certain task after being divided into a plurality of subtasks between subelement, is distributed to a plurality of subelement executed in parallel, behind the intact a plurality of subtasks of a plurality of subelement executed in parallel synchronously, the parallelization that just can begin next task after is synchronously carried out.
Embodiment:
With reference to Fig. 3, show the method flow diagram of data stream running in a kind of dynamic reconfigurable processor of the present invention, described method specifically comprises:
Step S301, dynamic reconfigurable processor judge whether these data only are used once and will be used the requirement of satisfying simultaneously as the pe array operand in pe array computings next time after data; Data are divided into the outer data of sheet, interaction data and pe array internal data in the sheet in the described dynamic reconfigurable processor;
In the present embodiment,, data are divided into the outer data of sheet, interaction data and pe array internal data in the sheet according to the reach of data in dynamic reconfigurable processor inside.Concrete, the outer data of sheet are meant data of reading in from the processor external memory storage and the data that are written out to the processor external memory storage, and its data path can be introduced in the content of back in detail.Interaction data is the data of sharing between the data shared between inner each subelement of finger processor and the different processor in the sheet, and its data path can be introduced in the content of back in detail.The pe array internal data is meant pe array relates to read in data and write out data in the process of carrying out computing, its data path can be introduced in the content of back in detail.
If, execution in step S302 then;
If not, execution in step S303 then;
Step S302, the inside and outside DTU (Data Transfer unit) is directly delivered to pe array with these data and is handled;
Step S303, the inside and outside DTU (Data Transfer unit) is written out to internal data memory with these data, by the internal data reader unit data is read in the data-carrier store internally, delivers to pe array and handles;
After step S304, pe array finish data processing and finish, the operation result of pe array internal data is sent to assigned address according to configuration information.
According to the data category of being divided, pe array with the operation result handled according to configuration information, select for use respective via to send to assigned address, each bar path has data storage device and data shifting apparatus, and is concrete, can be with reference to the stream of the dynamic reconfigurable processor data shown in Fig. 4 running synoptic diagram, wherein data storage device is divided into 5, specify as follows: the external data buffer, be used for the external data buffer memory that will read in, be read out when to be needed.Internal data memory is used for the data that temporary pe array computing will be used, and data are read out when need waiting, output to pe array.The internal data buffer is used for the result data of pe array is carried out buffer memory, waits to export to outside the processor.Data interaction working storage between subelement is used for the result data of temporary subelement A, treats that subelement B reads, to realize the data interaction between subelement.Data interaction working storage between processor is used for the result data of temporary processor A subelement a, and pending device B subelement b reads, to realize the data interaction between processor.Further specify, the data interaction working storage is shared by interior whole subelements of processor between described subelement; The data interaction working storage is shared by whole subelements that whole processors comprise between processor.
Data shifting apparatus is used for data are read from data storage device, and writes another data storage device, and data are shifted between data storage device, and final the realization writes pe array with data.Perhaps data are read from data storage device, pe array writes direct.After pe array has moved, the result data of pe array is read.Be divided into 6 according to transfer device: data interaction device in the external data reader unit, sheet, the inside and outside DTU (Data Transfer unit), the internal data reader unit, internal data writes out device and external data is write out device.
Flow direction by data stream carries out specific description, and the external data reader unit is used for the outer pending data of dynamic reconfigurable processor are read in the dynamic reconfigurable processor, is cached in the external data buffer.Data interaction device in the sheet, be used for between subelement between exchanges data working storage or processor the result data of other subelements of data interaction working storage stored read, be distributed to the internal data memory of current subelement or directly be distributed to pe array, whether this result data that depends on this subelement can direct processed cell array be handled.The inside and outside DTU (Data Transfer unit) is used for the external data of buffer memory in the external data buffer is distributed to internal data memory or directly is distributed to pe array, and this depends on whether these outside data can direct processed cell array be handled.The internal data reader unit, the internal data that is used for the current subelement that will store in the internal data memory is read, and when needed polylith 2D data splicing is become 2D data, the most spliced data (Pin Jie words if desired) send to pe array.Internal data is write out device, be used for the result data of pe array is read, writing to pe array again uses when and then moving pe array, or write to internal data memory with metadata cache, or write between subelement the data interaction working storage and use for data interaction between subelement, or write between processor the data interaction working storage and use, or write the internal data buffer and wait to export to outside the processor for data interaction between processor.External data is write out device, and the result data that is used for being cached in the subelement of internal data buffer exports to outside the processor.
With the mode data of description of 2D, a 2D data block each row of data number is identical in the present embodiment, and is stored in the storer in the mode of row alignment.
Specific to Various types of data, the working order of its data stream is as follows:
The data stream running of the outer data of sheet is that object describes with Fig. 4.The external data reader unit reads in the outer data of sheet from the processor external memory storage, according to configuration information data are written out to the external data buffer of the pe array of appointment then.The inside and outside DTU (Data Transfer unit) is read in data from the external data buffer, in two kinds of situation data are handled:
When below the data of reading in from the external data buffer satisfy simultaneously during three conditions, the inside and outside DTU (Data Transfer unit) can directly be delivered to pe array to data and handle: 1 these data only are used once; 2 these data need processed cell array to use (promptly being used) immediately in next pe array computing; 3 these data need not with internal data memory in data carry out concatenation (promptly satisfying requirement) as the pe array operand.
If the data of reading in from the external data buffer can not expire three above-mentioned conditions simultaneously, the inside and outside DTU (Data Transfer unit) can be written out to internal data memory to data, by the internal data reader unit data are read in the data-carrier store internally again, deliver to pe array and handle.
After data processing finishes, internal data is write out device and is read in data processed result from pe array, needs are sent to the outer data of sheet are written out to the internal data buffer, external data is write out device data is read in the data buffer internally then, is written out to the processor external memory storage.
External data is in the process that is read into and writes out pe array, to pass through external data buffer and internal data buffer respectively, they act as the data stream running: isolated outer reading and writing data and the interior data processing of sheet of sheet, made control become simple.When reading in the outer data of sheet, the external data reader unit only need be paid close attention to the external data buffer and whether be in the state of can writing; When writing the outer data of slice, external data is write out device and only need be paid close attention to the internal data buffer and whether be in readable state.Data buffer has data pre-fetch function, can filtering data traffic spike, overcome the influence that instability caused of data traffic.
Same, the running of the data stream of interaction data is that object describes with Fig. 4 in the sheet.In the sheet data interaction device according to configuration information between subelement between data interaction working storage or processor the data interaction working storage read in needed data, in two kinds of situation data are handled:
When below the data interaction working storage reads between data interaction working storage or processor between subelement data satisfy simultaneously during three conditions, data interaction device can directly be delivered to pe array to data and handles in the sheet: 1 these data only are used once; 2 these data need processed cell array to use immediately; 3 these data need not with internal data memory in data carry out concatenation.
If can not satisfy three above-mentioned conditions simultaneously from the data that the data interaction working storage reads between data interaction working storage or processor between subelement, data interaction device can be written out to internal data memory to data in the sheet, by the internal data reader unit data are read in the data-carrier store internally again, deliver to pe array and handle.
After data processing finished, internal data was write out device and is read in data processed result from pe array, in two kinds of situation data was handled:
If data need be used by other subelements in the same reconfigurable processor, then internal data is write out device data is written out to data interaction working storage between subelement.
If data need be handled processor by other restructurals and use, then internal data is write out device data is written out to data interaction working storage between processor.
Same, the data stream running of pe array internal data is that object describes with Fig. 4.
The Data Source of pe array input end has four kinds of situations according to from top to bottom order of diagram: current computing need be used the last operation result of self pe array immediately, and this operation result only is used once, simultaneously this operation result need not with internal data memory in data carry out concatenation, then the output terminal of pe array directly is delivered to operation result the input end of self; Current computing need be used interaction data in the sheet that data interaction device in the sheet reads in the data interaction working storage between data interaction working storage or processor immediately between subelement, and these data only are used once, simultaneously these data need not with internal data memory in data carry out concatenation, then data interaction device is directly given data transfer the input end of pe array in the sheet; The external data that current computing need use the inside and outside DTU (Data Transfer unit) to read in from the external data buffer immediately, and these data only are used once, simultaneously these data need not with internal data memory in data carry out concatenation, then the inside and outside DTU (Data Transfer unit) is directly given data transfer the input end of pe array; Current computing need be used the data (external data that these data are stored before may being in the internal data memory, interaction data in Cun Chu the sheet before, the perhaps operation result before self pe array), the internal data reader unit reads in desired data internally in the data-carrier store, be delivered to the input end of pe array.The input of pe array can be the combination in any of above four kinds of situations.
Internal data is write out device the operation result of pe array is read in, according to configuration information operation result is sent to assigned address then, the flow direction of data has five kinds of situations according to from top to bottom order of diagram: when the result of current computing satisfied following three conditions simultaneously, internal data is write out the input end that device directly is delivered to operation result self pe array: 1 this operation result only was used once; 2 these operation results need processed cell array promptly to use in computing neutrality next time; 3 these operation results need not with internal data memory in data carry out concatenation; The result of current computing need output to the processor external memory storage, internal data is write out device and at first operation result is written out to the internal data buffer, external data is write out device and is read in operation result in the data buffer internally then, is written out to the processor external memory storage again; The result of current computing need be used by other subelements in the same reconfigurable processor, and then internal data is write out device operation result is written out to data interaction working storage between subelement; The result of current computing need be used by other reconfigurable processors, and then internal data is write out device operation result is written out to data interaction working storage between processor; If the result of current computing need be used by self pe array, but can not satisfy three above-mentioned conditions simultaneously, internal data is write out device operation result is written out to internal data memory.The output of pe array can be certain several combination in above five kinds of situations.As mentioned above, the input end of pe array has four kinds of Data Sources, and output terminal has five kinds of data flows, 20 kinds of data paths of one-tenth capable of being combined.
Be that example illustrates the data stream running of the dynamic reconfigurable processor inside of process flow diagram correspondence therewith with a simple process flow figure below.
The operational flowchart of a pe array as shown in Figure 5, each square frame is represented the once-through operation of pe array.
The result of the N time computing needs and the result of the N+2 time computing carries out concatenation, is stored to internal data memory so internal data is write out device.
The input of the N+1 time computing comprises interaction data in outer data of sheet and the sheet.
The outer data of sheet need participate in the N time computing immediately, and use no longer repeatedly, do not need to carry out concatenation simultaneously, so the inside and outside DTU (Data Transfer unit) is directly delivered to the pe array input end with it.
Interaction data is read in the data interaction working storage between data interaction working storage or processor between subelement by data interaction device in the sheet in the sheet, but these data can not participate in computing immediately, so data interaction device is stored to internal data memory in the sheet.When proceeding to the N+1 time computing, the internal data reader unit sends it to the pe array input end again.
The result of the N+1 time computing does not participate in the N+2 time computing, but needs to participate in the N+3 time computing, is stored to internal data memory so internal data is write out device.
The input of the N+2 time computing comprises interaction data in outer data of sheet and the sheet.
After being read into, the outer data of sheet can not participate in computing immediately, so the inside and outside DTU (Data Transfer unit) is stored to internal data memory.When proceeding to the N+2 time computing, the internal data reader unit sends it to the pe array input end again.
Interaction data is read in the data interaction working storage between data interaction working storage or processor between subelement by data interaction device in the sheet in the sheet, these data need participate in the N+2 time computing immediately, and use no longer repeatedly, simultaneously do not need to carry out concatenation, so directly delivered to the pe array input end.
The result of the N+2 time computing need carry out concatenation with the result of the N time computing, is stored to internal data memory so internal data is write out device.
The input of the N+3 time computing comprises the result of the N+1 time computing and the splicing of the N time and the N+2 time operation result.
The result of the N+1 time computing is stored in the internal data memory, and the internal data reader unit reads in it and deliver to the input end of pe array.
The result of the N time and the N+2 time computing also is stored in the internal data memory, through after the concatenation, will splice the input end that pe array was read in and delivered to the result by the internal data reader unit.
The final operation result of whole process flow diagram need output to the pe array outside, be divided into following three kinds of situations: output to the processor external memory storage, internal data is write out device operation result is written out to the internal data buffer, external data is write out device and is read in operation result in the data buffer internally again, and it is written out to the processor external memory storage; Output is used for other subelements in the same reconfigurable processor, and internal data is write out device operation result is written out to data interaction working storage between subelement; Output is used for other reconfigurable processors, and internal data is write out device operation result is written out to data interaction working storage between processor.
More than the method for data stream running in a kind of dynamic reconfigurable processor provided by the present invention is described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (8)
1. the method for data stream running in the dynamic reconfigurable processor is characterized in that described method comprises:
The dynamic reconfigurable processor is judged whether these data only are used once and will be used the requirement of satisfying simultaneously as the pe array operand in pe array computing next time after data; Data are divided into the outer data of sheet, interaction data and pe array internal data in the sheet in the described dynamic reconfigurable processor;
If then the inside and outside DTU (Data Transfer unit) is directly delivered to pe array with these data and is handled;
If not, then the inside and outside DTU (Data Transfer unit) is written out to internal data memory with these data, by the internal data reader unit data is read in the data-carrier store internally, delivers to pe array and handles;
After pe array is finished data processing and finished, the operation result of pe array internal data is sent to assigned address according to configuration information.
2. the method for claim 1 is characterized in that:
The source of described pe array internal data comprises external data that interaction data in the sheet that data interaction device in the last operation result, sheet of pe array reads in the data interaction working storage between data interaction working storage or processor, inside and outside DTU (Data Transfer unit) read in from the external data buffer and the data the internal data memory between subelement.
3. the method for claim 1 is characterized in that:
The specified position of described configuration information comprises between the input end that is delivered to self pe array, processor external memory storage, subelement data interaction working storage and internal data memory between data interaction working storage, processor.
4. the method for claim 1 is characterized in that:
Described pe array internal data external data that to be interaction data in the sheet that data interaction device is read in the data interaction working storage between data interaction working storage or processor between subelement in the last operation result, sheet of pe array, inside and outside DTU (Data Transfer unit) read in from the external data buffer and in the data the internal data memory one or more.
5. the method for claim 1 is characterized in that:
For the outer data of sheet, after pe array is handled data, internal data is write out device and is read in data processed result from pe array, needs are sent to the outer data of sheet are written out to the internal data buffer, external data is write out device data is read in the data buffer internally then, is written out to the processor external memory storage.
6. method as claimed in claim 5 is characterized in that:
Described external data will be passed through external data buffer and internal data buffer respectively in the process that is read into and writes out pe array.
7. method as claimed in claim 6 is characterized in that:
When reading in the outer data of sheet, the external data reader unit only need be paid close attention to the external data buffer and whether be in the state of can writing.
8. method as claimed in claim 6 is characterized in that:
When writing the outer data of slice, external data is write out device and only need be paid close attention to the internal data buffer and whether be in readable state.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4546428A (en) * | 1983-03-08 | 1985-10-08 | International Telephone & Telegraph Corporation | Associative array with transversal horizontal multiplexers |
| CN1107597A (en) * | 1994-02-24 | 1995-08-30 | 吴乾弥 | Pipeline type and palpitation type single-instruction multi-data-flow array processing structure and method |
| US20040215928A1 (en) * | 2003-04-23 | 2004-10-28 | Mark Beaumont | Method for manipulating data in a group of processing elements to transpose the data using a memory stack |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4546428A (en) * | 1983-03-08 | 1985-10-08 | International Telephone & Telegraph Corporation | Associative array with transversal horizontal multiplexers |
| CN1107597A (en) * | 1994-02-24 | 1995-08-30 | 吴乾弥 | Pipeline type and palpitation type single-instruction multi-data-flow array processing structure and method |
| US20040215928A1 (en) * | 2003-04-23 | 2004-10-28 | Mark Beaumont | Method for manipulating data in a group of processing elements to transpose the data using a memory stack |
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