CN102063288A - DSP (Digital Signal Processing) chip-oriented instruction scheduling method - Google Patents
DSP (Digital Signal Processing) chip-oriented instruction scheduling method Download PDFInfo
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- CN102063288A CN102063288A CN2011100024549A CN201110002454A CN102063288A CN 102063288 A CN102063288 A CN 102063288A CN 2011100024549 A CN2011100024549 A CN 2011100024549A CN 201110002454 A CN201110002454 A CN 201110002454A CN 102063288 A CN102063288 A CN 102063288A
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Abstract
The invention relates to a DSP (Digital Signal Processing) chip oriented instruction scheduling method, which comprises the following steps of: step A. constructing topological sorting among basic block statements of an assembler; step B. calculating the delay of each instruction on the basis of the topological sorting obtained in the step A; step C. traversing a data dependence graph from root nodes to leaf nodes; and step D. finding out an instruction with the maximum delay in a candidate instruction set in the step C and executing time less than or equal to the current time and arranging the instruction in the current scheduling time slot. By means of modeling, the method realizes the optimization of a DSP chip which is not limited to a specific DSP chip on the market.
Description
Technical field
The present invention relates to compiler technologies in the Computer Science and Technology, relate in particular to a kind of: Digital Signal Processing, be called for short DSP towards the DSP(digital signal processing) the instruction scheduling method of chip.
Background technology
Along with the continuous development of computer technology multimedia technology, the audio frequency and video technology becomes a main flow direction of current computer science and technology research field.But the audio, video data amount is big, and the computing power of chip is had high requirements, so will realize many high-end applications of audio frequency and video technology, must try every possible means to improve the processing power of chip.And the assembly code of dsp chip of the prior art is generally limited to a certain concrete function.
Summary of the invention
Be generally limited to a certain concrete function at the dsp chip that exists in the prior art, therefore be necessary to provide a kind of instruction scheduling method towards dsp chip.
The present invention has overcome the deficiencies in the prior art, and the method that improves program operation speed is provided.The invention provides a kind of instruction scheduling method towards dsp chip, it comprises following steps:
Steps A. the topological sorting between the structure assembly routine fundamental block statement;
Step B. calculates the length of delay delay of every instruction in the assembly language program(me) fundamental block on the basis of the topological sorting that steps A obtains;
Step C. travels through the data dependency graph from the root node to the leaf node, and selection instruction is dispatched in the process of traversal, produces the candidate instruction collection; Described candidate instruction collection is divided into two set: the instruction that has maximum delay value among set record step B; The execution time is less than or equal to the instruction set of current time the earliest for set record;
Step D. is maximum with delay value in the candidate instruction set among the step C, and its execution time be less than or equal to the instruction of current time and find out, be arranged in current scheduling time groove, and then, upgrade candidate instruction and gather according to the data dependency graph;
Step e. the assembly language code that output scheduling is later.
Preferably, in the described steps A topological sorting between the structure assembly routine fundamental block statement based on linear dispatching algorithm.
Preferably, calculate the length of delay delay of every instruction in the assembly language program(me) fundamental block among the described step B, its computing formula is as follows:
Exectime(n wherein) instruct needed periodicity, wherein exectime(n for carrying out the n bar) instruct needed periodicity for carrying out the n bar, late_delay (n, m)=latency (linst (n), linst (m)+delay (m))+1; Latency (linst (n), linst (m)) is used to calculate needs the clock periodicity that keeps between two instructions, just when having data between two adjacent statements and rely on, machine is for fear of data hazard and the time that must postpone.
Preferably, after step D is complete, judge the execution in step E if instruction scheduling finishes, otherwise repeated execution of steps C.
Beneficial effect of the present invention is: the efficient that improves the audio frequency and video disposal route by the assembly code that changes the generation of audio frequency and video disposal route, optimize the handling procedure of dsp chip, by the mode of modeling, realized the optimization of general dsp chip, be not limited to a certain on the market concrete dsp chip.In invention, made full use of and all existed in all dsp chips or the function of similar very long instruction word (VLIW) collection VLIW.
Description of drawings
Fig. 1 is the step synoptic diagram towards the instruction scheduling method of dsp chip.
Embodiment
The present invention is further elaborated below in conjunction with accompanying drawing.
At first calling GCC(and be used for the compiler of programming under the linux system) compiler generates the assembly code file of computer language code correspondence, then based on assembling file, carry out following a series of instruction scheduling method towards dsp chip, generate assembly code file of the same name, give linker at last and generate executable file.
Step synoptic diagram as shown in Figure 1 towards the instruction scheduling method of dsp chip, it comprises following steps:
Steps A. the topological sorting between the structure assembly routine fundamental block statement;
Step B. calculates the length of delay delay of every instruction in the assembly language program(me) fundamental block on the basis of the topological sorting that steps A obtains;
Step C. travels through the data dependency graph from the root node to the leaf node, and selection instruction is dispatched in the process of traversal, produces the candidate instruction collection; Described candidate instruction collection cands is divided into two set: gather the instruction that has maximum delay value among the mcands recording step B for one; A set ecands writes down the instruction set that execution time etime the earliest is less than or equal to current time curtime;
Step D. is maximum with delay value in the candidate instruction set among the step C, and its execution time be less than or equal to the instruction of current time and find out, be arranged in current scheduling time groove, and then, upgrade candidate instruction and gather according to the data dependency graph;
Step e. the assembly language code that output scheduling is later.
Preferably, in the described steps A topological sorting between the structure assembly routine fundamental block statement based on linear dispatching algorithm.
Preferably, calculate the length of delay delay of every instruction in the assembly language program(me) fundamental block among the described step B, its computing formula is as follows:
Exectime(n wherein) instruct needed periodicity for carrying out the n bar, and late_delay (n, m)=latency (linst (n), linst (m))+delay (m)+1; Latency (linst (n), linst (m)) is used to calculate needs the clock periodicity that keeps between two instructions, just when having data between two adjacent statements and rely on, machine is for fear of data hazard and the time that must postpone;
Preferably, after step D is complete, judge the execution in step E if instruction scheduling finishes, otherwise repeated execution of steps C.
The present invention is not limited to aforesaid embodiment.The present invention expands to any new feature or any new combination that discloses in this manual, and the arbitrary new method that discloses or step or any new combination of process.
Claims (4)
1. instruction scheduling method towards dsp chip, it comprises following steps:
Steps A. the topological sorting between the structure assembly routine fundamental block statement;
Step B. calculates the length of delay delay of every instruction in the assembly language program(me) fundamental block on the basis of the topological sorting that steps A obtains;
Step C. travels through the data dependency graph from the root node to the leaf node, and selection instruction is dispatched in the process of traversal, produces the candidate instruction collection; Described candidate instruction collection is divided into two set: the instruction that has maximum delay value among set record step B; The execution time is less than or equal to the instruction set of current time the earliest for set record;
Step D. is maximum with delay value in the candidate instruction set among the step C, and its execution time be less than or equal to the instruction of current time and find out, be arranged in current scheduling time groove, and then, upgrade candidate instruction and gather according to the data dependency graph;
Step e. the assembly language code that output scheduling is later.
2. the instruction scheduling method towards dsp chip as claimed in claim 1 is characterized in that the topological sorting between the structure assembly routine fundamental block statement is based on linear dispatching algorithm in the described steps A.
3. the instruction scheduling method towards dsp chip as claimed in claim 2 is characterized in that among the described step B calculating the length of delay delay of every instruction in the assembly language program(me) fundamental block, and its computing formula is as follows:
Exectime(n wherein) instruct needed periodicity for carrying out the n bar, and late_delay (n, m)=latency (linst (n), linst (m))+delay (m)+1; Latency (linst (n), linst (m)) is used to calculate needs the clock periodicity that keeps between two instructions.
4. the instruction scheduling method towards dsp chip as claimed in claim 3 is characterized in that described step D judges the execution in step E if instruction scheduling finishes, otherwise repeated execution of steps C after complete.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103108044A (en) * | 2013-02-04 | 2013-05-15 | 南京大学 | Web service combination method based on dependence graph reducing and quality of service (QoS) holding |
| CN105843660A (en) * | 2016-03-21 | 2016-08-10 | 同济大学 | Code optimization scheduling method for encoder |
| CN108107872A (en) * | 2017-12-28 | 2018-06-01 | 北京翼辉信息技术有限公司 | A kind of network-based DSP applications on-line debugging system and adjustment method |
| CN111104169A (en) * | 2017-12-29 | 2020-05-05 | 上海寒武纪信息科技有限公司 | Instruction list scheduling method and device, computer equipment and storage medium |
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| US5202993A (en) * | 1991-02-27 | 1993-04-13 | Sun Microsystems, Inc. | Method and apparatus for cost-based heuristic instruction scheduling |
| CN1485735A (en) * | 2002-08-22 | 2004-03-31 | ���µ�����ҵ��ʽ���� | Display device and driving method thereof |
| CN1670699A (en) * | 2004-03-19 | 2005-09-21 | 中国科学院计算技术研究所 | A micro-dispatching method supporting directed cyclic graph |
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Patent Citations (3)
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| US5202993A (en) * | 1991-02-27 | 1993-04-13 | Sun Microsystems, Inc. | Method and apparatus for cost-based heuristic instruction scheduling |
| CN1485735A (en) * | 2002-08-22 | 2004-03-31 | ���µ�����ҵ��ʽ���� | Display device and driving method thereof |
| CN1670699A (en) * | 2004-03-19 | 2005-09-21 | 中国科学院计算技术研究所 | A micro-dispatching method supporting directed cyclic graph |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103108044A (en) * | 2013-02-04 | 2013-05-15 | 南京大学 | Web service combination method based on dependence graph reducing and quality of service (QoS) holding |
| CN103108044B (en) * | 2013-02-04 | 2015-08-19 | 南京大学 | A kind of based on dependency graph about subtract with QoS keep web service composition method |
| CN105843660A (en) * | 2016-03-21 | 2016-08-10 | 同济大学 | Code optimization scheduling method for encoder |
| CN105843660B (en) * | 2016-03-21 | 2019-04-02 | 同济大学 | A kind of code optimization dispatching method of compiler |
| CN108107872A (en) * | 2017-12-28 | 2018-06-01 | 北京翼辉信息技术有限公司 | A kind of network-based DSP applications on-line debugging system and adjustment method |
| CN108107872B (en) * | 2017-12-28 | 2019-03-22 | 北京翼辉信息技术有限公司 | A kind of network-based DSP application on-line debugging system and adjustment method |
| CN111104169A (en) * | 2017-12-29 | 2020-05-05 | 上海寒武纪信息科技有限公司 | Instruction list scheduling method and device, computer equipment and storage medium |
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Application publication date: 20110518 |