CN102024716B - 半导体器件以及制造半导体器件的方法 - Google Patents

半导体器件以及制造半导体器件的方法 Download PDF

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CN102024716B
CN102024716B CN201010286621.2A CN201010286621A CN102024716B CN 102024716 B CN102024716 B CN 102024716B CN 201010286621 A CN201010286621 A CN 201010286621A CN 102024716 B CN102024716 B CN 102024716B
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semiconductor packages
compensation structure
stress compensation
substrate
conductive layer
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CN102024716A (zh
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林耀剑
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明提供半导体器件以及制造半导体器件的方法。一种半导体器件含有具有腔体的PCB，其中该腔体形成在所述PCB的第一表面中。诸如密封剂或者虚设小片的应力补偿结构被沉积在所述腔体中。绝缘层形成在所述PCB和应力补偿结构上。所述绝缘层的一部分被去除以暴露所述应力补偿结构。导电层形成在所述应力补偿结构上。焊接掩膜层形成在所述导电层上具有朝所述导电层的开口。半导体封装被安装在所述腔体上。所述半导体封装是大阵列WLCSP。凸块电连接所述半导体封装与导电层。所述半导体封装电连接到所述导电层。所述应力补偿结构的CTE被选择为与所述半导体封装的CTE大体上相似或者匹配以减小所述半导体封装与PCB之间的应力。

Description

半导体器件以及制造半导体器件的方法
技术领域
本发明一般地涉及半导体器件，并且更具体地涉及在包含具有与大阵列WLCSP的CTE相似的CTE的密封剂或者虚设小片(dummy die)的印刷电路板或者衬底中形成腔体(cavity)的半导体器件以及方法。
背景技术
半导体器件在现代电子产品中是常见的。半导体器件在电部件的数量和密集程度方面不同。分立的半导体器件通常包含一种类型的电部件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器以及功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件典型地包含数百到数百万个电部件。集成半导体器件的例子包括微控制器、微处理器、电荷耦合器件、太阳能电池以及数字微镜器件(DMD)。
半导体器件执行广泛的功能，诸如高速计算、传送和接收电磁信号、控制电子器件、将太阳光转换为电力以及为电视显示产生视觉投影。在娱乐、通信、功率转换、网络、计算机以及消费品领域中都能找到半导体器件。在军事应用、航空、汽车、工业控制器以及办公室设备中也找得到半导体器件。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许它的导电性由电场或者基极电流(base current)的施加或者通过掺杂的工艺来操纵。掺杂将杂质引入到半导体材料以操纵和控制半导体器件的导电。
半导体器件包含有源和无源的电结构。有源结构包括双极和场效应晶体管，其控制电流的流动。通过改变掺杂的程度以及电场或者基极电流的施加，晶体管促进或者限制电流的流动。无源结构包括电阻器、电容器和电感器，其产生执行各种电功能所必要的电压和电流之间关联。无源和有源结构被电连接来形成电路，所述电路允许半导体器件执行高速计算以及其它有用的功能。
半导体器件通常使用两种复杂的制造工艺来制造，即前端制造和后端制造，每种工艺都潜在地涉及数百个步骤。前端制造涉及多个小片(die)在半导体晶圆(wafer)的表面上的形成。每个小片典型地是相同的并且包含通过将有源和无源部件电连接所形成的电路。后端制造涉及从完成的晶圆中分割出(singulate)单独的小片并且对该小片进行封装以提供结构支持和环境隔离。
半导体制造的一个目标是生产更小的半导体器件。更小的器件通常消耗更少的功率、具有更高的性能并且可以更高效地被生产。另外，更小的半导体器件具有更小的占用面积(footprint)，这对于更小的终端产品是理想的。更小的小片尺寸可以通过前端工艺的改进来实现，产生具有更小、更高密度的有源和无源部件的小片。后端工艺可以通过电互连和封装材料方面的改进来产生具有更小的占用面积的半导体器件封装。
在晶圆级芯片尺寸封装(WLCSP)以及扇出型晶圆级芯片尺寸封装(FO-WLCSP)中，半导体小片在所述封装内被堆叠并且垂直互连。随着对信号处理能力的需要增加，大阵列的堆叠半导体小片常常被装载在WLCSP和FO-WLSCP内。大阵列WLCSP/FO-WLCSP被安装到PCB。然而，大阵列WLCSP/FO-WLCSP可能引起故障并且降低板级可靠性，特别是在温度周期变化测试期间，这部分地归因于由所述PCB与大阵列WLCSP/FO-WLCSP之间的热膨胀系数(CTE)的不匹配所引起的应力。
发明内容
对存在于PCB上而不会不利地影响板级可靠性的大阵列WLCSP/FO-WLCSP有需要。因此，在一个实施例中，本发明是制造半导体器件的方法，该方法包括以下步骤：提供衬底，在所述衬底的第一表面中形成腔体，将具有CTE的密封剂沉积在所述腔体中，在所述衬底和密封剂上形成绝缘层，去除所述绝缘层的一部分以暴露所述密封剂，在所述密封剂上形成第一导电层以及将具有CTE的半导体封装安装在所述腔体上。所述半导体封装电连接到所述第一导电层。所述密封剂的CTE被选择为与所述半导体封装的CTE相似以便减小所述半导体封装与衬底之间的应力。
在另一个实施例中，本发明是制造半导体器件的方法，该方法包括以下步骤：提供衬底，在所述衬底的第一表面中形成腔体，将具有CTE的应力补偿结构安装在所述腔体中，在所述衬底和应力补偿结构上形成绝缘层，去除所述绝缘层的一部分以暴露所述应力补偿结构，在所述应力补偿结构上形成导电层以及将具有CTE的半导体封装安装在所述腔体上。所述半导体封装电连接到所述导电层。所述应力补偿结构的CTE被选择为与所述半导体封装的CTE相似以便减小所述半导体封装与衬底之间的应力。
在另一个实施例中，本发明是制造半导体器件的方法，该方法包括提供以下步骤：提供衬底，在所述衬底的第一表面中形成腔体，将具有CTE的应力补偿结构沉积在所述腔体中，在所述应力补偿结构上形成导电层以及将具有CTE的半导体封装安装在所述腔体上。所述半导体封装电连接到所述导电层。所述应力补偿结构的CTE被选择为与所述半导体封装的CTE相似以便减小所述半导体封装与衬底之间的应力。
在另一个实施例中，本发明是半导体器件，该半导体器件包括具有腔体的衬底，所述腔体形成在所述衬底的第一表面中。具有CTE的应力补偿结构被沉积在所述腔体中。导线层形成在所述应力补偿结构上。具有CTE的半导体封装被安装在所述腔体上。所述半导体封装电连接到所述导电层。所述应力补偿结构的CTE被选择为与所述半导体封装的CTE相似以便减小所述半导体封装与衬底之间的应力。
附图说明
图1示意了不同类型的封装被安装在其表面上的PCB；
图2a-2c示意了被安装在PCB上的有代表性的半导体封装的进一步的细节；
图3a-3d示意了在PCB中形成腔体的过程，所述腔体被填充有具有与安装在所述腔体上的FO-WLCSP的CTE匹配的CTE的密封剂；以及
图4示意了具有腔体的PCB，所述腔体包含具有与安装在所述腔体上的FO-WLCSP的CTE匹配的CTE的虚设小片。
具体实施方式
参考附图在下面的说明中用一个或者多个实施例描述了本发明，在附图中相似的数字表示相同或者相似的元件。虽然根据用于实现本发明的目的的最佳模式来描述本发明，本领域的技术人员将理解的是其旨在覆盖可以被包括在由被下面的公开内容和附图所支持的随附的权利要求及其等价所定义的本发明的精神和范围内的替换、修改以及等价。
通常使用两个复杂的制造工艺来制造半导体器件：前端制造和后端制造。前端制造涉及多个小片在半导体晶圆上的形成。晶圆上的每个小片包含有源和无源电部件，所述电部件被电连接以形成功能电路。诸如晶体管和二极管的有源电部件有控制电流的流动的能力。诸如电容器、电感器、电阻器和变压器(transformer)的无源电部件产生执行电路功能所必要的电压和电流之间的关联。
无源和有源部件通过包括掺杂、沉积、光刻、蚀刻和平面化的一系列工艺步骤被形成在半导体晶圆的表面之上。掺杂通过诸如离子注入或者热扩散等技术将杂质引入半导体材料中。该掺杂工艺改变有源器件中的半导体材料的导电性，将该半导体材料转换成绝缘体、导体或者响应电场或者基极电流动态地改变半导体材料的导电性。晶体管包含变化的掺杂类型和程度的区域，这是必要地被布置使得允许该晶体管根据电场或者基极电流的施加而促进或者限制电流的流动。
有源和无源部件通过具有不同电特性的材料的层来形成。这些层可以通过部分地由所沉积的材料的类型所确定的各种沉积技术来形成。举例来说，薄膜沉积可以涉及化学气相沉积(CVD)、物理气相沉积(PVD)、电解电镀以及化学镀工艺。每个层通常被图形化以形成有源部件部分、无源部件部分或者部件之间的电连接的部分。
这些层可以使用光刻来图形化，所述光刻涉及例如为光致抗蚀剂的光敏材料在将被图形化的层上的沉积。使用光将图案从光掩膜向光致抗蚀剂传递。使用溶剂将光致抗蚀剂图案的经受光的部分去除，暴露下面的层的将被图形化的部分。光致抗蚀剂的剩余部分被去除，留下图形化的层。可替换地，一些类型的材料通过使用诸如化学镀和电解电镀等技术将所述材料直接沉积到由先前的沉积/蚀刻工艺所形成的区域或者空隙处中而被图形化。
在现有的图案上沉积材料的薄膜会扩大下面的图案并且产生非均匀平整的表面。均匀平整的表面被需要以产生更小并且更密集组装的有源和无源部件。平面化可以被用于将材料从晶圆的表面去除并且产生均匀平整的表面。平面化涉及用抛光垫抛光晶圆的表面。研磨材料和腐蚀性化学品在抛光期间被加入到晶圆的表面。化学品的研磨和腐蚀性作用的结合的机械作用去除任何不规则的外形，产生均匀平整的表面。
后端制造指将完成的晶圆切割或者分割成单独的小片并且接着封装该小片以得到结构支持和环境隔离。为分割出该小片，该晶圆沿被称为划片街区或者划线(saw streets or scribes)的晶圆的非功能性区域被刻痕并且被切断(break)。使用激光切割工具或者锯条来分割晶圆。在分割之后，单独的小片被安装到封装衬底，该封装衬底包括用于与其它系统部件互连的管脚或者接触垫。形成在半导体小片上的接触垫接着被连接到封装内的接触垫。电连接用焊料凸块、钉头凸块(studbump)、导电胶或者引线键合(wirebond)来制作。密封剂或者其它成型材料被沉积在所述封装上以提供物理支持和电隔离。完成后的封装接着被插入到电系统中并且半导体器件的功能对于其它系统部件可用。
图1示意了具有芯片载体衬底或者印刷电路板(PCB)52的电子器件50，其中多个半导体封装被安装在其表面上。电子器件50可以具有一种类型的半导体封装或者多种类型的半导体封装，这取决于应用。不同类型的半导体封装在图1中为示意的目的被示出。
电子器件50可以是使用半导体器件来执行一个或者多个电功能的独立系统。可替换地，电子器件50可以是较大的系统的子部件。举例来说，电子器件50可以是图形卡、网络接口卡或者可以被插入计算机的其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件或者其它半导体小片或者电部件。
在图1中，PCB 52提供通用的衬底用于被安装在该PCB上的半导体封装的结构支持和电互连。使用蒸发、电解电镀、化学镀、丝网印刷或者其它合适的金属沉积工艺在PCB 52的表面上或者在PCB 52的层之内形成导电的信号轨迹54。信号轨迹54在半导体封装、被安装的部件以及其它外部的系统部件中的每一个之间提供电通信。轨迹54还向半导体封装中的每一个提供电源和地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是用于机械地以及电性地将半导体小片附接于中间载体的技术。第二级封装涉及机械地以及电性地将该中间载体附接于PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中小片被机械地以及电性地直接安装在PCB上。
为了示意的目的，若干类型的第一级封装，包括引线键合封装56和倒装芯片58在PCB 52上被示出。另外，若干类型的第二级封装，包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插式封装(DIP)64、栅格阵列封装(LGA)66、多芯片模块(MCM)68、四侧无引脚扁平封装(QFN)70以及四方扁平封装72被示出为安装在PCB 52上。取决于系统要求，被配置为第一和第二级封装样式的任何组合的半导体封装的任何组合、以及其它电子部件可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附接的半导体封装，而其它实施例要求多个互连的封装。通过在单个衬底上结合一个或者多个半导体封装，制造商可以将预制的部件并入电子器件和系统。由于半导体封装包括复杂的功能，可以使用更便宜的部件以及精简的制造工艺来制造电子器件。由此得到的器件出故障的可能性更小并且制造起来更便宜，从而为消费者产生更低的成本。
图2a-2c示出示范性的半导体封装。图2a示意被安装在PCB 52上的DIP 64的另外的细节。半导体小片74包括有源区域，该有源区域包含被实现为形成在该小片内并且根据该小片的电设计电互连的有源器件、无源器件、导电层以及介电层的模拟或者数字电路。举例来说，电路可以包括一个或者多个晶体管、二极管、电感器、电容器、电阻器以及在半导体小片74的有源区域内形成的其它电路元件。接触垫76是诸如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或者银(Ag)的导电材料的一个或者多个层，并且被电连接到形成在半导体小片74内的电路元件。在DIP 64的组装期间，使用金硅共晶层或者诸如热环氧树脂的粘合剂材料将半导体小片74安装在中间载体78上。封装主体包括绝缘封装材料，诸如聚合物或者陶瓷。导线80和引线键合82提供在半导体小片74和PCB 52之间的电互连。密封剂84被沉积在所述封装上以通过防止水分和微粒进入所述封装并且污染小片74或者引线键合82来进行环境保护。
图2b示意了被安装在PCB 52上的BCC 62的另外的细节。使用底部填充(underfill)或者环氧树脂粘合剂材料92将半导体小片88安装在载体90上。引线键合94在接触垫96和98之间提供第一级封装互连。成型化合物或者密封剂100被沉积在半导体小片88和引线键合94上以便为所述器件提供物理支持和电隔离。使用诸如电解电镀或者化学镀等合适的金属沉积工艺在PCB 52的表面上形成接触垫102以防止氧化。接触垫102电连接到PCB 52中的一个或者多个导电的信号轨迹54。凸块104形成在BCC 62的接触垫98和PCB 52的接触垫102之间。
在图2c中，通过倒置芯片型的第一级封装将半导体小片58面朝下安装在中间载体106。半导体小片58的有源区域108包含被实现为根据该小片的电设计所形成的有源器件、无源器件、导电层以及介电层的模拟或者数字电路。举例来说，所述电路可以包括一个或者多个晶体管、二极管、电感器、电容器、电阻器以及有源区域108内的其它电路元件。半导体小片58通过凸块110电性地以及机械地被连接到载体106。
使用凸块112通过BGA型的第二级封装将BGA 60电性地以及机械地连接到PCB 52。半导体小片58通过凸块110、信号线114以及凸块112电连接到PCB 52中导电的信号轨迹54。成型化合物或者密封剂116被沉积在半导体小片58和载体106上以便为所述器件提供物理支持和电隔离。倒置芯片半导体器件提供从半导体小片58上的有源器件到PCB 52上的传导轨迹的短的电传导路径以减小信号传播距离、降低电容以及改进整体的电路性能。在另一个实施例中，可以使用倒置芯片样式型的第一级封装将半导体小片58电性地以及机械地直接连接到PCB 52而不用中间载体106。
图3a-3d相对于图1和2a-2c示意了在PCB或者衬底中形成腔体的过程，其中所述腔体被填充有具有与安装在所述腔体上的WLCSP或者FO-WLCSP的CTE大体上相似或者匹配的CTE的密封剂。在图3a中，PCB或者衬底120是用于根据PCB的设计具有点对点电互连的电子部件的机械支持结构。PCB 120具有与非导电的或者介电衬底层叠的一个或者多个导电层122。所述衬底可以是一个或者多个层叠的以酚醛棉纸、环氧树脂、树脂、编织玻璃(woven glass)、毛面玻璃(matte glass)、聚酯以及其它增强纤维或者织物的组合预先浸渍(预浸渍)的聚四氟乙烯的层。PCB 120具有高介电常数、低损耗正切以及大约2.15g/cm3的密度。导电层122可以是用于电连接的通过电解电镀或者化学镀形成的Al、Cu、Sn、Ni、Au、Ag或者其它合适的电传导材料的一个或者多个层。PCB 120以及导电层122的布局通常使用丝网印刷、光刻、PCB研磨(milling)、化学镀或者电镀工艺。PCB 120可以具有用钻头或者激光钻孔切割的多个通孔。导电层122从PCB120的顶面124延伸至PCB 120的底面126。
腔体128在表面124中形成，该表面124具有与稍后安装在该腔体上的半导体封装140大致一样尺寸的区域。腔体128可以通过激光、钻孔、刳刨、削磨(skiving)或者刻痕(scoring)来形成。在一个实施例中，对于具有100-800微米(μm)的厚度的PCB 120，腔体128被形成至50-600μm的深度。
在图3c，使用焊膏印刷、压模成型、传递成型、液体密封剂成型、真空层压、旋涂或者其它合适的涂敷器将密封剂或者成型化合物130沉积在腔体128中。密封剂130可以是聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或者具有合适的填料的聚合物。在一个实施例中，通过精确的量的控制下的喷射分配工艺将密封剂130分配到腔体128中以分配适量的密封剂来填充腔体128。所分配的密封剂130被成型为与PCB 120的顶面124共平面的水平，如图3b所示。
在图3c中，可选的绝缘或者钝化层132在PCB 120和绝缘层130上被形成。绝缘层132可以是光敏绝缘聚合物材料的一个或者多个层。使用层压、印刷、旋涂或者喷涂来形成绝缘层132。通过蚀刻工艺或者激光钻孔将绝缘层132的一部分去除以暴露导电层122和密封剂130。
使用诸如PVD、CVD、溅射、电解电镀以及化学镀工艺的图形化和金属沉积工艺在导电层122、密封剂130和绝缘层132上形成电传导层134。导电层134可以是Al、Cu、Sn、Ni、Au、Ag或者其它合适的电传导材料的一个或者多个层。导电层134的一个部分电连接到导电层122。导电层134的其它部分可以是电共有的或者电隔离的，这取决于半导体器件的设计和功能。
焊接掩膜层(solder masking)136形成在PCB 120上，具有开口以暴露导电层134用于下一级的互连。焊接掩膜层136中的开口可以不与绝缘层132中的开口精确地重叠。
使用蒸发、电解电镀、化学镀、球状滴落(ball drop)或者丝网印刷工艺将电传导的凸块材料沉积在PCB 120的底面126上并且将其电连接到导电层122。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及其组合，连同可选的助熔剂溶液。举例来说，凸块材料可以是共晶Sn/Pb、高铅焊料或者无铅焊料。使用合适的附接或者焊接(bonding)工艺将凸块材料焊接于导电层122。在一个实施例中，通过将凸块材料加热到其熔点之上使该材料重熔(reflow)以形成球形的团或者凸块138。在一些应用中，凸块138第二次被重熔以改进到导电层122的电接触。凸块还可以被压缩焊接于导电层122。凸块138代表可以在导电层122上被形成的一种类型的互连结构。该互连结构还可以在PCB 120的顶面或者底面上使用焊接线、钉头凸块、微凸块或者其它电互连。
在图3d中，通过取向朝PCB 120的接触垫142将半导体封装或者部件140安装在包含密封剂130的腔体128上。半导体封装140是包含大阵列的堆叠半导体小片的WLCSP或者FO-WLCSP。每个半导体小片包含被实现为形成在该小片内并且根据该小片的电设计和功能电互连的有源器件、无源器件、导电层以及介电层的模拟或者数字电路。举例来说，电路可以包括一个或者多个晶体管、二极管、以及形成在该小片的有源表面内的其它电路元件以实现模拟电路或者数字电路，诸如数字信号处理器(DSP)、ASIC、存储器或者其它信号处理电路。半导体封装140还可以包含诸如电感器、电容器和电阻器的IPD用于RF信号处理。典型的RF系统需要在一个或者多个半导体封装中有多个IPD以执行必要的电功能。凸块146将接触垫142电连接到导电层134。凸块146可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。
电子系统148具有安装在PCB 120中的腔体128上的半导体封装140，如图3a-3d所示。半导体封装140是WLCSP或者FO-WLCSP，其包含大阵列的堆叠半导体小片以得到额外的信号处理能力。半导体封装140具有诸如硅、锗、砷化镓、三氯化铟或者碳化硅的基底材料用于结构支持。密封剂130是被选择为具有与半导体封装140的基底材料的CTE大体上相似或者匹配的CTE的应力补偿结构，半导体封装140的基底例如具有2-10×10-6/℃的CTE的硅。电子系统148的可靠性通过将半导体封装140安装在被填充有密封剂130的腔体128上而得以提高，因为该密封剂的CTE被选择为与该封装的基底材料的CTE相似。由于温度变化所引起的半导体封装140的任何膨胀或者收缩通过导电层134被传导并且由具有相似的热膨胀特性的密封剂130来补偿。半导体封装140与密封剂130大体上相似的CTE减小应力以及相关的故障，特别是在温度周期变化测试期间。
图4示出了被安装在PCB或者衬底的腔体中的虚设小片。该虚设小片具有与被安装在腔体上的WLCSP或者FO-WLCSP的CTE大体上相似或者匹配的CTE。PCB或者衬底150为根据该PCB的设计具有点到点电互连的电子部件提供机械支持结构。PCB 150具有与非导电的或者介电衬底层叠的一个或者多个导电层152。所述衬底可以是一个或者多个层叠的以酚醛棉纸、环氧树脂、树脂、编织玻璃、毛面玻璃、聚酯以及其它增强纤维或者织物的组合预先浸渍的聚四氟乙烯的层。PCB 150具有高介电常数、低损耗正切以及大约2.15g/cm3的密度。导电层152可以是用于电连接的通过电解电镀或者化学镀形成的Al、Cu、Sn、Ni、Au、Ag或者其它合适的电传导材料的一个或者多个层。PCB 150以及导电层152的布局通常使用丝网印刷、光刻、PCB研磨、化学镀或者电镀工艺。PCB 150可以具有通过钻头或者激光钻孔切割的多个通孔。导电层152从PCB 150的顶面154延伸至PCB150的底面156。
腔体158形成在表面154中，该表面154具有与稍后安装在该腔体上的半导体小片大致一样尺寸的区域。腔体158可以通过激光、钻孔、刳刨、削磨或者刻痕来形成。在一个实施例中，对于具有100-800μm的厚度的PCB 150，腔体158被形成至50-600μm的深度。
通过小片接触粘合剂162将虚设小片160安装在腔体158中。虚设小片160可以具有有源表面或者没有有源表面。举例来说，该虚设小片可以在所述表面上仅具有电感器。举例来说，使用焊膏印刷、压模成型、传递成型、液体密封剂成型、真空层压、旋涂或者其它合适的涂敷器将可选的密封剂或者成型化合物沉积在虚设小片160周围。该密封剂可以是聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或者具有合适的填料的聚合物。虚设小片160的顶面与顶面154共平面。
绝缘或者钝化层164形成在PCB 150和虚设小片160上。绝缘层164可以是光敏绝缘聚合物材料的一个或者多个层。使用层压、印刷、旋涂或者喷涂来形成绝缘层164。通过蚀刻工艺或者激光钻孔将绝缘层164的一部分去除以暴露导电层152和虚拟小片160。
使用诸如PVD、CVD、溅射、电解电镀以及化学镀工艺的图形化和金属沉积工艺在导电层152、虚设小片160和绝缘层164上形成电传导层166。导电层166可以是Al、Cu、Sn、Ni、Au、Ag或者其它合适的电传导材料的一个或者多个层。导电层166的一个部分电连接到导电层152。导电层166的其它部分可以是电共有的或者电隔离的，这取决于半导体器件的设计和功能。
焊接掩膜层168形成在PCB 160上，具有开口以暴露导电层166用于下一级的互连。焊接掩膜层168中的开口可以不与绝缘层164中的开口精确地重叠。
使用蒸发、电解电镀、化学镀、球状滴落或者丝网印刷工艺将电传导的凸块材料沉积在PCB 150的底面156上并且将其电连接到导电层152。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及其组合，连同可选的助熔剂溶液。举例来说，凸块材料可以是共晶Sn/Pb、高铅焊料或者无铅焊料。使用合适的附接或者焊接(bonding)工艺将凸块材料焊接于导电层152。在一个实施例中，通过将凸块材料加热到其熔点之上使该材料重熔以形成球形的团或者凸块170。在一些应用中，凸块170第二次被重熔以改进到导电层152的电接触。凸块还可以被压缩焊接于导电层152。凸块170代表可以形成在导电层122上的一种类型的互连结构。互连结构还可以使用焊接线、钉头凸块、微凸块或者其它电互连。
通过取向朝PCB 150的接触垫174将半导体封装或者部件172安装在包含虚设小片160的腔体158上。半导体封装172是包含多个堆叠的半导体小片的WLCSP或者FO-WLCSP。每个半导体小片包含被实现为形成在该小片内并且根据该小片的电设计和功能电互连的有源器件、无源器件、导电层以及介电层的模拟或者数字电路。举例来说，电路可以包括一个或者多个晶体管、二极管、以及在该小片的有源表面内被形成的其它电路元件以实现模拟电路或者数字电路，诸如DSP、ASIC、存储器或者其它信号处理电路。半导体封装172还可以包含诸如电感器、电容器和电阻器的IPD用于RF信号处理。典型的RF系统需要在一个或者多个半导体封装中有多个IPD以执行必要的电功能。凸块178将接触垫174电连接到导电层166。凸块178可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。
电子系统180具有安装在PCB 150中的腔体158上的半导体封装172。半导体封装172是WLCSP或者FO-WLCSP，其包含大阵列的堆叠的半导体小片以得到额外的信号处理能力。半导体封装172具有诸如硅、锗、砷化镓、三氯化铟或者碳化硅的基底材料用于结构支持。具有可选的密封剂的虚设小片160是被选择为具有与半导体封装172的基底材料的CTE大体上相似或者匹配的CTE的应力补偿结构，例如具有2-10×10-6/℃的CTE的硅。电子系统180的可靠性通过将半导体封装172安装包含虚设小片160的腔体158上而得以提高，因为该虚设小片的CTE被选择为与该封装的基底材料的CTE相似。由于温度变化所引起的半导体封装172的任何膨胀或者收缩通过导电层134被传导并且由具有相似的热膨胀特性的虚设小片160来补偿。半导体封装172与虚设小片160大体上相似的CTE减小应力以及相关的故障，特别是在温度周期变化测试期间。
虽然已详细地示意了本发明的一个或者多个实施例，本领域的技术人员将理解对这些实施例的修改和适应性变化可以被进行而不背离在下面的权利要求中所阐明的本发明的范围。

Claims (27)

1.一种制造半导体器件的方法，所述方法包括：
提供衬底；
形成穿过所述衬底的第一表面的腔体；
在所述腔体中沉积非导电的密封剂；
在所述衬底和所述非导电的密封剂上形成绝缘层；
去除所述绝缘层的一部分以暴露所述非导电的密封剂；
在所述非导电的密封剂上形成第一导电层；以及
将半导体封装安装在所述腔体上，所述半导体封装电连接到所述第一导电层，其中所述非导电的密封剂具有被选择为与所述半导体封装的热膨胀系数CTE相似的CTE以减小所述半导体封装与所述衬底之间的应力。
2.如权利要求1所述的方法，其还包括在所述第一导电层上形成焊接掩膜层。
3.如权利要求1所述的方法，其还包括在所述半导体封装与第一导电层之间形成凸块。
4.如权利要求1所述的方法，其还包括：
在所述衬底中形成第二导电层；以及
在相对所述衬底的第一表面的所述衬底的第二表面上形成凸块，所述第二导电层电连接到所述凸块。
5.如权利要求1所述的方法，其还包括：
用喷射分配工艺来沉积所述非导电的密封剂；以及
成型所述非导电的密封剂使得所述非导电的密封剂的表面与所述衬底的所述第一表面共平面。
6.如权利要求1所述的方法，其中所述半导体封装是大阵列晶圆级芯片尺寸封装。
7.一种制造半导体器件的方法，所述方法包括：
提供衬底；
形成穿过所述衬底的表面的腔体；
将包括绝缘材料或虚设小片的应力补偿结构安装在所述腔体中；
在所述衬底和应力补偿结构上形成绝缘层；
去除所述绝缘层的一部分以暴露所述应力补偿结构；
在所述应力补偿结构上形成导电层；以及
将半导体封装安装在所述腔体上，所述半导体封装电连接到所述导电层，其中所述应力补偿结构具有被选择为与所述半导体封装的热膨胀系数CTE相似的CTE以减小所述半导体封装与衬底之间的应力。
8.如权利要求7所述的方法，其中所述应力补偿结构包括密封剂。
9.如权利要求7所述的方法，其还包括将密封剂沉积在所述虚设小片上。
10.如权利要求7所述的方法，其还包括在所述导电层上形成焊接掩膜层。
11.如权利要求7所述的方法，其还包括在所述虚设小片上形成电感器。
12.如权利要求7所述的方法，其中所述半导体封装是大阵列晶圆级芯片尺寸封装。
13.一种制造半导体器件的方法，所述方法包括：
提供衬底；
形成穿过所述衬底的表面的腔体；
将包括绝缘材料或虚设小片的应力补偿结构安置在所述腔体中，其中所述应力补偿结构的表面与所述衬底的表面共平面；
在所述衬底和所述应力补偿结构上形成绝缘层；
去除所述绝缘层的一部分以暴露所述应力补偿结构；
在所述应力补偿结构上形成导电层；以及
将半导体封装安装在所述腔体上，所述半导体封装电连接到所述导电层，其中所述应力补偿结构具有被选择为与所述半导体封装的热膨胀系数CTE相似的CTE以减小所述半导体封装与衬底之间的应力。
14.如权利要求13所述的方法，其中所述应力补偿结构包括密封剂。
15.如权利要求14所述的方法，其还包括用喷射分配工艺来沉积所述密封剂。
16.如权利要求13所述的方法，其还包括在所述导电层上形成焊接掩膜层。
17.如权利要求13所述的方法，其还包括在所述半导体封装和所述导电层之间形成凸块。
18.一种半导体器件，所述半导体器件包括：
包括腔体的衬底，所述腔体形成为穿过所述衬底的表面；
安置在所述腔体中的包括绝缘材料或虚设小片的应力补偿结构，其中所述应力补偿结构的表面与所述衬底的表面共平面；
形成在所述应力补偿结构上的导电层；以及
安装在所述腔体上的半导体封装，所述半导体封装电连接到所述导电层，其中所述应力补偿结构具有被选择为与所述半导体封装的热膨胀系数CTE相似的CTE以减小所述半导体封装与衬底之间的应力。
19.如权利要求18所述的半导体器件，其中所述应力补偿结构包括密封剂。
20.如权利要求18所述的半导体器件，其中所述应力补偿结构包括所述虚设小片，在所述应力补偿结构的表面上形成电感器。
21.如权利要求18所述的半导体器件，其还包括形成在所述半导体封装与所述导电层之间的凸块。
22.如权利要求18所述的半导体器件，其中所述半导体封装是大阵列晶圆级芯片尺寸封装。
23.一种制造半导体器件的方法，所述方法包括：
提供衬底；
形成穿过所述衬底的表面的腔体；
在所述腔体中安置应力补偿结构；
在所述衬底和所述应力补偿结构上形成绝缘层；
去除所述绝缘层的一部分以暴露所述应力补偿结构；
在所述应力补偿结构上形成互连结构；以及
在所述互连结构上安装包括第一和第二接触垫的半导体封装，其中所述第一和第二接触垫安置于所述腔体的覆盖区中，所述应力补偿结构包括与所述半导体封装的热膨胀系数CTE相似的CTE以减小所述半导体封装与所述衬底之间的应力。
24.如权利要求23所述的方法，其中所述应力补偿结构包括绝缘材料。
25.如权利要求23所述的方法，其中所述应力补偿结构包括虚设小片。
26.如权利要求25所述的方法，其还包括在所述虚设小片上沉积密封剂。
27.如权利要求23所述的方法，其中所述应力补偿结构的表面与所述衬底的表面共平面。
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