CN101919053B - 经封装集成电路、封装集成电路的方法和集成电路封装系统 - Google Patents

经封装集成电路、封装集成电路的方法和集成电路封装系统 Download PDF

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CN101919053B
CN101919053B CN2009801025126A CN200980102512A CN101919053B CN 101919053 B CN101919053 B CN 101919053B CN 2009801025126 A CN2009801025126 A CN 2009801025126A CN 200980102512 A CN200980102512 A CN 200980102512A CN 101919053 B CN101919053 B CN 101919053B
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electronic substrate
screen
adhesive
emi
integrated circuit
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CN101919053A (zh
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斯坦利·克雷格·贝丁菲尔德
让-弗朗索瓦·德鲁阿尔
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Texas Instruments Inc
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Texas Instruments Inc
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    • H01L2924/3025—Electromagnetic shielding

Abstract

本发明揭示一种经封装集成电路(IC)(100)，其包含第一衬底(110)，所述第一衬底包括第一多个层及在所述第一衬底的上表面处的第一电路耦合特征(112)，所述第一多个层包含第一电磁干扰屏蔽层(132)。所述经封装IC还包含第二衬底(106)，所述第二衬底具有通过导电粘合剂材料(136)附接到所述第一衬底的下表面的上表面。所述第二衬底包含第二多个层及在所述第二衬底的下表面处的第二电路耦合特征(108)。所述第一多个层包含第二EMI屏蔽层(134)。所述经封装IC进一步包含功能裸片(124)，其安置于所述第一衬底与所述第二衬底之间且功能上耦合到所述第一电路耦合特征及/或所述第二电路耦合特征。在所述经封装IC中，所述粘合剂材料电耦合所述第一屏蔽层与所述第二屏蔽层。

Description

经封装集成电路、封装集成电路的方法和集成电路封装系统
技术领域
大体来说，此涉及集成电路封装，且更特定来说，涉及用于调制集成电路封装中电磁干扰的结构和技术。 
背景技术
随着对具有增加功能性的更快速、更小型电子产品的需求不断增加，一些设计者开始致力于系统级封装(SIP)解决方案。SIP通常包含集成到单个IC封装中的数个不同类型的集成电路(IC)。然而，近些年来，已使用堆叠式封装方案(例如，层叠封装(POP)配置)代替了SIP方案。通常，通过允许堆叠不同的半导体封装，可减小电子产品中用于半导体封装所需的占用面积大小。此外，由于一些堆叠式封装(例如，POP封装)通过允许堆叠不同组合半导体封装来提供模块化解决方案，因此设计者通常可使用几个单个半导体封装占用面积设计不同类型电子装置。 
已知一些类型的集成电路(IC)(包含堆叠式封装中所使用的那些集成电路)在操作周期期间辐射相对大量的电磁能量。举例来说，微处理器及其它数字处理装置被公认为是计算机系统中电磁辐射的主要来源。此类装置所辐射的电磁能量可干扰在辐射IC(包含同一堆叠式封装中的那些IC)附近的其它装置或电路的操作且因此通常是不期望的。 
过去曾使用过若干技术来减小从IC发射的电磁干扰(EMI)的水平，或保护IC使其免受EMI。通常，此类技术需要使用围绕其外围可具有多个间隔开的支腿的冲压板金属笼部件在所述IC周围形成大体导电笼结构。接着，将所述笼部件放置于所述IC封装上方且将其耦合到下伏电路板上的对应接地垫。所述电路板的接地垫使用(举例来说)通孔连接各自以导电方式耦合到所述电路板的接地平面。以此方式，在IC周围形成称为法拉第(Faraday)笼的用于阻挡EMI的大体导电屏蔽。然而，在堆叠式封装方案(例如，POP封装)中使用常规法拉第笼通常增加所述封装的总体尺寸且可消除最初通过堆叠式封装方案所获得的至少一部分大小优势。 
发明内容
随着堆叠式封装方案(例如，POP封装)的日益普及，其中使用所述堆叠式封装方案的应用的数目也得以增加。然而，将EMI敏感IC并入到此类封装中因法拉第笼的并入所产生的增加尺寸而为困难的。更糟的是，如果设计者希望将EMI产生IC及EMI敏感IC并入到单个POP封装中，那么EMI产生IC的接近可阻止这样做。对于此类封装技术，发明者已发现，添加常规法拉第笼结构不但增加POP封装的大小，而且增加封装及其中使用所述封装的电子装置的成本及复杂性。响应于这些问题，本发明的实施例提供用于在不添加单独法拉第笼结构的情况下在堆叠式IC封装中实施法拉第笼的方案。特定来说，发明者已发现，通过将屏蔽层并入现有用于形成可堆叠封装的电子衬底中并施加包括聚合物的导电环氧树脂以电接触屏蔽层，可在不增加封装总体尺寸且不需要将额外结构并入到所述封装中的情况下在其之间提供法拉第笼。 
在本发明的一个实施例中，提供经封装集成电路。所述经封装集成电路可包含第一电子衬底，所述第一电子衬底具有第一多个层及在所述第一电子衬底的上表面处的至少第一电路耦合特征，所述第一多个层包括至少第一电磁干扰(EMI)屏蔽层。所述经封装集成电路还可包含第二电子衬底，所述第二电子衬底具有通过导电粘合剂材料的一个或一个以上部分附接到第一电子衬底的下表面的上表面，所述第二电子衬底包括第二多个层及在所述第二电子衬底的下表面处的至少第二电路耦合特征，所述第一多个层包括至少第二EMI屏蔽层。在所述经封装集成电路中，至少一个功能裸片设置于所述第一电子衬底与所述第二电子衬底之间且功能上耦合到所述第一电路耦合特征及所述第二电路耦合特征中的至少一者。此外，所述粘合剂材料部分中的每一者均电耦合所述第一屏蔽层与所述第二屏蔽层。 
在本发明的另一实施例中，提供用于封装集成电路的方法。所述方法可包含提供第一电子衬底，所述第一电子衬底包括第一多个层及在所述第一电子衬底的上表面处的至少第一电路耦合特征，其中所述第一多个层包括至少第一电磁干扰(EMI)屏蔽层。所述方法还可包含提供第二电子衬底，所述第二电子衬底包括第二多个层及在所述第二电子衬底的下表面处的至少第二电路耦合特征，其中所述第二多个层包括至少第二EMI屏蔽层。所述方法可进一步包含将至少一个功能裸片附接到所述第一电子衬底的下表面或所述第二电子衬底的上表面且将所述功能裸片功能上耦合到所述第一电路耦合特征及所述第二电路耦合特征中的至少一者。所述方法还可包含通过导电粘合剂的一个或一个以上部分将所述第二电子衬底的所述上表面附接到所述第一电子衬底的所述下表面，其中所述粘合剂部分中的每一者均电耦合所述第一屏蔽层与所述第二屏蔽层。 
附图说明
图1显示根据本发明的实施例的实例性多芯片堆叠式封装系统的分解图。 
图2A显示根据本发明的实施例的封装粘合剂的第一实例性接合图案。 
图2B显示根据本发明的实施例的封装粘合剂的第二实例性接合图案。 
图3显示根据本发明的另一实施例的实例性经封装集成电路。 
图4显示根据本发明的实施例的实例性多芯片封装。 
图5显示根据本发明的实施例的多芯片封装中封装粘合剂的实例性接合图案。 
图6显示根据本发明的又一实施例的另一实例性多芯片堆叠式封装系统的分解图。 
具体实施方式
本发明的实施例提供用于减小集成电路(IC)中电磁干扰的结构及方法。特定来说，发明者已发现，可修改现有堆叠式封装技术(例如，POP封装)以在不显著增加所述封装总体大小的情况下为一个或一个以上堆叠式IC提供法拉第笼。因此，可在不显著改变POP封装工艺流程的情况下维持POP封装的大小优势。 
用于提供法拉第笼的常规技术是基于提供用以包围EMI敏感或EMI产生IC的接地金属壳体的基本思想。通常，可通过使用冲压金属结构或通过将固体金属盖部分附接到放置于将要屏蔽的IC周围的固体金属壁部分来提供此类结构。在另一技术中，可在将要屏蔽的IC封装上方喷射导电材料。然而，尽管此类技术可用来有效地屏蔽平面布置中的多个IC，但此类技术对于屏蔽一个或一个以上个别堆叠式裸片或封装来说通常不切实际。因此，常规技术仍需要单独封装EMI产生IC及EMI敏感IC(统称为“EMI反应IC”)且更重要的是将其放置于电子装置中的不同平面位置中。因此，用于这些EMI反应IC的不同平面位置增加电子装置中用于这些IC(例如，电子装置的电路板上)所需的总体面积。 
发明者注意到，用于形成法拉第笼的基本要求是将要屏蔽的目标放置于包括接地导电材料的壳体内。所述壳体不需要是连续的，但任何开口应显著小于将要阻挡的EMI的波长。此外，壳体壁应具有足够厚度。即，所述厚度应足够大以使得EMI仅影响所述壳体的壳体壁厚度的外部部分(趋肤深度)。所需厚度可随着壳体材料的导电性变化而变化且随着EMI的类型变化而变化。一般来说，当壳体材料的导电性增加时，用于阻挡EMI所需材料的厚度减小且反之亦然。因此，电磁层需要不仅导电而且具有大于将要阻挡的EMI的趋肤深度的厚度的层。在其中EMI产生IC在壳体内的情况下，除从壳体内部测量趋肤深度以外应用相同的原则。 
考虑到这些要求，发明者已发现，针对至少某些类型的堆叠封装技术(例如，POP封装)，可通过修改封装来形成法拉第笼，这些修改通常不需要显著增加封装的大小。特定来说，发明者已发现，可通过电耦合常规堆叠式封装的上部电子衬底及下部电子衬底中的屏蔽层来形成法拉第笼。即，可在第一多层印刷电路板(PCB)或通常用于将封装安装于电子装置板上的其它电子衬底的层中的一者中形成下部屏蔽层。然而，在堆叠式封装的情况下，IC通常夹在第一电子衬底与第二电子衬底之间。在此类配置中，第二电子衬底通常提供用于电及/或机械附接一个或一个以上第二IC(堆叠式裸片)、其它IC封装(堆叠式封装)或离散电装置及组件的安装或耦合特征。第一电子衬底也可包含耦合特征。耦合特征(举例说明但并不限于)可包含电端子或引线及/ 或用于附接裸片、封装或离散电装置及组件的物理结构。无论耦合特征的类型如何，可在第二电子衬底的层中或其上形成第二屏蔽层。将此类层引入到电子衬底中通常仅需要添加薄金属层，所述薄金属层具有仅为所述薄金属层所添加到的电子衬底的厚度的一小部分的厚度。举例来说，在典型的POP封装中，通常用于提供对邻近RF产生IC的充分屏蔽所需的金属层厚度为至少10um的(主要为)铜合金，且通常在15um与20um之间。 
通常，POP封装使用非导电模制材料或囊封材料来囊封第一电子衬底及第二电子衬底以及夹在之间的IC。然而，本发明的实施例用耦合第一电子衬底与第二电子衬底中的屏蔽层的导电粘合剂材料取代安置于第一电子衬底与第二电子衬底的面对表面之间的此囊封材料的至少一部分。即，一种在其最终或固化状态下导电且粘合到第一电子衬底及第二电子衬底的至少导电部分的材料。举例来说，已知一些包括基于银及基于碳(石墨)的聚合物的粘合剂可提供良好的导电性，例如，基于银及基于石墨的环氧树脂。然而，在各种实施例中，可使用相对于第一电子衬底及第二电子衬底的面对表面具有粘合特性的任一类型有机或无机导电材料，所述导电材料包含包括金属或非金属的材料。举例来说，包括金属的焊料材料也可用作粘合剂。此外，导电粘合剂可以一图案围绕夹在中间的IC放置以电耦合上部屏蔽层与下部屏蔽层且电磁包围夹在中间的IC。因此，本发明的实施例为夹在中间的IC提供法拉第笼，所述法拉第笼具有使用第一电子衬底层及第二电子衬底层形成的法拉第笼的上部屏蔽层及下部屏蔽层以及由导电粘合剂形成的法拉第笼的侧壁。 
举例来说，在图1中所示的实例性堆叠式封装系统100(特定来说，POP封装系统)中图解说明此一配置。在图1中，系统100包含顶部封装102及底部封装104。底部封装104包含具有多个向下延伸以用于将封装系统100耦合到装置板(未显示)的引线108的下部衬底106。底部封装104还包含具有多个耦合到下部电子衬底106的引线108中的至少一些引线的端子112的上部电子衬底110。端子112还可经配置以接纳并耦合到从顶部封装102的下部电子衬底116延伸的多个引线114。 
在各种实施例中，顶部封装102包含电耦合到其下部电子衬底116的一个或一个以上IC 118。顶部封装102还可包含在IC 118与其下部电子衬底116之间的一个或一个以上粘合剂层120及封装模制件122。在组装时，将顶部封装102放置于底部封装104的顶部上。接着，可经由下部电子衬底106接近顶部封装102中的IC118。 
在常规POP布置中，底部封装104中的IC 124通常耦合到下部电子衬底106的引线108中的至少一些引线。在图1中所示的实例性布置中，IC 124以倒装芯片布置配置。即，IC 124附接到上部电子衬底110且焊料球126形成于IC 124上。接着，将上部电子衬底110及IC 124面朝下放置于下部电子衬底106上。可使用一个或一个以上接合线127将上部电子衬底110的端子耦合到下部电子衬底106的端子(未显示)。在倒装芯片布置中，下部电子衬底106可在其上表面上具有耦合到底部封装104的引线108中的至少一些引线的多个端子(未显示)。在其它布置中，IC 124可附接且线 接合到下部电子衬底106上的端子。可使用所述端子来接近下部电子衬底106的耦合到引线108的互连系统129。接着，可使用底部填充层128及模制层130来将IC 124与上部电子衬底110及下部电子衬底106附接在一起。 
在此常规POP布置中，顶部封装102与底部封装104之间的EMI屏蔽通常不切实际，这是因为将额外结构插入在所述封装之间可禁止性地增加堆叠式封装的大小。因此，设计者通常避免将EMI反应IC组合在此一布置中，如先前所描述。 
相反，本发明的各种实施例通过将电磁屏蔽层并入到现有的电子衬底中而允许EMI反应IC的紧密放置。举例来说，如图1中所示，可通过使用所形成的包括底部封装104的上部电子衬底110及下部电子衬底106的法拉第笼来给IC 124提供电磁屏蔽。可通过用导电层涂覆上部电衬底110的下表面来提供上部屏蔽层132。举例来说，如图1中所示，可在上部电衬底110的底部表面上施加金属层，例如，铜、铝、镍、钛或其任一合金。在一些情况下，可如先前所描述通过沉积导电粘合剂来形成导电层。下部屏蔽层134可由底部封装104的下部电子衬底106的层中的一者来提供。即，通过配置下部电子衬底106的导电层中的至少一者来提供电磁屏蔽。在各种实施例中，下部屏蔽层134可耦合到耦合到电子装置(未显示)的接地平面的引线108中的一者。如先前所描述，选择上部屏蔽层132及下部屏蔽层134的厚度以确保对EMI的阻挡。 
用于IC 124的法拉第笼的侧壁由接触上部电子衬底110及下部电子衬底106的面对表面以电及机械耦合上部屏蔽层132与下部屏蔽层134的导电粘合剂部分136来提供。在上部屏蔽层132的情况下，导电粘合剂136可直接接触上部屏蔽层132。在下部屏蔽层134的情况下，可提供多个通孔138来电耦合粘合剂136与下部屏蔽134。下部屏蔽层134电耦合到连接到装置的接地平面的引线108中的一者。粘合剂导体部分的厚度或珠粒(x)应如先前所描述足以阻挡EMI。 
尽管在各种实施例中珠粒大小(x)可变化，但在一个实施例中，已发现在100um到200um之间的基于银的环氧树脂珠粒大小(x)通常足以阻挡IC所产生的EMI，其包含在800MHz到2700MHz范围中的EMI，所述频率范围通常用于无线通信。然而，本发明并不限于此方面且可选择珠粒大小以阻挡在任何频率下所产生的EMI。举例来说，上部屏蔽层132及下部屏蔽层134、通孔138以及导电粘合剂还可适合于屏蔽IC使其免受在诊断放射线照相设备中及其周围所产生的辐射，所述诊断放射线照相设备包含(但并不限于)计算机化断层显像(CT)及其它x射线成像设备、磁共振成像设备、放射性核素成像或核闪烁扫描设备及正电子发射断层显像(PET)。 
在本发明的各种实施例中，导电粘合剂可以多种图案施加且仍可有效阻挡EMI。举例来说，图2A及图2B显示POP封装系统的基于倒装芯片的底部封装的下部电子衬底200的俯视图。如先前所描述，下部电子衬底200在其上表面上可具有用于耦合来自上部电子衬底的接合线的第一多个端子202。下部电子衬底200还可具有用于耦合基于倒装芯片的IC的第二多个端子204。区域206、208分别界定上部电子衬底及IC的占用面积。 
在放置上部电子衬底及IC之前，可施加导电粘合剂。所属领域的技术人员将认识到用于导电粘合剂的一些材料将具有非矩形横截面。因此，所需的最小厚度及/或珠粒大小将基于所得导电粘合剂横截面的最薄部分。本文中所使用的“珠粒大小”是指导电粘合剂的横截面尺寸，其包含高度及厚度(x)。另外，导电粘合剂可以各种类型的接合图案施加。举例来说，如图2A中所示，可在区域206与208之间提供连续接合图案210。在此类实施例中，如先前所描述，在足够珠粒大小的情况下，所述连续接合图案可有效阻挡所有EMI。在另一实例中，如在图2B中所示，可替代地提供非连续接合图案212。在此类实施例中，非连续接合图案212可包含一个或一个以上空隙214。如先前所描述，可选择空隙宽度(y)以使得所述尺寸小于将要阻挡的EMI的波长。在此类实施例中，非连续图案的每一部分均可接触电子衬底中的一个或一个以上通孔。所述部分可具有任一长度。举例来说，在一些实施例中，可使用一组焊料或环氧树脂球形成非连续图案212。或者，也可使用一段焊料或环氧树脂。尽管实例性接合图案显示为均匀地围绕IC区域206，但接合图案可经形成以遵循任何路径，只要仍提供上部屏蔽层与下部屏蔽层的耦合且粘合剂继续电磁包围IC区域206。 
再次参照图1，可选择通孔的尺寸以使得通孔138之间的间隔也适于供阻挡EMI之用。即，通孔138的数目、间隔及宽度应基于通孔138的组成足以防止任何显著量的EMI到达IC 124。然而，导电粘合剂136与屏蔽层中的每一者之间的间隔通常小于100um。通常，此间隔足以阻挡来自横向放置源的EMI且在堆叠式封装的情况下其不是EMI的主要路径。 
如先前所描述，下部电子衬底104可含有具有用于接触引线108的布线层129的多个层。尽管下部屏蔽层134在一些实施例中可形成为实体板，但在其它实施例中，下部屏蔽层134可被图案化。在此类实施例中，图案化允许下部电衬底106中的布线层129具有到引线108的较短长度。然而，为保持法拉第笼的完整性，下部屏蔽层134中的任何开口可具有小于将要阻挡的EMI波长的尺寸。 
在本发明的其它实施例中，法拉第笼的上部屏蔽层不必如图1中所示形成于上部电子衬底的表面上。而是，如图3中所示，上部屏蔽层302可替代地形成于下部封装300的上部电子衬底304的内层中。在此类实施例中，可提供通孔306以将导电粘合剂308电耦合到上部屏蔽层302。也可如先前针对图1中的下部屏蔽层134所描述的那样图案化上部屏蔽层302。也可如先前针对图1中的通孔138所描述的那样配置通孔306的数目、间隔及宽度。 
在本发明的一些实施例中，可屏蔽多于一个IC。举例来说，如图4中所示，底部封装400可包含如先前针对图1所描述的那样使用上部屏蔽层404及下部屏蔽层406、导电粘合剂408以及通孔410屏蔽的两个或两个以上IC 402、403。在一些实施例中，可通过在IC 402与403之间提供额外导电粘合剂部分412来在其之间提供额外屏蔽。 
如上文针对图2A及图2B所描述，用于图4中的配置的导电粘合剂可以各种图案形成且仍可有效阻挡EMI。举例来说，图5显示用于封装两个裸片的POP封装系统 的基于倒装芯片的底部封装的下部电子衬底500的俯视图。下部电子衬底500可在其上部表面上具有用于耦合来自上部电子衬底的接合线的第一多个端子502。下部电子衬底500还可具有用于耦合基于倒装芯片的IC的第二多个端子504。区域506、508及509分别界定上部电子衬底、第一IC及第二IC的占用面积。 
如先前所描述，所述接合图案可变化。举例来说，可围绕IC区域508及509提供连续接合图案。在此类实施例中，如先前所描述，在足够珠粒大小(x)的情况下，所述连续接合图案可有效阻挡所有EMI。在另一实例中，如图5中所示，可如先前在图3B中所描述的那样提供非连续接合图案510。在此类实施例中，非连续接合图案510可包含一个或一个以上空隙514。如先前所描述，可选择空隙大小(y)以使得所述尺寸小于将要阻挡的EMI的波长。 
接合图案510还可包含额外部分512。与接合图案510一样，部分512的图案也可变化。举例来说，在一些情况下，如果提供非连续接合图案，那么空隙大小(y)可足以阻挡源于IC外部位置的EMI，但不能阻挡所述IC之间的EMI。在此类实施例中，可调整部分512中的任何空隙以在所述IC之间提供额外EMI屏蔽。举例来说，如图5中所示，如果IC彼此间比对周围环境更加敏感，那么可给部分512提供连续图案。 
在图1到图5中，法拉第笼是在POP系统的底部封装中实施。然而，本发明并不限于此方面且可在其中IC夹在两个电子衬底之间的任一封装中实施。举例来说，如图6中所图解说明，法拉第笼可在POP系统600的顶部封装602中实施。在此类实施例中，底部封装604任选地还可包含如图1到图5中所描述的法拉第笼。然而，如图6中所示，法拉第笼还可在顶部封装602中实施。在此类实施例中，顶部封装602可如先前针对图1所描述的那样包含用于屏蔽IC 614使其免受EMI所需的上部屏蔽层604及下部屏蔽层608、由导电粘合剂610形成的壁以及通孔612。 
此外，图6中的顶部封装602还图解说明性地显示本发明可如何在堆叠式IC系统(非POP)中实施。在此类实施例中，第二IC 616可安装于第二电子衬底的上表面上。如图6中所示，第二IC 616以倒装芯片配置安装，接触第二电子衬底的上表面上的多个端子(未显示)。所述端子可如先前所描述经由接合线620连接到下部电子衬底622的上表面上的端子且向外连接到引线624。接着，模制层626及底部填充层628可用于囊封IC 616、614。 
已主要在倒装芯片应用方面描述了本发明的各种实施例；然而本发明并不限于此方面。在一些实施例中，接合线可用于使IC表面上的端子直接接触到所使用的下部电子衬底或上部电子衬底的端子。此外，如图1中所示，可使用线接合与倒装芯片方法的组合。 
本发明所涉及领域的技术人员将了解，在所主张发明的范围内，许多其它实施例及变化形式是可能的。 

Claims (15)

1.一种经封装集成电路，其包括：
第一电子衬底，所述第一电子衬底包括第一多个层及在所述第一电子衬底的上表面处的至少第一电路耦合特征，所述第一多个层包括至少第一电磁干扰(EMI)屏蔽层；
第二电子衬底，所述第二电子衬底具有通过导电粘合剂材料的一个或一个以上部分附接到所述第一电子衬底的下表面的上表面，所述第二电子衬底包括第二多个层及在所述第二电子衬底的下表面处的至少第二电路耦合特征，所述第一多个层包括至少第二EMI屏蔽层；及
至少一个功能裸片，其安置于所述第一电子衬底与所述第二电子衬底之间且功能上耦合到所述第一电路耦合特征及所述第二电路耦合特征中的至少一者，
其中所述粘合剂材料部分中的每一者均电耦合所述第一屏蔽层与所述第二屏蔽层。
2.根据权利要求1所述的集成电路，其中所述第二电子衬底进一步包括在所述第二电子衬底的所述上表面上电耦合到所述第二屏蔽层的至少一个端子。
3.根据权利要求2所述的集成电路，其中所述第一电子衬底进一步包括在所述第一电子衬底的所述下表面上电耦合到所述第一屏蔽层的至少一个端子。
4.根据权利要求2所述的集成电路，其中在所述第一电子衬底的下表面处的所述第一多个层中的一者包括所述第一屏蔽层。
5.根据权利要求1所述的集成电路，其中所述粘合剂是以接合图案形成，所述接合图案界定所述第一电子衬底与所述第二电子衬底之间无所述粘合剂的至少一个区域。
6.根据权利要求1所述的集成电路，其中至少两个功能裸片安置于所述第一电子衬底与所述第二电子衬底之间，其中所述粘合剂是以接合图案形成，且其中成所述接合图案的所述粘合剂电磁包围所述功能裸片中的至少一者。
7.一种用于封装集成电路的方法，其包括：
提供第一电子衬底，所述第一电子衬底包括第一多个层及在所述第一电子衬底的上表面处的至少第一电路耦合特征，所述第一多个层包括至少第一电磁干扰(EMI)屏蔽层；
提供第二电子衬底，所述第二电子衬底包括第二多个层及在所述第二电子衬底的下表面处的至少第二电路耦合特征，所述第二多个层包括至少第二EMI屏蔽层；
将至少一个功能裸片附接到所述第一电子衬底的下表面或所述第二电子衬底的上表面且将所述功能裸片功能上耦合到所述第一电路耦合特征及所述第二电路耦合特征中的至少一者；及
通过导电粘合剂的一个或一个以上部分将所述第二电子衬底的所述上表面附接到所述第一电子衬底的所述下表面，其中所述粘合剂部分中的每一者均电耦合所述第一屏蔽层与所述第二屏蔽层。
8.根据权利要求7所述的方法，其中所述附接步骤进一步包括与所述第二电子衬底的所述上表面上电耦合到所述第二屏蔽层的至少一个端子接触地放置所述粘合剂。
9.根据权利要求8所述的方法，其中所述附接步骤进一步包括与所述第一电子衬底的所述下表面上电耦合到所述第一屏蔽层的至少一个端子接触地放置所述粘合剂。
10.根据权利要求8所述的方法，其中所述第一电子衬底的下表面处的所述第一多个层中的一者包括所述第一屏蔽层。
11.根据权利要求7所述的方法，其中所述附接步骤进一步包括以接合图案将所述粘合剂放置于所述第一电子衬底及所述第二电子衬底中的一者上，所述接合图案界定所述第一电子衬底与所述第二电子衬底之间无所述粘合剂的至少一个区域。
12.根据权利要求7所述的方法，其中将至少两个功能裸片安置于所述第一电子衬底与所述第二电子衬底之间，其中所述粘合剂是以接合图案形成，且其中成所述接合图案的所述粘合剂电磁包围所述功能裸片中的至少一者。
13.一种集成电路封装系统，其包括：
至少一个顶部封装，其用于封装至少一个顶部功能裸片，所述顶部封装包括耦合到所述顶部功能裸片并从所述顶部封装的下表面延伸的多个顶部封装引线；及
底部封装，其用于封装至少一个底部功能裸片，所述底部封装包括：
第一电子衬底，所述第一电子衬底包括第一多个层及在所述第一电子衬底的上表面处用于接纳所述顶部引线的多个电端子，所述第一多个层包括至少第一电磁干扰(EMI)屏蔽层，及
第二电子衬底，所述第二电子衬底具有通过包括导电聚合物的粘合剂的一个或一个以上部分附接到所述第一电子衬底的下表面的上表面，所述第二电子衬底包括第二多个层及在所述第二电子衬底的下表面处的多个底部封装引线，所述第二多个层包括至少第二EMI屏蔽层，
其中所述底部裸片安置于所述第一电子衬底与所述第二电子衬底之间，其中所述粘合剂部分电耦合所述第一屏蔽层与所述第二屏蔽层，且其中所述顶部裸片及所述底部裸片均功能上耦合到所述底部引线。
14.根据权利要求13所述的系统，其中所述第二电子衬底进一步包括所述第二电子衬底的所述上表面上电耦合到所述第二屏蔽层的至少一个端子。
15.根据权利要求14所述的集成电路，其中所述第一电子衬底进一步包括所述第一电子衬底的所述下表面上电耦合到所述第一屏蔽层的至少一个端子。
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