CN101789489A - 相变存储器单元及形成的方法 - Google Patents

相变存储器单元及形成的方法 Download PDF

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CN101789489A
CN101789489A CN200910261372A CN200910261372A CN101789489A CN 101789489 A CN101789489 A CN 101789489A CN 200910261372 A CN200910261372 A CN 200910261372A CN 200910261372 A CN200910261372 A CN 200910261372A CN 101789489 A CN101789489 A CN 101789489A
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electrode
memory component
tellurium
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克里斯蒂·A·坎贝尔
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Micron Technology Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Abstract

本发明提供一种相变存储器元件及形成所述元件的方法。所述存储器元件包括第一电极(12)及所述第一电极上方的包含相变材料层(18)的硫族化物。金属硫族化物层(20)位于所述相变材料层上方。所述金属硫族化物层为碲化锡。第二电极(24)位于所述金属硫族化物层上方。所述存储器元件经配置以具有降低的电流要求。

Description

相变存储器单元及形成的方法
本申请为发明名称为“相变存储器单元及形成的方法”的原中国发明专利申请的分案申请。原申请的申请号为200680034986.8(国际申请号为WO2007/016169A1)；原申请的申请日为2006年7月26日；以及原发明专利申请案的优先权日为2005年8月2日。
技术领域
本发明涉及半导体装置，且特定来说涉及相变存储器装置及形成所述装置的方法。
背景技术
非易失性存储器因其在无供电的情况下能够维持数据而成为集成电路的重要元件。已研究相变材料在非易失性存储器单元中的使用。相变存储器单元包括相变材料，例如，能够在非晶相与结晶相之间稳定转换的硫族化物合金。每一相位呈现特定电阻状态且所述电阻状态区分所述存储器单元的逻辑值。具体来说，非晶态呈现相对高的电阻，而结晶态呈现相对低的电阻。
典型的相变单元在第一与第二电极之间具有相变材料层。作为一个实例，所述相变材料为硫族化物合金，例如Ge2Sb2Te5或SbTeAg。例如，参见Lankhorst等人的Low-cost and nanoscale non-volatile memory concept for future silicon chips，NATUREMATERIALS，第4册第347-352页(2005年4月)。
根据经由电极施加的电流量将所述相变材料的一部分设置成特定的电阻状态。为获得非晶态，通过所述相变单元施加相对高的写入电流脉冲(重设脉冲)以使所述材料的一部分熔化一较短的时间段。移除所述电流且所述单元快速冷却到玻璃化温度以下，此导致所述材料的所述部分具有非晶相。为获得结晶态，将较低电流写入脉冲(设置脉冲)施加到所述相变单元一较长的时间段以将所述材料加热到其熔化点温度以下。此导致所述材料的非晶部分再结晶为结晶相，一旦移除所述电流，所述结晶相即得以维持且单元10快速冷却。
非易失性存储器的受欢迎的特性为低功率消耗。然而，相变存储器单元经常要求大的操作电流。因此，提供具有降低的电流要求的相变存储器单元将是所期望的。
发明内容
本发明的实施例提供一种相变存储器元件及用于形成所述元件的方法。所述存储器元件包括第一电极及位于所述第一电极上方的包含相变材料层的硫族化物。金属硫族化物层位于所述相变材料层上方。所述金属硫族化物层包含锡-碲-碲。第二电极位于所述金属硫族化物层上方。所述存储器元件经配置以具有降低的功率消耗。
附图说明
参照附图从下文提供的对实例性实施例的详细说明中将更加明了本发明的前述及其它优点及特征，附图中：
图1描绘根据本发明的实施例的相变存储器元件；
图2A-2C描绘图1的存储器元件在不同处理阶段时的形成；及
图3是包括根据本发明的实例性实施例的存储器元件的系统的方块图。
具体实施方式
在以下详细说明中，参考本发明的各种具体实施例。以足够的细节说明所述实施例以使所属领域的技术人员能够实践本发明。应了解，可采用其它实施例，且可在不背离本发明的精神或范围的前提下做出各种结构、逻辑及电学改变。
以下说明中使用的术语“衬底”可包括任何支撑结构，包括但不限于具有暴露的衬底表面的半导体衬底。半导体衬底应被理解为包括硅、绝缘体上硅(SOI)、蓝宝石上硅(SOS)、经掺杂及未经掺杂的半导体、由基础半导体基底支撑的硅外延层及其它半导体结构。当在以下说明中提及半导体衬底或晶圆片时，可能已利用先前的处理步骤在基础半导体或基底中或上方形成了区域或结。所述衬底无需是基于半导体的，但可以是任何适合于支撑集成电路的支撑结构，包括但不限于金属、合金、玻璃、聚合物、陶瓷及所属技术中已知的任何其它支撑材料。
现在参照图式解释本发明，所述图式图解说明实例性实施例，且贯穿所述图式，相同的参考编号指示相同的特征。图1描绘根据本发明构造的存储器元件100的实例性实施例。图1中所示的装置100由衬底10支撑。位于所述衬底上方的是第一绝缘层11。第一电极21上覆在第一绝缘层11及衬底10上。第一电极12可以是任何适合的导电材料，且在所图解说明的实施例中为钨(W)。
第二绝缘层14位于第一电极12上方。通孔42位于绝缘层14内以暴露第一电极12的一部分。在所图解说明的实施例中，通孔42延伸穿过第一电极12的一部分。第二绝缘层14可以是氮化物，例如氮化硅(Si3N4)；低介电常数材料；绝缘玻璃；绝缘聚合物；以及其它材料。
如图1中所示，相变材料层18(具体来说，硫族化物材料层18)被沉积在通孔42内及第一电极12上方。在所图解说明的实施例中，层18为碲化锗层。层18的其它实例性硫族化物组合物包括浓度低于约70％的Te。锗浓度优选地高于约10％。层18可包括额外元素，例如锑。所给出的百分数为原子百分数，其总计为组成元素的原子的100％。在所图解说明的实例中，碲化锗层18为约
Figure G2009102613729D00031
厚且与下伏的第一电极12电接触，但在通孔42的邻近下伏的第一电极12的边缘42a处不到约
Figure G2009102613729D00032
厚。位于碲化锗层18上方且位于通孔42内的是碲化锡层20。在所图解说明的实施例中，层20为约50％的锡及约50％的碲且约
Figure G2009102613729D00033
厚。
虽然显示层20位于硫族化物材料层18上方，但应了解可改变所述层的方位。举例来说，硫族化物材料层18可位于层20上方。
位于碲化锡层20上方且位于通孔42内的是第二电极24。第二电极24可以是任何适合的导电材料，且在所图解说明的实施例中为钨。
对于操作，使用脉冲发生器35来施加约1.4V的重设脉冲，且使用小于或约280μA的电流。所述重设脉冲使碲化锗层18的至少一部分熔化，使层18处于高电阻、非晶态。使用约1.17V的设置脉冲及小于或约200μA的电流。所述设置脉冲使碲层18的至少一部分结晶，使层18处于低电阻状态。
图2A-2C为晶圆片的剖面视图，其描绘根据本发明的实例性实施例的存储器元件100的形成。对本文中所说明的任何动作不要求特定的次序，除了那些逻辑上需要前面动作的结果的动作外。相应的，虽然将以下动作说明为按具体次序实施，但所述次序仅为实例性且如果需要可改变所述次序。虽然显示单个存储器元件100的形成，但应了解，存储器元件100可以是可同时形成的存储器元件阵列中的一个存储器元件。
如图2A所示，首先提供衬底10。如上文所示，衬底10可以是基于半导体或如所属技术中已知用作支撑结构的另一种材料。在衬底10上方形成第一绝缘层11且在绝缘层11上方形成第一电极12。在第一电极12上方形成第二绝缘层14。所述第一绝缘层可以是(例如)二氧化硅。第二绝缘层14可以是氮化硅、低介电常数材料或所属技术中已知的其它适合绝缘体，且可通过所属技术中已知的任何方法形成。
如图2B中所图解说明，(例如)通过光刻及蚀刻技术在第二绝缘层14内形成通孔42以暴露第一电极12的一部分。视情况，通孔42可部分地延伸穿过第一电极12。
如图2C中所示，在第一电极12及第二绝缘层14上方且在通孔42内形成碲化锗层18。可通过任何适合的方法完成碲化锗层18的形成。层18形成为具有约
Figure G2009102613729D00034
的厚度。
在碲化锗层18上方且在通孔42内形成碲化锡层20。可通过任何适合的方法形成层20，所述方法例如为物理气相沉积、化学气相沉积、共蒸发、溅镀及其它技术。层18形成为具有约
Figure G2009102613729D00035
的厚度。
在碲化锡层20上方及通孔42内沉积导电材料以形成第二电极24。类似于第一电极12，用于第二电极24的导电材料可以是适合于导电电极的任何材料，例如钨。在所图解说明的实施例中，将层18、20、24形成为覆盖层。
如所属技术中已知，可实施额外的处理步骤，举例来说，形成到达存储器元件100是其一部分的集成电路(例如，逻辑电路、读出放大器等)的其它电路的连接。
图3图解说明包括存储器电路348(例如，存储器装置)的处理器系统300，存储器电路348采用包括根据本发明构造的至少一个存储器元件100的存储器阵列301。处理器系统300可以是(例如)计算机系统，其通常包含中央处理单元(CPU)344，例如微处理器、数字信号处理器或其它可编程数字逻辑装置，中央处理单元(CPU)344经由总线352与输入/输出(I/O)装置346通信。存储器电路348通常通过存储器控制器经由总线352与CPU 344通信。
在计算机系统的情况下，处理器系统300可包括外围装置，例如软盘驱动器354及光盘(CD)ROM驱动器356，所述外围装置也经由总线352与CPU 344通信。存储器电路348优选地构造为集成电路，其包括具有根据本发明的至少一个存储器元件100的存储器阵列301。如果需要，可将存储器电路348与所述处理器(举例来说，CPU 344)组合在单个集成电路中。
应仅将以上说明及图式视为对实现本发明的特征及优点的实例性实施例的说明。可在不背离本发明的精神及范围的情况下对具体处理条件及结构做出修改及替换。相应地，不应将本发明视为受限于前述说明及图式，本发明仅受随附权利要求书的范围的限定。

Claims (19)

1.一种存储器元件，其包含：
第一电极；
碲化锗材料，其与所述第一电极接触；
碲化锡材料，其与所述碲化锗材料接触；和
第二电极，其与所述碲化锡材料接触。
2.如权利要求1所述的存储器元件，其中至少一部分所述碲化锗材料形成为具有约
Figure F2009102613729C00011
的厚度。
3.如权利要求1所述的存储器元件，其中所述碲化锡材料形成为具有约
Figure F2009102613729C00012
的厚度。
4.如权利要求1所述的存储器元件，其中所述第一电极和所述第二电极中一者或两者形成为包含钨。
5.一种存储器元件，包含：
第一和第二电极；
位于所述第一和第二电极之间的绝缘材料；
位于所述第一和第二电极之间的包含硫族化物的相变材料；及
位于所述相变材料和所述第二电极之间的碲化锡材料，其中所述相变材料和所述碲化锡材料形成在通孔内，所述通孔位于通过所述第一电极至少部分地延伸的所述绝缘材料内。
6.如权利要求5所述的存储器元件，其中所述相变材料在所述通孔的邻近所述第一电极的边缘处具有小于或等于约
Figure F2009102613729C00013
的厚度。
7.如权利要求5所述的存储器元件，其中所述存储器元件经配置以使用小于或约200μA的电流设置成第一电阻状态。
8.如权利要求5所述的存储器元件，其中所述存储器元件经配置以使用小于或约280μA的电流重设成第二电阻状态。
9.如权利要求5所述存储器元件，其中所述存储器元件经配置以使用约1.17V的电压重设成所述第一电阻状态。
10.如权利要求5所述的存储器元件，其中所述存储器元件经配置以使用约1.4V的电压设置成所述第二电阻状态。
11.如权利要求5所述的存储器元件，其中所述相变材料包含碲化锗。
12.如权利要求5所述的存储器元件，其中所述相变材料包含小于70％的碲。
13.如权利要求5所述的存储器元件，其中所述碲化锡材料包含约50％的锡和约50％的碲。
14.如权利要求5所述的存储器元件，其中所述第一电极和所述第二电极中的一者或两者包含钨。
15.一种形成存储器元件的方法，其包括：
形成第一电极；
所述第一电极上方及通孔内形成包含硫族化物的相变材料；
在所述相变材料上方及所述通孔内形成碲化锡材料；及
在所述碲化锡材料上方形成第二电极。
16.如权利要求15所述的方法，其中至少一部分所述相变材料形成为具有约
Figure F2009102613729C00021
的厚度。
17.如权利要求15所述的方法，其中所述相变材料形成为包含碲化锗。
18.如权利要求15所述的方法，其中所述金属硫族化物材料形成为具有约
Figure F2009102613729C00022
的厚度。
19.如权利要求15所述的方法，其中所述第一电极和所述第二电极中的一者或两者形成为包含钨。
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