CN101730928B - 使用保形绝缘体层形成互补金属元件 - Google Patents
使用保形绝缘体层形成互补金属元件 Download PDFInfo
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
Abstract
本发明提供了一种用以形成密集间隔的金属线的方法。第一组金属线通过蚀刻第一金属层而形成。薄介电层保形地沉积在第一金属线上。第二金属沉积在薄介电层上,填充第一金属线之间的间隙。第二金属层平坦化以形成插入在第一金属线之间的第二金属线,在基本上平坦的表面上共同暴露薄介电层和第二金属层。在一些实施例中,继续平坦化以去除第一金属线的薄介电质覆盖顶部,在基本上平坦的表面上共同暴露由薄介电层分隔开的第一金属线和第二金属线。
Description
技术领域
本发明涉及用于使用消减(subtractive)方法和金属镶嵌(damascene)方法二者在紧密间距处形成金属元件(feature)的方法。互补金属图案可通过蚀刻金属层、在经蚀刻的表面上形成保形(conformal)介电层、以及随后沉积另一金属层而形成。
背景技术
在收缩的所占尺寸(footprint)内的半导体器件上增大元件密度(featuredensity)的方法持续地演化,以满足对于更小、更强大的电子器件的需求。然而,在一些例子中,实际考虑可能限制那些方法可演化的程度。例如,图1是在45nm工艺中在底层上形成的金属图案的现有技术例子的示例性截面图。如图所示,在图1中,金属102可通过公知的方法在底层106上形成为图案。例如,金属102可使用标准的光刻(photolithographic)技术来沉积并蚀刻。为了清楚起见,仅精细金属图案的例子的一部分以截面图示出。金属图案可形成任意数量的元件或连接线。可以设置绝缘体104以形成金属线108和110之间的势垒。金属线108和110可具有大约45nm的宽度112,并且绝缘体104可具有大约45nm的宽度114。同样地,元件的间距116大约90nm。
在一些传统例子中,为了容纳更密集布置的元件,通常需要减小间距。对于如上所述的传统制造方法,这将需要发展到更加昂贵的制造手段。例如,可能需要更加昂贵的光刻工具。因而,所期望的是开发增大元件密度而不增加制造成本的方法。
另外,由于线宽减小,导电线的金属量也减小,因而导致导电线的阻抗增大。因而,可期望的是开发可应对增大的元件密度而不相应地减小导体线宽的方法。例如,为了符合相同区域中更宽的导体线,所期望的是最小化它们之间的间隙宽度。
发明内容
本发明由所附的权利要求限定,并且本部分的任何内容都不作为对那些权利要求的限制。总体上,本发明针对一种形成非常密集的金属线的方法。
本发明的第一方面提供一种用于在底层上沉积至少两个金属层的方法,该方法包括:在底层上沉积第一金属层;掩蔽第一金属层使得第一金属层包括第一被掩蔽的部分和第一未掩蔽的部分;以及蚀刻第一金属层使得第一未掩蔽的部分去除到底层;在第一金属层上和底层上沉积第一中间层;在第一中间层上沉积第二金属层;以及平坦化第二金属层以在第一基本上平坦的表面处共同暴露第一中间层和第二金属层。
本发明的另一方面提供一种在底层上形成第一金属元件和第二金属元件以用于半导体器件的方法,该方法包括:在底层上沉积第一金属层;掩蔽第一金属层使得第一金属层包括第一被掩蔽的部分和第一未掩蔽的部分,其中第一被掩蔽的部分和第一未掩蔽的部分与互补的图案相对应;蚀刻第一金属层使得第一未掩蔽的部分去除到底层,离开第一金属元件;在第一金属层上和底层上沉积第一保形介电层;在第一保形介电层上沉积第二金属层;以及平坦化第二金属层以形成第二金属元件,并且在基本上平坦的表面处共同暴露第二金属元件和第一保形介电质。
在此描述的本发明的每个方面和实施例可以单独地或彼此结合地使用。
现在将参考附图描述优选的方面和实施例。
附图说明
图1是具有在45nm工艺中形成的金属图案的底层的现有技术例子的截面图。
图2是根据本发明实施例的用于在底层上形成金属线的方法的示例性流程图。
图3至6是示出使用根据本发明实施例的方法在底层上形成金属线的阶段的截面图。
图7是根据本发明实施例在底层上的金属线的截面图。
图8是根据本发明实施例在底层上的金属线的截面图。
图9是用于单片(monolithic)三维存储器阵列的根据本发明实施例形成的金属线的截面图。
图10A至C是根据本发明实施例在底层上的金属线的平面图。
图11是根据本发明实施例在第一金属线和第二金属线之间的连接的平面图。
具体实施方式
现在将参考如附图所示的一些实施例对本发明进行详细描述。在下面的描述中,为了提供本发明的全面理解,阐明了大量的具体细节。然而,对于本领域技术人员显而易见的是,本发明可以没有一些或所有这些具体细节而实施。在其它实例中,为了避免不必要地使本发明模糊,没有详细描述公知的工艺步骤和/或结构。
图2是根据本发明实施例的用于在底层上形成金属线的方法的示例性流程图。图2将连同图3至8进行讨论,图3至8是使用根据本发明实施例的方法在底层上形成金属线的阶段的示例性表示。在第一步骤202,第一金属沉积在底层上。参考图3,在一个实施例中,第一金属层302沉积在底层304上。如可以理解的,任意数量的合适的金属合成物(composition)可使用任意数量的不背离本发明的公知方法而沉积在任意数量的底层合成物上。底层304典型地是诸如二氧化硅的介电材料。金属304可以是钨、铝或一些其它合适的导电材料。在一些实施例中,第一金属层302的厚度不小于大约30nm。在其它实施例中,第一金属层302的厚度不大于大约1000nm。
在下一步骤204,第一金属层使用任意数量的公知方法进行掩蔽。掩蔽典型地在层上,例如在诸如光刻胶(photoresist)的光敏材料中,提供了精细的图案,使得后续的蚀刻将去除被掩蔽的层的未掩蔽的部分。在下一步骤206,蚀刻第一金属层302。如图4所示,蚀刻后的作为结果的图案可包括一系列的金属元件(feature);例如,图案可包括诸如沟槽404的沟槽和诸如线408和410的线。在一些实施例中,蚀刻可进行到底层304。在其它实施例中,可以理解,可越过底层进行蚀刻。蚀刻可以以现有技术中公知的任何方式完成而没有背离本发明。
在下一步骤208,介电质可保形地沉积到剩下的金属层的顶部和侧壁、及暴露的底层上。因而,如图5所示,根据本发明的实施例,介电层504可保形地沉积在线408和410的顶部和侧壁及底层304的暴露部分上并与之接触。介电层504可以以现有技术中任何公知的方式进行沉积。介电层504的厚度选择成使得在已经沉积介电层504之后,金属线408和410之间的沟槽404仍具有足够的宽度,以允许其后的金属线形成。在一些实施例中,介电层504沉积之后,沟槽404的宽度可以与第一金属线408和410的宽度相同或接近相同。明显地,这要求在介电层504的沉积之前,沟槽404的宽度必须宽于金属线408和410的宽度。在一些实施例中,可选择介电质以提供扩散阻挡层(diffusion barrier)和附着层(adhesion layer)。在一些实施例中,对于介电层可采用Si3N4或SiO2。
在下一步骤210,第二金属沉积在介电层上。如图6所示,第二金属层604沉积在介电层504上,且与介电层504接触。在一些实施例中,第二金属层是基本上类似于第一金属层的合成物。在其它实施例中,第二金属层不同于第一金属层。另外,如图6所示,根据本发明的实施例,第二金属层604现在形成与原始的被掩蔽的第一金属层相互补的图案。即,第二金属层填充第一金属层的经蚀刻的部分,该部分与第一金属层的原始未掩蔽的部分相对应。可以理解,在一些例子中,用于沉积而选择的金属合成物需要附加步骤或方法以应对化学和物理特性。在一些实施例中,对于第二金属层可单独地或相结合地采用铜或铝而不背离本发明。在其它实施例中,对于第二金属层可采用钨。可以理解,把钨用于第二金属层沉积,可能要求在介电层上沉积之前有保形附着层。因而,在一些实施例中,在沉积第二金属层604之前,诸如Ti、TiW或TiN的薄附着层(单独地或相结合地)可保形地沉积在介电层504上,而不背离本发明。
另外,可以理解,尽管示出的金属线宽度基本相等,但是线的宽度可改变以补偿第一金属层和第二金属层之间的体量差,而不背离本发明。例如,如上所示,在采用钨作为介电层504上方的第二金属层604的情况下,可以要求附着层。然而,TiN附着层的使用可导致钨的第二金属层相对于钨的第一金属层体量改变。因而,为了金属线具有相类似的电气特征,可调整金属线(也就是第二金属层)的宽度,以合适地补偿体量差,而没有背离本发明。
另外,可以理解,关于根据在此描述的实施例的第一或第二金属层的金属的选择,可以针对与金属层相连的特定元件或器件最优化。例如,一些金属-半导体连接可造成非意图的肖特基(Schottky)器件。因而,在仅单个金属可用于导电线的情况下,一些器件构造也许是不可能的。然而,因为本方法在形成导电线过程中提供了不同于第二金属的第一金属的选择,因而可实现其它情况下不可能的器件组合。因而,在一些实施例中,第一金属层和第二金属层基本上类似,然而在其它实施例中,第一金属层和第二金属层基本上不类似。
在下一步骤212,本方法确定是否期望共面构造。共面构造是其中两金属层可以从同一侧接触的构造,例如从上侧。替代地,非共面构造是其中任一金属层可以从上面和从下面独立地接触的构造。因而,如果本方法在步骤212确定需要共面构造,那么该方法进行到步骤214,以平坦化结构的表面,从而在基本上平坦的表面处共同曝露两金属。可以以现有技术中公知的任意方式完成平坦化而不背离本发明,例如:化学机械抛光(CMP)和采用湿或干蚀刻方法的毯式回蚀(blanket etchback)。如图7所示,根据本发明的实施例,器件700包括已经平坦化以曝露金属线408、708和410的表面720。另外,如图所示,介电层504的在平坦化期间没有去除的部分也在基本上平坦的表面上共同暴露,并用于这些金属线彼此之间绝缘。在结构700的同一侧上的位置730、740和750处,可产生与金属线408、708和410的电气接触。在一些实施例中,第二金属层的厚度在平坦化之后不小于大约30nm。在其它实施例中,第二金属层的厚度在平坦化之后不大于大约1000nm。
如果本方法在步骤212确定不需要共面构造,那么方法进行到步骤216,以平坦化器件的表面,平坦化步骤在介电质504上停止,并且不去除之以暴露第一金属线410和408。可以以现有技术中公知的任意方式完成平坦化而不背离本发明,例如:CMP和采用湿或干蚀刻方法的毯式回蚀。如图8所示,根据本发明的实施例,器件800包括表面820,该表面820已经被平坦化以在基本上平坦的表面上共同暴露介电质504和线708。在一些实施例中,第二金属层的厚度在平坦化之后不小于大约30nm。在其它实施例中,第二金属层的厚度在平坦化之后不大于大约1000nm。例如,如图所示,在该实施例中,第一金属线408和410通过介电质504而保持屏蔽。在结构800上方的位置830处可产生与金属线708的电气接触,而在结构800下方的位置840和850处可以产生与金属线408和410的电气接触。
在此引入作为参考的Herner等的美国专利No.6952030“High-densitythree-dimensional memory cell(高密度三维存储单元)”描述了一种单片三维存储器阵列,该单片三维存储器阵列包括在衬底上方堆叠而形成为单片的多个存储器级(level)。每个存储器级包括设置在导体之间的垂直定向的二极管。该二极管优选是p-i-n二极管,具有在一端的重掺杂的p型区域、在另一端的重掺杂的n型区域、以及中间的本征区域。在这样的阵列中可以采用根据本发明的方面形成的导体,该导体从上方和下方可接触,如图8所示。转向图9,例如,第一存储器级中垂直定向的二极管220可从下方产生与第一金属线408和410的电气接触,然而第二存储器级中的二极管330可从上方产生与诸如金属线708的第二金属线的电气接触。
在图7或图8的实施例中,在平坦化步骤之后,由第一金属形成的第一多个基本上平行的金属线之中散布由第二金属形成的第二多个基本上平行的金属线。
如上所示,在消减地形成的传统金属线图案中,为了容纳更密集布置的元件,通常需要减小间距。随着间距减小,导电线的金属体量也减小,因而导致导电线的阻抗增大。通常地,由于非常窄的线难以干净地蚀刻,因而相邻线之间的间隙不能太窄。参考图1的现有技术例子,介电质104的宽度可与金属线108和110的宽度相同,并且间距可以是线108和110的宽度的两倍。
参考图7和8,相邻金属线408和708之间的介电层504的宽度很大程度(substantially)小于金属线408和708的宽度,因而间距很大程度小于线408和708的宽度的两倍,允许密度增大。因而,在一个实施例中,对于大约250nm的间距,金属线的宽度在大约170-230nm的范围内,并且介电质的宽度在大约20-80nm的范围内。在另一实施例中,对于大约180nm的间距,金属线的宽度在大约140-166nm的范围内,并且介电质的宽度在大约14-40nm的范围内。在另一实施例中,对于大约90nm的间距,金属线的宽度在大约70-83nm的范围内,并且介电质的宽度在大约7-20nm的范围内。在另一实施例中,对于大约72nm的间距,金属线的宽度在大约56-67nm的范围内,并且介电质的宽度在大约5-16nm的范围内。在另一实施例中,对于大约58nm的间距,金属线的宽度在大约45-54nm的范围内,并且介电质的宽度在大约4-13nm的范围内。在另一实施例中,对于大约48nm的间距,金属线的宽度在大约38-44.5nm的范围内,并且介电质的宽度在大约3.5-10nm的范围内。
图10A-C是根据本发明的实施例的底层上的金属线的示意性表示。图A是根据本发明实施例制造的半导体器件900的一部分的顶视图。另外,图10A相应于如上所述的图7的顶视图。如图所示,大量的第一金属线406、408和410由介电质504与周围的金属902相绝缘。如可以理解的,在该构造中,第二金属线708和706一起变短,并且必须彼此绝缘。参考图10B,蚀刻掩模920可应用于器件900,以隔离第二金属902的线708和706。在此蚀刻步骤中,仅第二金属可被掩蔽和蚀刻,或第一金属和第二金属两者都可被掩蔽和蚀刻。蚀刻至少进行到底层,在底层上保形介电层可沉积在所有的暴露表面上。可采用现有技术中公知的任何合适的介电层,而没有背离本发明。在一些实施例中,可采用Si3N4或SiO2作为介电层。然后可平坦化器件以在基本上平坦的表面处共同暴露金属线,如图10C所示。如图所示,诸如线406、408和410的第一组金属线和诸如708和706的第二组金属线由介电质934围绕。
图10A-C还示出了本发明如何能够减小工艺成本。导体406、408和410以间距P构图。因此这些导体的密度是1/P线每单位宽度。图10B中的结果具有2/P线每单位宽度的导体线密度。在传统的构图工艺中,该密度将需要以P/2的间距构图,这将需要使用本发明方法所需要的工艺工具的两倍能力的工艺工具。在示出的例子中需要附加的掩模920,但是图10B上的掩模920中形状的间距是2P。因而,通常需要一个具有P/2的间距能力的构图步骤的P/2的导体密度通过两个构图步骤制成,一个具有P的能力,一个具有2P的能力。构图工具的成本是它们的间距能力的强函数。因而,可以期望本发明的工艺比传统的工艺廉价。
图11是根据本发明实施例的在第一金属线1002和第二金属线708之间的连接1006的示例性例子。如上所述,第一组金属线可由第一金属层限定,并且第二组金属线可由第二金属层限定。如可以理解的,在一些实施例中,可期望将第一组金属线的一些部分连接到第二组金属线的一些部分。因而,在一些实施例中,可形成通路1006以连接第一金属线1002和第二金属线708。如可以理解的,可以以现有技术中公知的任何方式形成通路,而没有背离本发明。
虽然本发明根据多个优选的实施例进行了描述,但是仍然存在落入本发明的范围内的替换、置换和等效物。还应意识到,存在实施本发明的方法和设备的许多替换方式。例如,尽管参考了独立公开共面和非共面实施例的图7和图8,但是可以理解这些实施例不是相互排斥,并且在一些实施例中可相结合地使用,而没有背离本发明。尽管在此提供了各种例子,但是意图这些例子是示例性的,并且相对于本发明不是限制性的。另外,为了方便在此提供摘要,不应采用摘要以解释或限制在权利要求中表达的整个发明。因此所意图的是所附的权利要求解释为包括所有这样的落入本发明的真实精神和范围内的替换、置换和等效物。
前述详细说明已经描述了本发明可采取的许多形式中的仅仅一些形式。为此原因,该详细说明意图作为示例,而不是为了限定。仅仅包括所有等效物的所附权利要求意图限定本发明的范围。
Claims (14)
1.一种用于在底层上沉积至少两个金属层的方法,包括:
在所述底层上沉积第一金属层;
掩蔽所述第一金属层使得所述第一金属层包括第一被掩蔽的部分和第一未掩蔽的部分;
蚀刻所述第一金属层使得所述第一未掩蔽的部分去除到所述底层;
在所述第一金属层上和所述底层上沉积第一中间层;
在所述第一中间层上沉积第二金属层;
平坦化所述第二金属层以在第一平坦的表面处共同暴露所述第一中间层和所述第二金属层;
掩蔽所述第二金属层和所述第一中间层,使得所述第二金属层和所述第一中间层包括第二被掩蔽的部分和第二未掩蔽的部分;以及
蚀刻所述第二未掩蔽的部分至所述底层;
在所有经蚀刻的表面上沉积第二中间层;以及
平坦化所述第二中间层以在第二平坦的表面处共同暴露所述第二中间层和所述第一金属层。
2.根据权利要求1所述的方法,其中平坦化所述第二金属层将所述第一金属层在所述第一平坦的表面处与所述第二金属层和所述第一中间层共同暴露。
3.根据权利要求2所述的方法,其中:
掩蔽所述第二金属层和所述第一中间层包括掩蔽所述第一金属层,使得所述第一金属层、所述第二金属层和所述第一中间层包括第二被掩蔽的部分和第二未掩蔽的部分;以及
蚀刻所述第二未掩蔽的部分至所述底层包括蚀刻所述第一金属层。
4.根据权利要求3所述的方法,其中所述第一中间层包括Si3N4或SiO2,或所述第二中间层包括Si3N4或SiO2。
5.根据权利要求3所述的方法,其中通过化学机械抛光或回蚀来执行平坦化所述第二中间层。
6.根据权利要求4所述的方法,还包括:
将所述第一金属层的一部分与所述第二金属层的一部分电气连接。
7.根据权利要求1所述的方法,其中通过化学机械抛光或回蚀来执行平坦化所述第二金属层。
8.根据权利要求1所述的方法,其中所述第一金属层和所述第二金属层是相同的合成物。
9.根据权利要求1所述的方法,其中,在蚀刻所述第一金属层之后,所述第一金属层是多个平行的第一金属线的形式。
10.根据权利要求11所述的方法,其中,在平坦化所述第二金属层之后,所述第二金属层是多个平行的第二金属线的形式,所述第二金属线之中散布所述第一金属线。
11.根据权利要求1所述的方法,其中所述第一金属层是从由钨和铝组成的组中选择的合成物。
12.根据权利要求1所述的方法,其中所述第二金属层是从由钨、铝和铜组成的组中选择的合成物。
13.根据权利要求12所述的方法,当所述第二金属层是钨时,所述方法还包括:
在沉积所述第一中间层之后,在所述第一中间层上沉积第一保形附着层。
14.根据权利要求13所述的方法,其中所述第一保形附着层从由Ti、TiW和TiN组成的组中选择。
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-
2008
- 2008-06-26 TW TW097123943A patent/TWI371798B/zh not_active IP Right Cessation
- 2008-06-27 WO PCT/US2008/068499 patent/WO2009006263A2/en active Application Filing
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Also Published As
Publication number | Publication date |
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TW200917368A (en) | 2009-04-16 |
KR20100050478A (ko) | 2010-05-13 |
WO2009006263A3 (en) | 2009-03-12 |
US20090004844A1 (en) | 2009-01-01 |
US7927990B2 (en) | 2011-04-19 |
TWI371798B (en) | 2012-09-01 |
CN101730928A (zh) | 2010-06-09 |
WO2009006263A2 (en) | 2009-01-08 |
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